legup-4.0
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Properties Friends Macros Groups Pages
Public Types | Public Member Functions | Static Public Member Functions | Protected Member Functions | Private Member Functions | Private Attributes
llvm::X86TargetLowering Class Referencefinal

#include <X86ISelLowering.h>

+ Inheritance diagram for llvm::X86TargetLowering:

Public Types

enum  ConstraintType {
  C_Register, C_RegisterClass, C_Memory, C_Other,
  C_Unknown
}
 
enum  ConstraintWeight {
  CW_Invalid = -1, CW_Okay = 0, CW_Good = 1, CW_Better = 2,
  CW_Best = 3, CW_SpecificReg = CW_Okay, CW_Register = CW_Good, CW_Memory = CW_Better,
  CW_Constant = CW_Best, CW_Default = CW_Okay
}
 
typedef std::vector< ArgListEntry > ArgListTy
 
typedef std::vector
< AsmOperandInfo > 		AsmOperandInfoVector
 
enum  LegalizeAction { Legal, Promote, Expand, Custom }
 
enum  LegalizeTypeAction {
  TypeLegal, TypePromoteInteger, TypeExpandInteger, TypeSoftenFloat,
  TypeExpandFloat, TypeScalarizeVector, TypeSplitVector, TypeWidenVector
}
 
enum  BooleanContent { UndefinedBooleanContent, ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent }
 Enum that describes how the target represents true/false values. More...
 
enum  SelectSupportKind { ScalarValSelect, ScalarCondVectorVal, VectorMaskSelect }
 Enum that describes what type of support for selects the target has. More...
 
typedef std::pair
< LegalizeTypeAction, EVT > 		LegalizeKind
 

Public Member Functions

 X86TargetLowering (X86TargetMachine &TM)
 
unsigned getJumpTableEncoding () const override
 
MVT getScalarShiftAmountTy (EVT LHSTy) const override
 
const MCExpr * LowerCustomJumpTableEntry (const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override
 
SDValue getPICJumpTableRelocBase (SDValue Table, SelectionDAG &DAG) const override
 
const MCExpr * getPICJumpTableRelocBaseExpr (const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
 
unsigned getByValTypeAlignment (Type *Ty) const override
 
EVT getOptimalMemOpType (uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override
 
bool isSafeMemOpType (MVT VT) const override
 
bool allowsUnalignedMemoryAccesses (EVT VT, unsigned AS, bool *Fast) const override
 
SDValue LowerOperation (SDValue Op, SelectionDAG &DAG) const override
 
void ReplaceNodeResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
 
SDValue PerformDAGCombine (SDNode *N, DAGCombinerInfo &DCI) const override
 
bool isTypeDesirableForOp (unsigned Opc, EVT VT) const override
 
bool IsDesirableToPromoteOp (SDValue Op, EVT &PVT) const override
 
MachineBasicBlock * EmitInstrWithCustomInserter (MachineInstr *MI, MachineBasicBlock *MBB) const override
 
const char * getTargetNodeName (unsigned Opcode) const override
 
EVT getSetCCResultType (LLVMContext &Context, EVT VT) const override
 getSetCCResultType - Return the value type to use for ISD::SETCC. More...
 
void computeKnownBitsForTargetNode (const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override
 
unsigned ComputeNumSignBitsForTargetNode (SDValue Op, const SelectionDAG &DAG, unsigned Depth) const override
 
bool isGAPlusOffset (SDNode *N, const GlobalValue *&GA, int64_t &Offset) const override
 
SDValue getReturnAddressFrameIndex (SelectionDAG &DAG) const
 
bool ExpandInlineAsm (CallInst *CI) const override
 
ConstraintType getConstraintType (const std::string &Constraint) const override
 
ConstraintWeight getSingleConstraintMatchWeight (AsmOperandInfo &info, const char *constraint) const override
 
const char * LowerXConstraint (EVT ConstraintVT) const override
 
void LowerAsmOperandForConstraint (SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
 
std::pair< unsigned, const
TargetRegisterClass * > 		getRegForInlineAsmConstraint (const std::string &Constraint, MVT VT) const override
 
bool isLegalAddressingMode (const AddrMode &AM, Type *Ty) const override
 
bool isLegalICmpImmediate (int64_t Imm) const override
 
bool isLegalAddImmediate (int64_t Imm) const override
 
int getScalingFactorCost (const AddrMode &AM, Type *Ty) const override
 Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value. More...
 
bool isVectorShiftByScalarCheap (Type *Ty) const override
 
bool isTruncateFree (Type *Ty1, Type *Ty2) const override
 
bool isTruncateFree (EVT VT1, EVT VT2) const override
 
bool allowTruncateForTailCall (Type *Ty1, Type *Ty2) const override
 
bool isZExtFree (Type *Ty1, Type *Ty2) const override
 
bool isZExtFree (EVT VT1, EVT VT2) const override
 
bool isZExtFree (SDValue Val, EVT VT2) const override
 
bool isFMAFasterThanFMulAndFAdd (EVT VT) const override
 
bool isNarrowingProfitable (EVT VT1, EVT VT2) const override
 
bool isFPImmLegal (const APFloat &Imm, EVT VT) const override
 
bool isShuffleMaskLegal (const SmallVectorImpl< int > &Mask, EVT VT) const override
 
bool isVectorClearMaskLegal (const SmallVectorImpl< int > &Mask, EVT VT) const override
 
bool ShouldShrinkFPConstant (EVT VT) const override
 
const X86Subtarget * getSubtarget () const
 
bool isScalarFPTypeInSSEReg (EVT VT) const
 
bool isTargetFTOL () const
 
bool isIntegerTypeFTOL (EVT VT) const
 
bool shouldConvertConstantLoadToIntImm (const APInt &Imm, Type *Ty) const override
 Returns true if it is beneficial to convert a load of a constant to just the constant itself. More...
 
const char * getClearCacheBuiltinName () const override
 Intel processors have a unified instruction and data cache. More...
 
unsigned getRegisterByName (const char *RegName, EVT VT) const override
 
FastISel * createFastISel (FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override
 
bool getStackCookieLocation (unsigned &AddressSpace, unsigned &Offset) const override
 
SDValue BuildFILD (SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const
 
bool isNoopAddrSpaceCast (unsigned SrcAS, unsigned DestAS) const override
 
void resetOperationActions () override
 Reset the operation actions based on target options. More...
 
LegalizeTypeAction getPreferredVectorAction (EVT VT) const override
 Customize the preferred legalization strategy for certain types. More...
 
virtual bool getPreIndexedAddressParts (SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
 
virtual bool getPostIndexedAddressParts (SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const
 
virtual bool isOffsetFoldingLegal (const GlobalAddressSDNode *GA) const
 
bool isInTailCallPosition (SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const
 
void softenSetCCOperands (SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const
 
std::pair< SDValue, SDValue > makeLibCall (SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
 Returns a pair of (return value, chain). More...
 
bool SimplifyDemandedBits (SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
 
bool isConstTrueVal (const SDNode *N) const
 
bool isConstFalseVal (const SDNode *N) const
 
SDValue SimplifySetCC (EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const
 
virtual bool isDesirableToCommuteWithShift (const SDNode *N) const
 Return true if it is profitable to move a following shift through this. More...
 
virtual bool isDesirableToTransformToIntegerOp (unsigned, EVT) const
 
std::pair< SDValue, SDValue > LowerCallTo (CallLoweringInfo &CLI) const
 
virtual void HandleByVal (CCState *, unsigned &, unsigned) const
 Target-specific cleanup for formal ByVal parameters. More...
 
virtual bool functionArgumentNeedsConsecutiveRegisters (Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
 
virtual SDValue prepareVolatileOrAtomicLoad (SDValue Chain, SDLoc DL, SelectionDAG &DAG) const
 
virtual void LowerOperationWrapper (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
 
bool verifyReturnAddressArgumentIsConstant (SDValue Op, SelectionDAG &DAG) const
 
virtual AsmOperandInfoVector ParseConstraints (ImmutableCallSite CS) const
 
virtual ConstraintWeight getMultipleConstraintMatchWeight (AsmOperandInfo &info, int maIndex) const
 
virtual void ComputeConstraintToUse (AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
 
SDValue BuildExactSDIV (SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const
 Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant. More...
 
SDValue BuildSDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
 Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...
 
SDValue BuildUDIV (SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const
 Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html More...
 
bool expandMUL (SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const
 
bool expandFP_TO_SINT (SDNode *N, SDValue &Result, SelectionDAG &DAG) const
 
virtual void AdjustInstrPostInstrSelection (MachineInstr *MI, SDNode *Node) const
 
const TargetMachine & getTargetMachine () const
 
const DataLayout * getDataLayout () const
 
const TargetLoweringObjectFile & getObjFileLowering () const
 
bool isBigEndian () const
 
bool isLittleEndian () const
 
virtual MVT getPointerTy (uint32_t=0) const
 
unsigned getPointerSizeInBits (uint32_t AS=0) const
 
unsigned getPointerTypeSizeInBits (Type *Ty) const
 
EVT getShiftAmountTy (EVT LHSTy) const
 
virtual MVT getVectorIdxTy () const
 
bool isSelectExpensive () const
 Return true if the select operation is expensive for this target. More...
 
virtual bool isSelectSupported (SelectSupportKind) const
 
bool hasMultipleConditionRegisters () const
 Return true if multiple condition registers are available. More...
 
bool hasExtractBitsInsn () const
 Return true if the target has BitExtract instructions. More...
 
virtual bool shouldExpandBuildVectorWithShuffles (EVT, unsigned DefinedValues) const
 
bool isIntDivCheap () const
 
bool isSlowDivBypassed () const
 Returns true if target has indicated at least one type should be bypassed. More...
 
const DenseMap< unsigned int,
unsigned int > & 		getBypassSlowDivWidths () const
 
bool isPow2DivCheap () const
 Return true if pow2 div is cheaper than a chain of srl/add/sra. More...
 
bool isJumpExpensive () const
 
bool isPredictableSelectExpensive () const
 
virtual bool isLoadBitCastBeneficial (EVT, EVT) const
 
bool isMaskAndBranchFoldingLegal () const
 Return if the target supports combining a chain like: More...
 
virtual MVT::SimpleValueType getCmpLibcallReturnType () const
 
BooleanContent getBooleanContents (bool isVec, bool isFloat) const
 
BooleanContent getBooleanContents (EVT Type) const
 
Sched::Preference getSchedulingPreference () const
 Return target scheduling preference. More...
 
virtual Sched::Preference getSchedulingPreference (SDNode *) const
 
virtual const TargetRegisterClass * getRegClassFor (MVT VT) const
 
virtual const TargetRegisterClass * getRepRegClassFor (MVT VT) const
 
virtual uint8_t getRepRegClassCostFor (MVT VT) const
 
bool isTypeLegal (EVT VT) const
 
const ValueTypeActionImpl & getValueTypeActions () const
 
LegalizeTypeAction getTypeAction (LLVMContext &Context, EVT VT) const
 
LegalizeTypeAction getTypeAction (MVT VT) const
 
EVT getTypeToTransformTo (LLVMContext &Context, EVT VT) const
 
EVT getTypeToExpandTo (LLVMContext &Context, EVT VT) const
 
unsigned getVectorTypeBreakdown (LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
 
virtual bool getTgtMemIntrinsic (IntrinsicInfo &, const CallInst &, unsigned) const
 
virtual bool canOpTrap (unsigned Op, EVT VT) const
 
LegalizeAction getOperationAction (unsigned Op, EVT VT) const
 
bool isOperationLegalOrCustom (unsigned Op, EVT VT) const
 
bool isOperationLegalOrPromote (unsigned Op, EVT VT) const
 
bool isOperationExpand (unsigned Op, EVT VT) const
 
bool isOperationLegal (unsigned Op, EVT VT) const
 Return true if the specified operation is legal on this target. More...
 
LegalizeAction getLoadExtAction (unsigned ExtType, MVT VT) const
 
bool isLoadExtLegal (unsigned ExtType, EVT VT) const
 Return true if the specified load with extension is legal on this target. More...
 
LegalizeAction getTruncStoreAction (MVT ValVT, MVT MemVT) const
 
bool isTruncStoreLegal (EVT ValVT, EVT MemVT) const
 
LegalizeAction getIndexedLoadAction (unsigned IdxMode, MVT VT) const
 
bool isIndexedLoadLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getIndexedStoreAction (unsigned IdxMode, MVT VT) const
 
bool isIndexedStoreLegal (unsigned IdxMode, EVT VT) const
 Return true if the specified indexed load is legal on this target. More...
 
LegalizeAction getCondCodeAction (ISD::CondCode CC, MVT VT) const
 
bool isCondCodeLegal (ISD::CondCode CC, MVT VT) const
 Return true if the specified condition code is legal on this target. More...
 
MVT getTypeToPromoteTo (unsigned Op, MVT VT) const
 
EVT getValueType (Type *Ty, bool AllowUnknown=false) const
 
MVT getSimpleValueType (Type *Ty, bool AllowUnknown=false) const
 Return the MVT corresponding to this LLVM type. See getValueType. More...
 
MVT getRegisterType (MVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
MVT getRegisterType (LLVMContext &Context, EVT VT) const
 Return the type of registers that this ValueType will eventually require. More...
 
unsigned getNumRegisters (LLVMContext &Context, EVT VT) const
 
bool hasBigEndianPartOrdering (EVT VT) const
 
bool hasTargetDAGCombine (ISD::NodeType NT) const
 
unsigned getMaxStoresPerMemset (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memset. More...
 
unsigned getMaxStoresPerMemcpy (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memcpy. More...
 
unsigned getMaxStoresPerMemmove (bool OptSize) const
 Get maximum # of store operations permitted for llvm.memmove. More...
 
bool usesUnderscoreSetJmp () const
 Determine if we should use _setjmp or setjmp to implement llvm.setjmp. More...
 
bool usesUnderscoreLongJmp () const
 Determine if we should use _longjmp or longjmp to implement llvm.longjmp. More...
 
bool supportJumpTables () const
 Return whether the target can generate code for jump tables. More...
 
int getMinimumJumpTableEntries () const
 
unsigned getStackPointerRegisterToSaveRestore () const
 
unsigned getExceptionPointerRegister () const
 
unsigned getExceptionSelectorRegister () const
 
unsigned getJumpBufSize () const
 
unsigned getJumpBufAlignment () const
 
unsigned getMinStackArgumentAlignment () const
 Return the minimum stack alignment of an argument. More...
 
unsigned getMinFunctionAlignment () const
 Return the minimum function alignment. More...
 
unsigned getPrefFunctionAlignment () const
 Return the preferred function alignment. More...
 
unsigned getPrefLoopAlignment () const
 Return the preferred loop alignment. More...
 
bool getInsertFencesForAtomic () const
 
virtual unsigned getMaximalGlobalOffset () const
 
Helpers for TargetTransformInfo implementations
int InstructionOpcodeToISD (unsigned Opcode) const
 Get the ISD node that corresponds to the Instruction class opcode. More...
 
std::pair< unsigned, MVT > getTypeLegalizationCost (Type *Ty) const
 Estimate the cost of type-legalization and the legalized type. More...
 

Static Public Member Functions

static ISD::NodeType getExtendForContent (BooleanContent Content)
 

Protected Member Functions

std::pair< const
TargetRegisterClass *, uint8_t > 		findRepresentativeClass (MVT VT) const override
 
void initActions ()
 Initialize all of the actions to default values. More...
 

Private Member Functions

void addLegalFPImmediate (const APFloat &Imm)
 
SDValue LowerCallResult (SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
 
SDValue LowerMemArgument (SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl< ISD::InputArg > &ArgInfo, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, unsigned i) const
 
SDValue LowerMemOpCallTo (SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
 
bool IsEligibleForTailCallOptimization (SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
 
bool IsCalleePop (bool isVarArg, CallingConv::ID CallConv) const
 
SDValue EmitTailCallLoadRetAddr (SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall, bool Is64Bit, int FPDiff, SDLoc dl) const
 
unsigned GetAlignedArgumentStackSize (unsigned StackSize, SelectionDAG &DAG) const
 
std::pair< SDValue, SDValue > FP_TO_INTHelper (SDValue Op, SelectionDAG &DAG, bool isSigned, bool isReplace) const
 
SDValue LowerBUILD_VECTOR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerBUILD_VECTORvXi1 (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVECTOR_SHUFFLE (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVSELECT (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerEXTRACT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG) const
 
SDValue ExtractBitFromMaskVector (SDValue Op, SelectionDAG &DAG) const
 
SDValue InsertBitToMaskVector (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerINSERT_VECTOR_ELT (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerConstantPool (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerBlockAddress (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerGlobalAddress (const GlobalValue *GV, SDLoc dl, int64_t Offset, SelectionDAG &DAG) const
 
SDValue LowerGlobalAddress (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerGlobalTLSAddress (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerExternalSymbol (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSINT_TO_FP (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerUINT_TO_FP (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerUINT_TO_FP_i64 (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerUINT_TO_FP_i32 (SDValue Op, SelectionDAG &DAG) const
 
SDValue lowerUINT_TO_FP_vec (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerTRUNCATE (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFP_TO_SINT (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFP_TO_UINT (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerToBT (SDValue And, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG) const
 
SDValue LowerSETCC (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSELECT (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerBRCOND (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerMEMSET (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerJumpTable (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerDYNAMIC_STACKALLOC (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVASTART (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerVAARG (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerRETURNADDR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFRAMEADDR (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFRAME_TO_ARGS_OFFSET (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerEH_RETURN (SDValue Op, SelectionDAG &DAG) const
 
SDValue lowerEH_SJLJ_SETJMP (SDValue Op, SelectionDAG &DAG) const
 
SDValue lowerEH_SJLJ_LONGJMP (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerINIT_TRAMPOLINE (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFLT_ROUNDS_ (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerSIGN_EXTEND_INREG (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerWin64_i128OP (SDValue Op, SelectionDAG &DAG) const
 
SDValue LowerFormalArguments (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
 
SDValue LowerCall (CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
 
SDValue LowerReturn (SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, SDLoc dl, SelectionDAG &DAG) const override
 
bool isUsedByReturnOnly (SDNode *N, SDValue &Chain) const override
 
bool mayBeEmittedAsTailCall (CallInst *CI) const override
 
MVT getTypeForExtArgOrReturn (MVT VT, ISD::NodeType ExtendKind) const override
 
bool CanLowerReturn (CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
 
const MCPhysReg * getScratchRegisters (CallingConv::ID CC) const override
 
MachineBasicBlock * EmitAtomicLoadArith (MachineInstr *MI, MachineBasicBlock *MBB) const
 
MachineBasicBlock * EmitAtomicLoadArith6432 (MachineInstr *MI, MachineBasicBlock *MBB) const
 
MachineBasicBlock * EmitVAARG64WithCustomInserter (MachineInstr *MI, MachineBasicBlock *MBB) const
 
MachineBasicBlock * EmitVAStartSaveXMMRegsWithCustomInserter (MachineInstr *BInstr, MachineBasicBlock *BB) const
 Utility function to emit the xmm reg save portion of va_start. More...
 
MachineBasicBlock * EmitLoweredSelect (MachineInstr *I, MachineBasicBlock *BB) const
 
MachineBasicBlock * EmitLoweredWinAlloca (MachineInstr *MI, MachineBasicBlock *BB) const
 
MachineBasicBlock * EmitLoweredSegAlloca (MachineInstr *MI, MachineBasicBlock *BB, bool Is64Bit) const
 
MachineBasicBlock * EmitLoweredTLSCall (MachineInstr *MI, MachineBasicBlock *BB) const
 
MachineBasicBlock * emitLoweredTLSAddr (MachineInstr *MI, MachineBasicBlock *BB) const
 
MachineBasicBlock * emitEHSjLjSetJmp (MachineInstr *MI, MachineBasicBlock *MBB) const
 
MachineBasicBlock * emitEHSjLjLongJmp (MachineInstr *MI, MachineBasicBlock *MBB) const
 
MachineBasicBlock * emitFMA3Instr (MachineInstr *MI, MachineBasicBlock *MBB) const
 
SDValue EmitTest (SDValue Op0, unsigned X86CC, SDLoc dl, SelectionDAG &DAG) const
 
SDValue EmitCmp (SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl, SelectionDAG &DAG) const
 
SDValue ConvertCmpIfNecessary (SDValue Cmp, SelectionDAG &DAG) const
 Convert a comparison if required by the subtarget. More...
 

Private Attributes

const X86Subtarget * Subtarget
 
const DataLayout * TD
 
TargetOptions TO
 
bool X86ScalarSSEf32
 
bool X86ScalarSSEf64
 
std::vector< APFloat > LegalFPImmediates
 LegalFPImmediates - A list of legal fp immediates. More...
 

Helpers for load-linked/store-conditional atomic expansion.

virtual Value * emitLoadLinked (IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const
 
virtual Value * emitStoreConditional (IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const
 
virtual bool shouldExpandAtomicInIR (Instruction *Inst) const
 
virtual bool GetAddrModeArguments (IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const
 
virtual bool hasPairedLoad (Type *, unsigned &) const
 
virtual bool hasPairedLoad (EVT, unsigned &) const
 Specify maximum number of store instructions per memset call. More...
 
virtual bool isFNegFree (EVT VT) const
 
virtual bool isFAbsFree (EVT VT) const
 
void setLibcallName (RTLIB::Libcall Call, const char *Name)
 Rename the default libcall routine name for the specified libcall. More...
 
const char * getLibcallName (RTLIB::Libcall Call) const
 Get the libcall routine name for the specified libcall. More...
 
void setCmpLibcallCC (RTLIB::Libcall Call, ISD::CondCode CC)
 
ISD::CondCode getCmpLibcallCC (RTLIB::Libcall Call) const
 
void setLibcallCallingConv (RTLIB::Libcall Call, CallingConv::ID CC)
 Set the CallingConv that should be used for the specified libcall. More...
 
CallingConv::ID getLibcallCallingConv (RTLIB::Libcall Call) const
 Get the CallingConv that should be used for the specified libcall. More...
 
LegalizeKind getTypeConversion (LLVMContext &Context, EVT VT) const
 Reset the operation actions based on target options. More...
 
void setBooleanContents (BooleanContent Ty)
 
void setBooleanContents (BooleanContent IntTy, BooleanContent FloatTy)
 
void setBooleanVectorContents (BooleanContent Ty)
 
void setSchedulingPreference (Sched::Preference Pref)
 Specify the target scheduling preference. More...
 
void setUseUnderscoreSetJmp (bool Val)
 
void setUseUnderscoreLongJmp (bool Val)
 
void setSupportJumpTables (bool Val)
 Indicate whether the target can generate code for jump tables. More...
 
void setMinimumJumpTableEntries (int Val)
 
void setStackPointerRegisterToSaveRestore (unsigned R)
 
void setExceptionPointerRegister (unsigned R)
 
void setExceptionSelectorRegister (unsigned R)
 
void setSelectIsExpensive (bool isExpensive=true)
 
void setHasMultipleConditionRegisters (bool hasManyRegs=true)
 
void setHasExtractBitsInsn (bool hasExtractInsn=true)
 
void setJumpIsExpensive (bool isExpensive=true)
 
void setIntDivIsCheap (bool isCheap=true)
 
void addBypassSlowDiv (unsigned int SlowBitWidth, unsigned int FastBitWidth)
 Tells the code generator which bitwidths to bypass. More...
 
void setPow2DivIsCheap (bool isCheap=true)
 
void addRegisterClass (MVT VT, const TargetRegisterClass *RC)
 
void clearRegisterClasses ()
 Remove all register classes. More...
 
void clearOperationActions ()
 Remove all operation actions. More...
 
void computeRegisterProperties ()
 
void setOperationAction (unsigned Op, MVT VT, LegalizeAction Action)
 
void setLoadExtAction (unsigned ExtType, MVT VT, LegalizeAction Action)
 
void setTruncStoreAction (MVT ValVT, MVT MemVT, LegalizeAction Action)
 
void setIndexedLoadAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 
void setIndexedStoreAction (unsigned IdxMode, MVT VT, LegalizeAction Action)
 
void setCondCodeAction (ISD::CondCode CC, MVT VT, LegalizeAction Action)
 
void AddPromotedToType (unsigned Opc, MVT OrigVT, MVT DestVT)
 
void setTargetDAGCombine (ISD::NodeType NT)
 
void setJumpBufSize (unsigned Size)
 Set the target's required jmp_buf buffer size (in bytes); default is 200. More...
 
void setJumpBufAlignment (unsigned Align)
 
void setMinFunctionAlignment (unsigned Align)
 Set the target's minimum function alignment (in log2(bytes)) More...
 
void setPrefFunctionAlignment (unsigned Align)
 
void setPrefLoopAlignment (unsigned Align)
 
void setMinStackArgumentAlignment (unsigned Align)
 Set the minimum stack alignment of an argument (in log2(bytes)). More...
 
void setInsertFencesForAtomic (bool fence)
 
bool isLegalRC (const TargetRegisterClass *RC) const
 
MachineBasicBlock * emitPatchPoint (MachineInstr *MI, MachineBasicBlock *MBB) const
 
unsigned MaxStoresPerMemset
 Specify maximum number of store instructions per memset call. More...
 
unsigned MaxStoresPerMemsetOptSize
 
unsigned MaxStoresPerMemcpy
 Specify maximum bytes of store instructions per memcpy call. More...
 
unsigned MaxStoresPerMemcpyOptSize
 
unsigned MaxStoresPerMemmove
 Specify maximum bytes of store instructions per memmove call. More...
 
unsigned MaxStoresPerMemmoveOptSize
 
bool PredictableSelectIsExpensive
 
bool MaskAndBranchFoldingIsLegal
 

Detailed Description

Definition at line 518 of file X86ISelLowering.h.

Member Typedef Documentation

typedef std::vector<ArgListEntry> llvm::TargetLowering::ArgListTy
inherited

Definition at line 2126 of file TargetLowering.h.

typedef std::vector<AsmOperandInfo> llvm::TargetLowering::AsmOperandInfoVector
inherited

Definition at line 2484 of file TargetLowering.h.

typedef std::pair<LegalizeTypeAction, EVT> llvm::TargetLoweringBase::LegalizeKind
inherited

LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.

Definition at line 106 of file TargetLowering.h.

Member Enumeration Documentation

enum llvm::TargetLoweringBase::BooleanContent
inherited

Enum that describes how the target represents true/false values.

Enumerator
UndefinedBooleanContent 
ZeroOrOneBooleanContent 
ZeroOrNegativeOneBooleanContent 

Definition at line 109 of file TargetLowering.h.

109  {
110  UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
111  ZeroOrOneBooleanContent, // All bits zero except for bit 0.
112  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
113  };
enum llvm::TargetLowering::ConstraintType
inherited
Enumerator
C_Register 
C_RegisterClass 
C_Memory 
C_Other 
C_Unknown 

Definition at line 2425 of file TargetLowering.h.

2425  {
2426  C_Register, // Constraint represents specific register(s).
2427  C_RegisterClass, // Constraint represents any of register(s) in class.
2428  C_Memory, // Memory constraint.
2429  C_Other, // Something else.
2430  C_Unknown // Unsupported constraint.
2431  };
enum llvm::TargetLowering::ConstraintWeight
inherited
Enumerator
CW_Invalid 
CW_Okay 
CW_Good 
CW_Better 
CW_Best 
CW_SpecificReg 
CW_Register 
CW_Memory 
CW_Constant 
CW_Default 

Definition at line 2433 of file TargetLowering.h.

2433  {
2434  // Generic weights.
2435  CW_Invalid = -1, // No match.
2436  CW_Okay = 0, // Acceptable.
2437  CW_Good = 1, // Good weight.
2438  CW_Better = 2, // Better weight.
2439  CW_Best = 3, // Best weight.
2440 
2441  // Well-known weights.
2442  CW_SpecificReg = CW_Okay, // Specific register operands.
2443  CW_Register = CW_Good, // Register operands.
2444  CW_Memory = CW_Better, // Memory operands.
2445  CW_Constant = CW_Best, // Constant operand.
2446  CW_Default = CW_Okay // Default or don't know type.
2447  };
enum llvm::TargetLoweringBase::LegalizeAction
inherited

This enum indicates whether operations are valid for a target, and if not, what action should be used to make them valid.

Enumerator
Legal 
Promote 
Expand 
Custom 

Definition at line 84 of file TargetLowering.h.

84  {
85  Legal, // The target natively supports this operation.
86  Promote, // This operation should be executed in a larger type.
87  Expand, // Try to expand this to other ops, otherwise use a libcall.
88  Custom // Use the LowerOperation hook to implement custom lowering.
89  };
enum llvm::TargetLoweringBase::LegalizeTypeAction
inherited

This enum indicates whether a types are legal for a target, and if not, what action should be used to make them valid.

Enumerator
TypeLegal 
TypePromoteInteger 
TypeExpandInteger 
TypeSoftenFloat 
TypeExpandFloat 
TypeScalarizeVector 
TypeSplitVector 
TypeWidenVector 

Definition at line 93 of file TargetLowering.h.

93  {
94  TypeLegal, // The target natively supports this type.
95  TypePromoteInteger, // Replace this integer with a larger one.
96  TypeExpandInteger, // Split this integer into two of half the size.
97  TypeSoftenFloat, // Convert this float to a same size integer type.
98  TypeExpandFloat, // Split this float into two of half the size.
99  TypeScalarizeVector, // Replace this one-element vector with its element.
100  TypeSplitVector, // Split this vector into two of half the size.
101  TypeWidenVector // This vector should be widened into a larger vector.
102  };
enum llvm::TargetLoweringBase::SelectSupportKind
inherited

Enum that describes what type of support for selects the target has.

Enumerator
ScalarValSelect 
ScalarCondVectorVal 
VectorMaskSelect 

Definition at line 116 of file TargetLowering.h.

116  {
117  ScalarValSelect, // The target supports scalar selects (ex: cmov).
118  ScalarCondVectorVal, // The target supports selects with a scalar condition
119  // and vector values (ex: cmov).
120  VectorMaskSelect // The target supports vector selects with a vector
121  // mask (ex: x86 blends).
122  };

Constructor & Destructor Documentation

X86TargetLowering::X86TargetLowering ( X86TargetMachine &  TM)
explicit

Definition at line 214 of file X86ISelLowering.cpp.

215  : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
216  Subtarget = &TM.getSubtarget<X86Subtarget>();
217  X86ScalarSSEf64 = Subtarget->hasSSE2();
218  X86ScalarSSEf32 = Subtarget->hasSSE1();
219  TD = getDataLayout();
220 
221  resetOperationActions();
222 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86Subtarget::hasSSE2
bool hasSSE2() const
Definition: X86Subtarget.h:312
llvm::TargetLoweringBase::getDataLayout
const DataLayout * getDataLayout() const
Definition: TargetLowering.h:150
llvm::TargetLowering::TargetLowering
TargetLowering(const TargetLowering &) LLVM_DELETED_FUNCTION
llvm::TargetMachine::getSubtarget
const STC & getSubtarget() const
Definition: Target/TargetMachine.h:135
llvm::TargetMachine::getTargetTriple
const StringRef getTargetTriple() const
Definition: Target/TargetMachine.h:94
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:311
createTLOF
static TargetLoweringObjectFile * createTLOF(const Triple &TT)
Definition: X86ISelLowering.cpp:194
llvm::X86TargetLowering::resetOperationActions
void resetOperationActions() override
Reset the operation actions based on target options.
Definition: X86ISelLowering.cpp:224
llvm::X86TargetLowering::TD
const DataLayout * TD
Definition: X86ISelLowering.h:810

Member Function Documentation

void llvm::TargetLoweringBase::addBypassSlowDiv ( unsigned int  SlowBitWidth,
unsigned int  FastBitWidth 
)
inlineprotectedinherited

Tells the code generator which bitwidths to bypass.

Definition at line 1063 of file TargetLowering.h.

1063  {
1064  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1065  }
llvm::TargetLoweringBase::BypassSlowDivWidths
DenseMap< unsigned int, unsigned int > BypassSlowDivWidths
Definition: TargetLowering.h:1486
void llvm::X86TargetLowering::addLegalFPImmediate ( const APFloat &  Imm)
inlineprivate

addLegalFPImmediate - Indicate that this x86 target can instruction select the specified FP immediate natively.

Definition at line 828 of file X86ISelLowering.h.

828  {
829  LegalFPImmediates.push_back(Imm);
830  }
llvm::X86TargetLowering::LegalFPImmediates
std::vector< APFloat > LegalFPImmediates
LegalFPImmediates - A list of legal fp immediates.
Definition: X86ISelLowering.h:824
void llvm::TargetLoweringBase::AddPromotedToType ( unsigned  Opc,
MVT  OrigVT,
MVT  DestVT 
)
inlineprotectedinherited

If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/fp until it can find one that works. If that default is insufficient, this method can be used by the target to override the default.

Definition at line 1173 of file TargetLowering.h.

1173  {
1174  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1175  }
llvm::TargetLoweringBase::PromoteToType
std::map< std::pair< unsigned, MVT::SimpleValueType >, MVT::SimpleValueType > PromoteToType
Definition: TargetLowering.h:1774
void llvm::TargetLoweringBase::addRegisterClass ( MVT  VT,
const TargetRegisterClass *  RC 
)
inlineprotectedinherited

Add the specified register class as an available regclass for the specified value type. This indicates the selector can handle values of that class natively.

Definition at line 1074 of file TargetLowering.h.

1074  {
1075  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1076  AvailableRegClasses.push_back(std::make_pair(VT, RC));
1077  RegClassForVT[VT.SimpleTy] = RC;
1078  }
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::AvailableRegClasses
std::vector< std::pair< MVT, const TargetRegisterClass * > > AvailableRegClasses
True if this is a little endian target.
Definition: TargetLowering.h:1759
llvm::TargetLoweringBase::RegClassForVT
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1569
void TargetLowering::AdjustInstrPostInstrSelection ( MachineInstr *  MI,
SDNode *  Node 
) const
virtualinherited

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag. These instructions must be adjusted after instruction selection by target hooks. e.g. To fill in optional defs for ARM 's' setting instructions.

Reimplemented in llvm::ARMTargetLowering, and llvm::SITargetLowering.

Definition at line 325 of file SelectionDAGISel.cpp.

326  {
327  assert(!MI->hasPostISelHook() &&
328  "If a target marks an instruction with 'hasPostISelHook', "
329  "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
330 }
llvm::MachineInstr::hasPostISelHook
bool hasPostISelHook(QueryType Type=IgnoreBundle) const
Definition: MachineInstr.h:595
assert
assert(Globals.size() > 1)
bool X86TargetLowering::allowsUnalignedMemoryAccesses ( EVT  VT,
unsigned  AS,
bool *  Fast 
) const
overridevirtual

allowsUnalignedMemoryAccesses - Returns true if the target allows unaligned memory accesses. of the specified type. Returns whether it is "fast" by reference in the second argument.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1745 of file X86ISelLowering.cpp.

1747  {
1748  if (Fast)
1749  *Fast = Subtarget->isUnalignedMemAccessFast();
1750  return true;
1751 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86Subtarget::isUnalignedMemAccessFast
bool isUnalignedMemAccessFast() const
Definition: X86Subtarget.h:348
bool X86TargetLowering::allowTruncateForTailCall ( Type *  Ty1,
Type *  Ty2 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16764 of file X86ISelLowering.cpp.

16764  {
16765  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
16766  return false;
16767 
16768  if (!isTypeLegal(EVT::getEVT(Ty1)))
16769  return false;
16770 
16771  assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
16772 
16773  // Assuming the caller doesn't have a zeroext or signext return parameter,
16774  // truncation all the way down to i1 is valid.
16775  return true;
16776 }
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
assert
assert(Globals.size() > 1)
llvm::Type::isIntegerTy
bool isIntegerTy() const
Definition: Type.h:193
llvm::EVT::getEVT
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Definition: ValueTypes.cpp:275
llvm::Type::getPrimitiveSizeInBits
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
SDValue TargetLowering::BuildExactSDIV ( SDValue  Op1,
SDValue  Op2,
SDLoc  dl,
SelectionDAG &  DAG 
) const
inherited

Given an exact SDIV by a constant, create a multiplication with the multiplicative inverse of the constant.

Definition at line 2617 of file TargetLowering.cpp.

2618  {
2619  ConstantSDNode *C = cast<ConstantSDNode>(Op2);
2620  APInt d = C->getAPIntValue();
2621  assert(d != 0 && "Division by zero!");
2622 
2623  // Shift the value upfront if it is even, so the LSB is one.
2624  unsigned ShAmt = d.countTrailingZeros();
2625  if (ShAmt) {
2626  // TODO: For UDIV use SRL instead of SRA.
2627  SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
2628  Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, false, false,
2629  true);
2630  d = d.ashr(ShAmt);
2631  }
2632 
2633  // Calculate the multiplicative inverse, using Newton's method.
2634  APInt t, xn = d;
2635  while ((t = d*xn) != 1)
2636  xn *= APInt(d.getBitWidth(), 2) - t;
2637 
2638  Op2 = DAG.getConstant(xn, Op1.getValueType());
2639  return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2640 }
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy) const
Definition: TargetLoweringBase.cpp:860
llvm::ConstantSDNode::getAPIntValue
const APInt & getAPIntValue() const
Definition: SelectionDAGNodes.h:1349
d
int d()
Definition: dwarfdump-test4-part2.cc:2
assert
assert(Globals.size() > 1)
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
SDValue X86TargetLowering::BuildFILD ( SDValue  Op,
EVT  SrcVT,
SDValue  Chain,
SDValue  StackSlot,
SelectionDAG &  DAG 
) const

Definition at line 10708 of file X86ISelLowering.cpp.

10710  {
10711  // Build the FILD
10712  SDLoc DL(Op);
10713  SDVTList Tys;
10714  bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
10715  if (useSSE)
10716  Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
10717  else
10718  Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
10719 
10720  unsigned ByteSize = SrcVT.getSizeInBits()/8;
10721 
10722  FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
10723  MachineMemOperand *MMO;
10724  if (FI) {
10725  int SSFI = FI->getIndex();
10726  MMO =
10727  DAG.getMachineFunction()
10728  .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10729  MachineMemOperand::MOLoad, ByteSize, ByteSize);
10730  } else {
10731  MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
10732  StackSlot = StackSlot.getOperand(1);
10733  }
10734  SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
10735  SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
10736  X86ISD::FILD, DL,
10737  Tys, Ops, SrcVT, MMO);
10738 
10739  if (useSSE) {
10740  Chain = Result.getValue(1);
10741  SDValue InFlag = Result.getValue(2);
10742 
10743  // FIXME: Currently the FST is flagged to the FILD_FLAG. This
10744  // shouldn't be necessary except that RFP cannot be live across
10745  // multiple blocks. When stackifier is fixed, they can be uncoupled.
10746  MachineFunction &MF = DAG.getMachineFunction();
10747  unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
10748  int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
10749  SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10750  Tys = DAG.getVTList(MVT::Other);
10751  SDValue Ops[] = {
10752  Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
10753  };
10754  MachineMemOperand *MMO =
10755  DAG.getMachineFunction()
10756  .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10757  MachineMemOperand::MOStore, SSFISize, SSFISize);
10758 
10759  Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
10760  Ops, Op.getValueType(), MMO);
10761  Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
10762  MachinePointerInfo::getFixedStack(SSFI),
10763  false, false, false, 0);
10764  }
10765 
10766  return Result;
10767 }
llvm::MachineMemOperand::MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:101
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::MachineMemOperand::MOStore
The memory access writes data.
Definition: MachineMemOperand.h:103
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
Definition: MachineInstr.cpp:414
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::dyn_cast
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: MachineFunction.cpp:230
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Definition: MachineFunction.cpp:513
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getMemIntrinsicNode
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true)
Definition: SelectionDAG.cpp:4586
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1297
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1419
llvm::X86TargetLowering::isScalarFPTypeInSSEReg
bool isScalarFPTypeInSSEReg(EVT VT) const
Definition: X86ISelLowering.h:752
SDValue TargetLowering::BuildSDIV ( SDNode *  N,
const APInt &  Divisor,
SelectionDAG &  DAG,
bool  IsAfterLegalization,
std::vector< SDNode * > *  Created 
) const
inherited

Given an ISD::SDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html

Definition at line 2646 of file TargetLowering.cpp.

2648  {
2649  EVT VT = N->getValueType(0);
2650  SDLoc dl(N);
2651 
2652  // Check to see if we can do this.
2653  // FIXME: We should be more aggressive here.
2654  if (!isTypeLegal(VT))
2655  return SDValue();
2656 
2657  APInt::ms magics = Divisor.magic();
2658 
2659  // Multiply the numerator (operand 0) by the magic value
2660  // FIXME: We should support doing a MUL in a wider type
2661  SDValue Q;
2662  if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2663  isOperationLegalOrCustom(ISD::MULHS, VT))
2664  Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2665  DAG.getConstant(magics.m, VT));
2666  else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2667  isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2668  Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2669  N->getOperand(0),
2670  DAG.getConstant(magics.m, VT)).getNode(), 1);
2671  else
2672  return SDValue(); // No mulhs or equvialent
2673  // If d > 0 and m < 0, add the numerator
2674  if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2675  Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2676  if (Created)
2677  Created->push_back(Q.getNode());
2678  }
2679  // If d < 0 and m > 0, subtract the numerator.
2680  if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2681  Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2682  if (Created)
2683  Created->push_back(Q.getNode());
2684  }
2685  // Shift right algebraic if shift value is nonzero
2686  if (magics.s > 0) {
2687  Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2688  DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2689  if (Created)
2690  Created->push_back(Q.getNode());
2691  }
2692  // Extract the sign bit and add it to the quotient
2693  SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
2694  DAG.getConstant(VT.getScalarSizeInBits() - 1,
2695  getShiftAmountTy(Q.getValueType())));
2696  if (Created)
2697  Created->push_back(T.getNode());
2698  return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2699 }
llvm::APInt::ms::s
unsigned s
shift amount
Definition: APInt.h:1699
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:592
llvm::APInt::magic
ms magic() const
Definition: APInt.cpp:1396
llvm::APInt::isNegative
bool isNegative() const
Determine sign of this APInt.
Definition: APInt.h:320
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy) const
Definition: TargetLoweringBase.cpp:860
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Definition: SelectionDAGNodes.h:648
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
T
#define T
Definition: Mips16ISelLowering.cpp:349
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::EVT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:240
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
llvm::TargetLoweringBase::isOperationLegalOrCustom
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Definition: TargetLowering.h:489
llvm::TargetLoweringBase::isOperationLegal
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
Definition: TargetLowering.h:512
llvm::APInt::isStrictlyPositive
bool isStrictlyPositive() const
Determine if this APInt Value is positive.
Definition: APInt.h:333
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::APInt::ms
Magic data for optimising signed division by a constant.
Definition: APInt.h:1697
llvm::APInt::ms::m
APInt m
magic number
Definition: APInt.h:1698
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
SDValue TargetLowering::BuildUDIV ( SDNode *  N,
const APInt &  Divisor,
SelectionDAG &  DAG,
bool  IsAfterLegalization,
std::vector< SDNode * > *  Created 
) const
inherited

Given an ISD::UDIV node expressing a divide by constant, return a DAG expression to select that will generate the same value by multiplying by a magic number. See: http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html

Definition at line 2705 of file TargetLowering.cpp.

2707  {
2708  EVT VT = N->getValueType(0);
2709  SDLoc dl(N);
2710 
2711  // Check to see if we can do this.
2712  // FIXME: We should be more aggressive here.
2713  if (!isTypeLegal(VT))
2714  return SDValue();
2715 
2716  // FIXME: We should use a narrower constant when the upper
2717  // bits are known to be zero.
2718  APInt::mu magics = Divisor.magicu();
2719 
2720  SDValue Q = N->getOperand(0);
2721 
2722  // If the divisor is even, we can avoid using the expensive fixup by shifting
2723  // the divided value upfront.
2724  if (magics.a != 0 && !Divisor[0]) {
2725  unsigned Shift = Divisor.countTrailingZeros();
2726  Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2727  DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
2728  if (Created)
2729  Created->push_back(Q.getNode());
2730 
2731  // Get magic number for the shifted divisor.
2732  magics = Divisor.lshr(Shift).magicu(Shift);
2733  assert(magics.a == 0 && "Should use cheap fixup now");
2734  }
2735 
2736  // Multiply the numerator (operand 0) by the magic value
2737  // FIXME: We should support doing a MUL in a wider type
2738  if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2739  isOperationLegalOrCustom(ISD::MULHU, VT))
2740  Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2741  else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2742  isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2743  Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2744  DAG.getConstant(magics.m, VT)).getNode(), 1);
2745  else
2746  return SDValue(); // No mulhu or equvialent
2747  if (Created)
2748  Created->push_back(Q.getNode());
2749 
2750  if (magics.a == 0) {
2751  assert(magics.s < Divisor.getBitWidth() &&
2752  "We shouldn't generate an undefined shift!");
2753  return DAG.getNode(ISD::SRL, dl, VT, Q,
2754  DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
2755  } else {
2756  SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2757  if (Created)
2758  Created->push_back(NPQ.getNode());
2759  NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2760  DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
2761  if (Created)
2762  Created->push_back(NPQ.getNode());
2763  NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2764  if (Created)
2765  Created->push_back(NPQ.getNode());
2766  return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2767  DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
2768  }
2769 }
llvm::APInt::magicu
mu magicu(unsigned LeadingZeros=0) const
Definition: APInt.cpp:1440
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:592
llvm::APInt::mu
Magic data for optimising unsigned division by a constant.
Definition: APInt.h:1703
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy) const
Definition: TargetLoweringBase.cpp:860
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Definition: SelectionDAGNodes.h:648
llvm::APInt::lshr
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1128
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::isOperationLegalOrCustom
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Definition: TargetLowering.h:489
llvm::TargetLoweringBase::isOperationLegal
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
Definition: TargetLowering.h:512
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
llvm::APInt::countTrailingZeros
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.cpp:737
llvm::APInt::mu::m
APInt m
magic number
Definition: APInt.h:1704
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::APInt::mu::s
unsigned s
shift amount
Definition: APInt.h:1706
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::APInt::mu::a
bool a
add indicator
Definition: APInt.h:1705
bool X86TargetLowering::CanLowerReturn ( CallingConv::ID  CallConv,
MachineFunction &  MF,
bool  isVarArg,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
LLVMContext &  Context 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 1865 of file X86ISelLowering.cpp.

1868  {
1869  SmallVector<CCValAssign, 16> RVLocs;
1870  CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
1871  RVLocs, Context);
1872  return CCInfo.CheckReturn(Outs, RetCC_X86);
1873 }
llvm::CCState::CheckReturn
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &ArgsFlags, CCAssignFn Fn)
Definition: CallingConvLower.cpp:86
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
bool TargetLoweringBase::canOpTrap ( unsigned  Op,
EVT  VT 
) const
virtualinherited

Returns true if the operation can trap for the value type.

VT must be a legal type. By default, we optimistically assume most operations don't trap except for divide and remainder.

canOpTrap - Returns true if the operation can trap for the value type. VT must be a legal type.

Definition at line 869 of file TargetLoweringBase.cpp.

869  {
870  assert(isTypeLegal(VT));
871  switch (Op) {
872  default:
873  return false;
874  case ISD::FDIV:
875  case ISD::FREM:
876  case ISD::SDIV:
877  case ISD::UDIV:
878  case ISD::SREM:
879  case ISD::UREM:
880  return true;
881  }
882 }
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
assert
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::clearOperationActions ( )
inlineprotectedinherited

Remove all operation actions.

Definition at line 1088 of file TargetLowering.h.

1088  {
1089  }
void llvm::TargetLoweringBase::clearRegisterClasses ( )
inlineprotectedinherited

Remove all register classes.

Definition at line 1081 of file TargetLowering.h.

1081  {
1082  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1083 
1084  AvailableRegClasses.clear();
1085  }
llvm::TargetLoweringBase::AvailableRegClasses
std::vector< std::pair< MVT, const TargetRegisterClass * > > AvailableRegClasses
True if this is a little endian target.
Definition: TargetLowering.h:1759
llvm::LibFunc::memset
void *memset(void *b, int c, size_t len);
Definition: TargetLibraryInfo.h:414
llvm::TargetLoweringBase::RegClassForVT
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1569
void TargetLowering::ComputeConstraintToUse ( AsmOperandInfo &  OpInfo,
SDValue  Op,
SelectionDAG *  DAG = nullptr 
) const
virtualinherited

Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand being passed in is available, it can be passed in as Op, otherwise an empty SDValue can be passed.

ComputeConstraintToUse - Determines the constraint code and constraint type to use for the specific AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.

Definition at line 2582 of file TargetLowering.cpp.

2584  {
2585  assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2586 
2587  // Single-letter constraints ('r') are very common.
2588  if (OpInfo.Codes.size() == 1) {
2589  OpInfo.ConstraintCode = OpInfo.Codes[0];
2590  OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2591  } else {
2592  ChooseConstraint(OpInfo, *this, Op, DAG);
2593  }
2594 
2595  // 'X' matches anything.
2596  if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2597  // Labels and constants are handled elsewhere ('X' is the only thing
2598  // that matches labels). For Functions, the type here is the type of
2599  // the result, which is not what we want to look at; leave them alone.
2600  Value *v = OpInfo.CallOperandVal;
2601  if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2602  OpInfo.CallOperandVal = v;
2603  return;
2604  }
2605 
2606  // Otherwise, try to resolve it to something we know about by looking at
2607  // the actual operand type.
2608  if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2609  OpInfo.ConstraintCode = Repl;
2610  OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2611  }
2612  }
2613 }
llvm::TargetLowering::getConstraintType
virtual ConstraintType getConstraintType(const std::string &Constraint) const
Given a constraint, return the type of constraint it is for this target.
Definition: TargetLowering.cpp:2048
llvm::TargetLowering::LowerXConstraint
virtual const char * LowerXConstraint(EVT ConstraintVT) const
Definition: TargetLowering.cpp:2091
assert
assert(Globals.size() > 1)
ChooseConstraint
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, const TargetLowering &TLI, SDValue Op, SelectionDAG *DAG)
Definition: TargetLowering.cpp:2531
llvm::Value
LLVM Value Representation.
Definition: Value.h:69
void X86TargetLowering::computeKnownBitsForTargetNode ( const SDValue  Op,
APInt &  KnownZero,
APInt &  KnownOne,
const SelectionDAG &  DAG,
unsigned  Depth = 0 
) const
overridevirtual

computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.

Reimplemented from llvm::TargetLowering.

Definition at line 18243 of file X86ISelLowering.cpp.

18247  {
18248  unsigned BitWidth = KnownZero.getBitWidth();
18249  unsigned Opc = Op.getOpcode();
18250  assert((Opc >= ISD::BUILTIN_OP_END ||
18251  Opc == ISD::INTRINSIC_WO_CHAIN ||
18252  Opc == ISD::INTRINSIC_W_CHAIN ||
18253  Opc == ISD::INTRINSIC_VOID) &&
18254  "Should use MaskedValueIsZero if you don't know whether Op"
18255  " is a target node!");
18256 
18257  KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
18258  switch (Opc) {
18259  default: break;
18260  case X86ISD::ADD:
18261  case X86ISD::SUB:
18262  case X86ISD::ADC:
18263  case X86ISD::SBB:
18264  case X86ISD::SMUL:
18265  case X86ISD::UMUL:
18266  case X86ISD::INC:
18267  case X86ISD::DEC:
18268  case X86ISD::OR:
18269  case X86ISD::XOR:
18270  case X86ISD::AND:
18271  // These nodes' second result is a boolean.
18272  if (Op.getResNo() == 0)
18273  break;
18274  // Fallthrough
18275  case X86ISD::SETCC:
18276  KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
18277  break;
18278  case ISD::INTRINSIC_WO_CHAIN: {
18279  unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
18280  unsigned NumLoBits = 0;
18281  switch (IntId) {
18282  default: break;
18283  case Intrinsic::x86_sse_movmsk_ps:
18284  case Intrinsic::x86_avx_movmsk_ps_256:
18285  case Intrinsic::x86_sse2_movmsk_pd:
18286  case Intrinsic::x86_avx_movmsk_pd_256:
18287  case Intrinsic::x86_mmx_pmovmskb:
18288  case Intrinsic::x86_sse2_pmovmskb_128:
18289  case Intrinsic::x86_avx2_pmovmskb: {
18290  // High bits of movmskp{s|d}, pmovmskb are known zero.
18291  switch (IntId) {
18292  default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
18293  case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
18294  case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
18295  case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
18296  case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
18297  case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
18298  case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
18299  case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
18300  }
18301  KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
18302  break;
18303  }
18304  }
18305  break;
18306  }
18307  }
18308 }
llvm::SDValue::getResNo
unsigned getResNo() const
get the index which selects a specific result in the SDNode
Definition: SelectionDAGNodes.h:127
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::APInt::getHighBitsSet
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
assert
assert(Globals.size() > 1)
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode ( SDValue  Op,
const SelectionDAG &  DAG,
unsigned  Depth 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 18310 of file X86ISelLowering.cpp.

18313  {
18314  // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
18315  if (Op.getOpcode() == X86ISD::SETCC_CARRY)
18316  return Op.getValueType().getScalarType().getSizeInBits();
18317 
18318  // Fallback case.
18319  return 1;
18320 }
llvm::EVT::getScalarType
EVT getScalarType() const
Definition: ValueTypes.h:211
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
void TargetLoweringBase::computeRegisterProperties ( )
protectedinherited

Once all of the register classes are added, this allows us to compute derived properties we expose.

computeRegisterProperties - Once all of the register classes are added, this allows us to compute derived properties we expose.

Definition at line 1025 of file TargetLoweringBase.cpp.

1025  {
1026  assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
1027  "Too many value types for ValueTypeActions to hold!");
1028 
1029  // Everything defaults to needing one register.
1030  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1031  NumRegistersForVT[i] = 1;
1032  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1033  }
1034  // ...except isVoid, which doesn't need any registers.
1035  NumRegistersForVT[MVT::isVoid] = 0;
1036 
1037  // Find the largest integer register class.
1038  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1039  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1040  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1041 
1042  // Every integer value type larger than this largest register takes twice as
1043  // many registers to represent as the previous ValueType.
1044  for (unsigned ExpandedReg = LargestIntReg + 1;
1045  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1046  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1047  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1048  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1049  ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1050  TypeExpandInteger);
1051  }
1052 
1053  // Inspect all of the ValueType's smaller than the largest integer
1054  // register to see which ones need promotion.
1055  unsigned LegalIntReg = LargestIntReg;
1056  for (unsigned IntReg = LargestIntReg - 1;
1057  IntReg >= (unsigned)MVT::i1; --IntReg) {
1058  MVT IVT = (MVT::SimpleValueType)IntReg;
1059  if (isTypeLegal(IVT)) {
1060  LegalIntReg = IntReg;
1061  } else {
1062  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1063  (const MVT::SimpleValueType)LegalIntReg;
1064  ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1065  }
1066  }
1067 
1068  // ppcf128 type is really two f64's.
1069  if (!isTypeLegal(MVT::ppcf128)) {
1070  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1071  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1072  TransformToType[MVT::ppcf128] = MVT::f64;
1073  ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1074  }
1075 
1076  // Decide how to handle f128. If the target does not have native f128 support,
1077  // expand it to i128 and we will be generating soft float library calls.
1078  if (!isTypeLegal(MVT::f128)) {
1079  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1080  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1081  TransformToType[MVT::f128] = MVT::i128;
1082  ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1083  }
1084 
1085  // Decide how to handle f64. If the target does not have native f64 support,
1086  // expand it to i64 and we will be generating soft float library calls.
1087  if (!isTypeLegal(MVT::f64)) {
1088  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1089  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1090  TransformToType[MVT::f64] = MVT::i64;
1091  ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1092  }
1093 
1094  // Decide how to handle f32. If the target does not have native support for
1095  // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
1096  if (!isTypeLegal(MVT::f32)) {
1097  if (isTypeLegal(MVT::f64)) {
1098  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
1099  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
1100  TransformToType[MVT::f32] = MVT::f64;
1101  ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
1102  } else {
1103  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1104  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1105  TransformToType[MVT::f32] = MVT::i32;
1106  ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1107  }
1108  }
1109 
1110  if (!isTypeLegal(MVT::f16)) {
1111  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1112  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1113  TransformToType[MVT::f16] = MVT::i16;
1114  ValueTypeActions.setTypeAction(MVT::f16, TypeSoftenFloat);
1115  }
1116 
1117  // Loop over all of the vector value types to see which need transformations.
1118  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1119  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1120  MVT VT = (MVT::SimpleValueType) i;
1121  if (isTypeLegal(VT))
1122  continue;
1123 
1124  MVT EltVT = VT.getVectorElementType();
1125  unsigned NElts = VT.getVectorNumElements();
1126  bool IsLegalWiderType = false;
1127  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1128  switch (PreferredAction) {
1129  case TypePromoteInteger: {
1130  // Try to promote the elements of integer vectors. If no legal
1131  // promotion was found, fall through to the widen-vector method.
1132  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1133  MVT SVT = (MVT::SimpleValueType) nVT;
1134  // Promote vectors of integers to vectors with the same number
1135  // of elements, with a wider element type.
1136  if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
1137  && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)
1138  && SVT.getScalarType().isInteger()) {
1139  TransformToType[i] = SVT;
1140  RegisterTypeForVT[i] = SVT;
1141  NumRegistersForVT[i] = 1;
1142  ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1143  IsLegalWiderType = true;
1144  break;
1145  }
1146  }
1147  if (IsLegalWiderType)
1148  break;
1149  }
1150  case TypeWidenVector: {
1151  // Try to widen the vector.
1152  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1153  MVT SVT = (MVT::SimpleValueType) nVT;
1154  if (SVT.getVectorElementType() == EltVT
1155  && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1156  TransformToType[i] = SVT;
1157  RegisterTypeForVT[i] = SVT;
1158  NumRegistersForVT[i] = 1;
1159  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1160  IsLegalWiderType = true;
1161  break;
1162  }
1163  }
1164  if (IsLegalWiderType)
1165  break;
1166  }
1167  case TypeSplitVector:
1168  case TypeScalarizeVector: {
1169  MVT IntermediateVT;
1170  MVT RegisterVT;
1171  unsigned NumIntermediates;
1172  NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1173  NumIntermediates, RegisterVT, this);
1174  RegisterTypeForVT[i] = RegisterVT;
1175 
1176  MVT NVT = VT.getPow2VectorType();
1177  if (NVT == VT) {
1178  // Type is already a power of 2. The default action is to split.
1179  TransformToType[i] = MVT::Other;
1180  if (PreferredAction == TypeScalarizeVector)
1181  ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1182  else
1183  ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1184  } else {
1185  TransformToType[i] = NVT;
1186  ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1187  }
1188  break;
1189  }
1190  default:
1191  llvm_unreachable("Unknown vector legalization action!");
1192  }
1193  }
1194 
1195  // Determine the 'representative' register class for each value type.
1196  // An representative register class is the largest (meaning one which is
1197  // not a sub-register class / subreg register class) legal register class for
1198  // a group of value types. For example, on i386, i8, i16, and i32
1199  // representative would be GR32; while on x86_64 it's GR64.
1200  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1201  const TargetRegisterClass* RRC;
1202  uint8_t Cost;
1203  std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
1204  RepRegClassForVT[i] = RRC;
1205  RepRegClassCostForVT[i] = Cost;
1206  }
1207 }
llvm::TargetLoweringBase::RepRegClassForVT
const TargetRegisterClass * RepRegClassForVT[MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1579
llvm::TargetLoweringBase::TransformToType
MVT TransformToType[MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1591
llvm::TargetLoweringBase::findRepresentativeClass
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(MVT VT) const
Definition: TargetLoweringBase.cpp:998
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::MVT::getScalarType
MVT getScalarType() const
Definition: MachineValueType.h:260
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
assert
assert(Globals.size() > 1)
llvm::MVT::isInteger
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: MachineValueType.h:177
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:312
llvm::TargetLoweringBase::NumRegistersForVT
unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
Definition: TargetLowering.h:1570
getVectorTypeBreakdownMVT
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
Definition: TargetLoweringBase.cpp:885
llvm::TargetLoweringBase::RegisterTypeForVT
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
Definition: TargetLowering.h:1571
llvm::TargetLoweringBase::RegClassForVT
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1569
llvm::TargetLoweringBase::ValueTypeActions
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
Definition: TargetLowering.h:1625
llvm::MSP430ISD::RRC
Y = RRC X, rotate right via carry.
Definition: MSP430ISelLowering.h:37
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:190
llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction
void setTypeAction(MVT VT, LegalizeTypeAction Action)
Definition: TargetLowering.h:361
llvm::MVT::getPow2VectorType
MVT getPow2VectorType() const
Definition: MachineValueType.h:249
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:264
llvm::TargetLoweringBase::RepRegClassCostForVT
uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1584
SDValue X86TargetLowering::ConvertCmpIfNecessary ( SDValue  Cmp,
SelectionDAG &  DAG 
) const
private

Convert a comparison if required by the subtarget.

Definition at line 11926 of file X86ISelLowering.cpp.

11927  {
11928  // If the subtarget does not support the FUCOMI instruction, floating-point
11929  // comparisons have to be converted.
11930  if (Subtarget->hasCMov() ||
11931  Cmp.getOpcode() != X86ISD::CMP ||
11932  !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
11933  !Cmp.getOperand(1).getValueType().isFloatingPoint())
11934  return Cmp;
11935 
11936  // The instruction selector will select an FUCOM instruction instead of
11937  // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
11938  // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
11939  // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
11940  SDLoc dl(Cmp);
11941  SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
11942  SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
11943  SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
11944  DAG.getConstant(8, MVT::i8));
11945  SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
11946  return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
11947 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86ISD::CMP
X86 compare and logical compare instructions.
Definition: X86ISelLowering.h:93
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::X86Subtarget::hasCMov
bool hasCMov() const
Definition: X86Subtarget.h:309
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::EVT::isFloatingPoint
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
FastISel * X86TargetLowering::createFastISel ( FunctionLoweringInfo &  funcInfo,
const TargetLibraryInfo *  libInfo 
) const
overridevirtual

createFastISel - This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.

Reimplemented from llvm::TargetLowering.

Definition at line 3361 of file X86ISelLowering.cpp.

3362  {
3363  return X86::createFastISel(funcInfo, libInfo);
3364 }
llvm::X86::createFastISel
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
Definition: X86FastISel.cpp:3300
MachineBasicBlock* llvm::X86TargetLowering::EmitAtomicLoadArith ( MachineInstr *  MI,
MachineBasicBlock *  MBB 
) const
private

Utility function to emit atomic-load-arith operations (and, or, xor, nand, max, min, umax, umin). It takes the corresponding instruction to expand, the associated machine basic block, and the associated X86 opcodes for reg/reg.

MachineBasicBlock* llvm::X86TargetLowering::EmitAtomicLoadArith6432 ( MachineInstr *  MI,
MachineBasicBlock *  MBB 
) const
private

Utility function to emit atomic-load-arith operations (and, or, xor, nand, add, sub, swap) for 64-bit operands on 32-bit target.

SDValue X86TargetLowering::EmitCmp ( SDValue  Op0,
SDValue  Op1,
unsigned  X86CC,
SDLoc  dl,
SelectionDAG &  DAG 
) const
private

Emit nodes that will be selected as "cmp Op0,Op1", or something equivalent, for use with the given x86 condition code.

Emit nodes that will be selected as "cmp Op0,Op1", or something equivalent.

Definition at line 11891 of file X86ISelLowering.cpp.

11892  {
11893  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
11894  if (C->getAPIntValue() == 0)
11895  return EmitTest(Op0, X86CC, dl, DAG);
11896 
11897  if (Op0.getValueType() == MVT::i1)
11898  llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
11899  }
11900 
11901  if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
11902  Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
11903  // Do the comparison at i32 if it's smaller, besides the Atom case.
11904  // This avoids subregister aliasing issues. Keep the smaller reference
11905  // if we're optimizing for size, however, as that'll allow better folding
11906  // of memory operations.
11907  if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
11908  !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
11909  AttributeSet::FunctionIndex, Attribute::MinSize) &&
11910  !Subtarget->isAtom()) {
11911  unsigned ExtendOp =
11912  isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
11913  Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
11914  Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
11915  }
11916  // Use SUB instead of CMP to enable CSE between SUB and CMP.
11917  SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
11918  SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
11919  Op0, Op1);
11920  return SDValue(Sub.getNode(), 1);
11921  }
11922  return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
11923 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::MachineFunction::getFunction
const Function * getFunction() const
Definition: MachineFunction.h:151
llvm::X86TargetLowering::EmitTest
SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:11654
llvm::AttributeSet::hasAttribute
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::X86ISD::CMP
X86 compare and logical compare instructions.
Definition: X86ISelLowering.h:93
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::Function::getAttributes
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::X86Subtarget::isAtom
bool isAtom() const
Definition: X86Subtarget.h:365
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
isX86CCUnsigned
static bool isX86CCUnsigned(unsigned X86CC)
Return true if the condition is an unsigned comparison operation.
Definition: X86ISelLowering.cpp:3535
llvm::Attribute::MinSize
Function must be optimized for size first.
Definition: Attributes.h:79
MachineBasicBlock * X86TargetLowering::emitEHSjLjLongJmp ( MachineInstr *  MI,
MachineBasicBlock *  MBB 
) const
private

Definition at line 17890 of file X86ISelLowering.cpp.

17891  {
17892  DebugLoc DL = MI->getDebugLoc();
17893  MachineFunction *MF = MBB->getParent();
17894  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17895  MachineRegisterInfo &MRI = MF->getRegInfo();
17896 
17897  // Memory Reference
17898  MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17899  MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17900 
17901  MVT PVT = getPointerTy();
17902  assert((PVT == MVT::i64 || PVT == MVT::i32) &&
17903  "Invalid Pointer Size!");
17904 
17905  const TargetRegisterClass *RC =
17906  (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
17907  unsigned Tmp = MRI.createVirtualRegister(RC);
17908  // Since FP is only updated here but NOT referenced, it's treated as GPR.
17909  const X86RegisterInfo *RegInfo =
17910  static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
17911  unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
17912  unsigned SP = RegInfo->getStackRegister();
17913 
17914  MachineInstrBuilder MIB;
17915 
17916  const int64_t LabelOffset = 1 * PVT.getStoreSize();
17917  const int64_t SPOffset = 2 * PVT.getStoreSize();
17918 
17919  unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
17920  unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
17921 
17922  // Reload FP
17923  MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
17924  for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
17925  MIB.addOperand(MI->getOperand(i));
17926  MIB.setMemRefs(MMOBegin, MMOEnd);
17927  // Reload IP
17928  MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
17929  for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17930  if (i == X86::AddrDisp)
17931  MIB.addDisp(MI->getOperand(i), LabelOffset);
17932  else
17933  MIB.addOperand(MI->getOperand(i));
17934  }
17935  MIB.setMemRefs(MMOBegin, MMOEnd);
17936  // Reload SP
17937  MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
17938  for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17939  if (i == X86::AddrDisp)
17940  MIB.addDisp(MI->getOperand(i), SPOffset);
17941  else
17942  MIB.addOperand(MI->getOperand(i));
17943  }
17944  MIB.setMemRefs(MMOBegin, MMOEnd);
17945  // Jump
17946  BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
17947 
17948  MI->eraseFromParent();
17949  return MBB;
17950 }
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Definition: MachineBasicBlock.h:137
llvm::MachineRegisterInfo::createVirtualRegister
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
Definition: MachineRegisterInfo.cpp:97
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:114
llvm::MachineInstrBuilder::addDisp
const MachineInstrBuilder & addDisp(const MachineOperand &Disp, int64_t off, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:197
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::MVT::getStoreSize
unsigned getStoreSize() const
Definition: MachineValueType.h:438
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:340
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
Definition: MachineInstrBuilder.h:159
assert
assert(Globals.size() > 1)
llvm::X86::AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
Definition: MachineInstrBuilder.h:228
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
llvm::X86RegisterInfo::getStackRegister
unsigned getStackRegister() const
Definition: X86RegisterInfo.h:125
llvm::TargetMachine::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: Target/TargetMachine.h:118
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
Definition: MachineFunction.h:167
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::MachineInstrBuilder::addOperand
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:166
llvm::MachineInstr::getDebugLoc
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:339
MachineBasicBlock * X86TargetLowering::emitEHSjLjSetJmp ( MachineInstr *  MI,
MachineBasicBlock *  MBB 
) const
private

Definition at line 17753 of file X86ISelLowering.cpp.

17754  {
17755  DebugLoc DL = MI->getDebugLoc();
17756  MachineFunction *MF = MBB->getParent();
17757  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17758  MachineRegisterInfo &MRI = MF->getRegInfo();
17759 
17760  const BasicBlock *BB = MBB->getBasicBlock();
17761  MachineFunction::iterator I = MBB;
17762  ++I;
17763 
17764  // Memory Reference
17765  MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17766  MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17767 
17768  unsigned DstReg;
17769  unsigned MemOpndSlot = 0;
17770 
17771  unsigned CurOp = 0;
17772 
17773  DstReg = MI->getOperand(CurOp++).getReg();
17774  const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
17775  assert(RC->hasType(MVT::i32) && "Invalid destination!");
17776  unsigned mainDstReg = MRI.createVirtualRegister(RC);
17777  unsigned restoreDstReg = MRI.createVirtualRegister(RC);
17778 
17779  MemOpndSlot = CurOp;
17780 
17781  MVT PVT = getPointerTy();
17782  assert((PVT == MVT::i64 || PVT == MVT::i32) &&
17783  "Invalid Pointer Size!");
17784 
17785  // For v = setjmp(buf), we generate
17786  //
17787  // thisMBB:
17788  // buf[LabelOffset] = restoreMBB
17789  // SjLjSetup restoreMBB
17790  //
17791  // mainMBB:
17792  // v_main = 0
17793  //
17794  // sinkMBB:
17795  // v = phi(main, restore)
17796  //
17797  // restoreMBB:
17798  // v_restore = 1
17799 
17800  MachineBasicBlock *thisMBB = MBB;
17801  MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17802  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17803  MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
17804  MF->insert(I, mainMBB);
17805  MF->insert(I, sinkMBB);
17806  MF->push_back(restoreMBB);
17807 
17808  MachineInstrBuilder MIB;
17809 
17810  // Transfer the remainder of BB and its successor edges to sinkMBB.
17811  sinkMBB->splice(sinkMBB->begin(), MBB,
17812  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17813  sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17814 
17815  // thisMBB:
17816  unsigned PtrStoreOpc = 0;
17817  unsigned LabelReg = 0;
17818  const int64_t LabelOffset = 1 * PVT.getStoreSize();
17819  Reloc::Model RM = MF->getTarget().getRelocationModel();
17820  bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
17821  (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
17822 
17823  // Prepare IP either in reg or imm.
17824  if (!UseImmLabel) {
17825  PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
17826  const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
17827  LabelReg = MRI.createVirtualRegister(PtrRC);
17828  if (Subtarget->is64Bit()) {
17829  MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
17830  .addReg(X86::RIP)
17831  .addImm(0)
17832  .addReg(0)
17833  .addMBB(restoreMBB)
17834  .addReg(0);
17835  } else {
17836  const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
17837  MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
17838  .addReg(XII->getGlobalBaseReg(MF))
17839  .addImm(0)
17840  .addReg(0)
17841  .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
17842  .addReg(0);
17843  }
17844  } else
17845  PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
17846  // Store IP
17847  MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
17848  for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17849  if (i == X86::AddrDisp)
17850  MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
17851  else
17852  MIB.addOperand(MI->getOperand(MemOpndSlot + i));
17853  }
17854  if (!UseImmLabel)
17855  MIB.addReg(LabelReg);
17856  else
17857  MIB.addMBB(restoreMBB);
17858  MIB.setMemRefs(MMOBegin, MMOEnd);
17859  // Setup
17860  MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
17861  .addMBB(restoreMBB);
17862 
17863  const X86RegisterInfo *RegInfo =
17864  static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
17865  MIB.addRegMask(RegInfo->getNoPreservedMask());
17866  thisMBB->addSuccessor(mainMBB);
17867  thisMBB->addSuccessor(restoreMBB);
17868 
17869  // mainMBB:
17870  // EAX = 0
17871  BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
17872  mainMBB->addSuccessor(sinkMBB);
17873 
17874  // sinkMBB:
17875  BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17876  TII->get(X86::PHI), DstReg)
17877  .addReg(mainDstReg).addMBB(mainMBB)
17878  .addReg(restoreDstReg).addMBB(restoreMBB);
17879 
17880  // restoreMBB:
17881  BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
17882  BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
17883  restoreMBB->addSuccessor(sinkMBB);
17884 
17885  MI->eraseFromParent();
17886  return sinkMBB;
17887 }
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Definition: MachineBasicBlock.h:137
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Definition: TargetMachine.cpp:76
llvm::MachineRegisterInfo::createVirtualRegister
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
Definition: MachineRegisterInfo.cpp:97
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
Definition: MachineBasicBlock.cpp:598
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:114
llvm::MachineInstrBuilder::addDisp
const MachineInstrBuilder & addDisp(const MachineOperand &Disp, int64_t off, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:197
llvm::MachineRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned Reg) const
Definition: MachineRegisterInfo.h:556
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::MVT::getStoreSize
unsigned getStoreSize() const
Definition: MachineValueType.h:438
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Definition: MachineInstrBuilder.h:83
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
Definition: MachineFunction.cpp:215
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Definition: MachineBasicBlock.h:117
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:340
llvm::X86Subtarget::ClassifyBlockAddressReference
unsigned char ClassifyBlockAddressReference() const
Definition: X86Subtarget.cpp:49
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
Definition: MachineInstrBuilder.h:159
assert
assert(Globals.size() > 1)
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Definition: TargetMachine.cpp:84
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:72
llvm::X86::AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
llvm::MachineBasicBlock::bundle_iterator
Definition: MachineBasicBlock.h:144
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
Definition: MachineInstrBuilder.h:228
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
llvm::TargetMachine::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: Target/TargetMachine.h:118
llvm::X86InstrInfo::getGlobalBaseReg
unsigned getGlobalBaseReg(MachineFunction *MF) const
Definition: X86InstrInfo.cpp:5170
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Definition: TargetLowering.h:314
llvm::X86RegisterInfo::getNoPreservedMask
const uint32_t * getNoPreservedMask() const
Definition: X86RegisterInfo.cpp:321
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Definition: MachineBasicBlock.h:565
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
Definition: MachineFunction.h:167
I
#define I(x, y, z)
Definition: MD5.cpp:54
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::TargetRegisterClass::hasType
bool hasType(EVT vt) const
Definition: TargetRegisterInfo.h:104
llvm::MachineOperand::getReg
unsigned getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:264
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:331
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:98
llvm::MachineFunction::push_back
void push_back(MachineBasicBlock *MBB)
Definition: MachineFunction.h:329
llvm::MachineInstrBuilder::addOperand
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:166
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:300
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:149
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Definition: MachineInstrBuilder.h:64
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
Definition: MachineBasicBlock.cpp:488
llvm::MachineInstr::getDebugLoc
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:339
MachineBasicBlock * X86TargetLowering::emitFMA3Instr ( MachineInstr *  MI,
MachineBasicBlock *  MBB 
) const
private

Definition at line 17956 of file X86ISelLowering.cpp.

17957  {
17958  MachineOperand &AddendOp = MI->getOperand(3);
17959 
17960  // Bail out early if the addend isn't a register - we can't switch these.
17961  if (!AddendOp.isReg())
17962  return MBB;
17963 
17964  MachineFunction &MF = *MBB->getParent();
17965  MachineRegisterInfo &MRI = MF.getRegInfo();
17966 
17967  // Check whether the addend is defined by a PHI:
17968  assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
17969  MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
17970  if (!AddendDef.isPHI())
17971  return MBB;
17972 
17973  // Look for the following pattern:
17974  // loop:
17975  // %addend = phi [%entry, 0], [%loop, %result]
17976  // ...
17977  // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
17978 
17979  // Replace with:
17980  // loop:
17981  // %addend = phi [%entry, 0], [%loop, %result]
17982  // ...
17983  // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
17984 
17985  for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
17986  assert(AddendDef.getOperand(i).isReg());
17987  MachineOperand PHISrcOp = AddendDef.getOperand(i);
17988  MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
17989  if (&PHISrcInst == MI) {
17990  // Found a matching instruction.
17991  unsigned NewFMAOpc = 0;
17992  switch (MI->getOpcode()) {
17993  case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
17994  case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
17995  case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
17996  case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
17997  case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
17998  case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
17999  case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
18000  case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
18001  case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
18002  case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
18003  case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
18004  case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
18005  case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
18006  case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
18007  case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
18008  case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18009  case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18010  case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18011  case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18012  case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18013  case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18014  case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18015  case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18016  case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18017  default: llvm_unreachable("Unrecognized FMA variant.");
18018  }
18019 
18020  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
18021  MachineInstrBuilder MIB =
18022  BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18023  .addOperand(MI->getOperand(0))
18024  .addOperand(MI->getOperand(3))
18025  .addOperand(MI->getOperand(2))
18026  .addOperand(MI->getOperand(1));
18027  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18028  MI->eraseFromParent();
18029  }
18030  }
18031 
18032  return MBB;
18033 }
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Definition: MachineBasicBlock.h:137
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:114
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:703
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:227
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Definition: MachineInstr.h:274
llvm::MachineInstr::getOpcode
int getOpcode() const
Definition: MachineInstr.h:270
assert
assert(Globals.size() > 1)
llvm::MachineBasicBlock::bundle_iterator
Definition: MachineBasicBlock.h:144
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
Definition: MachineInstrBuilder.h:228
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
llvm::TargetMachine::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: Target/TargetMachine.h:118
llvm::MachineRegisterInfo::hasOneDef
bool hasOneDef(unsigned RegNo) const
Definition: MachineRegisterInfo.h:379
llvm::MachineRegisterInfo::def_instr_begin
def_instr_iterator def_instr_begin(unsigned RegNo) const
Definition: MachineRegisterInfo.h:344
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
Definition: MachineFunction.h:167
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
llvm::MachineOperand::getReg
unsigned getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:264
llvm::MachineInstr::getDebugLoc
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
MachineBasicBlock * X86TargetLowering::EmitInstrWithCustomInserter ( MachineInstr *  MI,
MachineBasicBlock *  MBB 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 18036 of file X86ISelLowering.cpp.

18037  {
18038  switch (MI->getOpcode()) {
18039  default: llvm_unreachable("Unexpected instr type to insert");
18040  case X86::TAILJMPd64:
18041  case X86::TAILJMPr64:
18042  case X86::TAILJMPm64:
18043  llvm_unreachable("TAILJMP64 would not be touched here.");
18044  case X86::TCRETURNdi64:
18045  case X86::TCRETURNri64:
18046  case X86::TCRETURNmi64:
18047  return BB;
18048  case X86::WIN_ALLOCA:
18049  return EmitLoweredWinAlloca(MI, BB);
18050  case X86::SEG_ALLOCA_32:
18051  return EmitLoweredSegAlloca(MI, BB, false);
18052  case X86::SEG_ALLOCA_64:
18053  return EmitLoweredSegAlloca(MI, BB, true);
18054  case X86::TLSCall_32:
18055  case X86::TLSCall_64:
18056  return EmitLoweredTLSCall(MI, BB);
18057  case X86::CMOV_GR8:
18058  case X86::CMOV_FR32:
18059  case X86::CMOV_FR64:
18060  case X86::CMOV_V4F32:
18061  case X86::CMOV_V2F64:
18062  case X86::CMOV_V2I64:
18063  case X86::CMOV_V8F32:
18064  case X86::CMOV_V4F64:
18065  case X86::CMOV_V4I64:
18066  case X86::CMOV_V16F32:
18067  case X86::CMOV_V8F64:
18068  case X86::CMOV_V8I64:
18069  case X86::CMOV_GR16:
18070  case X86::CMOV_GR32:
18071  case X86::CMOV_RFP32:
18072  case X86::CMOV_RFP64:
18073  case X86::CMOV_RFP80:
18074  return EmitLoweredSelect(MI, BB);
18075 
18076  case X86::FP32_TO_INT16_IN_MEM:
18077  case X86::FP32_TO_INT32_IN_MEM:
18078  case X86::FP32_TO_INT64_IN_MEM:
18079  case X86::FP64_TO_INT16_IN_MEM:
18080  case X86::FP64_TO_INT32_IN_MEM:
18081  case X86::FP64_TO_INT64_IN_MEM:
18082  case X86::FP80_TO_INT16_IN_MEM:
18083  case X86::FP80_TO_INT32_IN_MEM:
18084  case X86::FP80_TO_INT64_IN_MEM: {
18085  MachineFunction *F = BB->getParent();
18086  const TargetInstrInfo *TII = F->getTarget().getInstrInfo();
18087  DebugLoc DL = MI->getDebugLoc();
18088 
18089  // Change the floating point control register to use "round towards zero"
18090  // mode when truncating to an integer value.
18091  int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18092  addFrameReference(BuildMI(*BB, MI, DL,
18093  TII->get(X86::FNSTCW16m)), CWFrameIdx);
18094 
18095  // Load the old value of the high byte of the control word...
18096  unsigned OldCW =
18097  F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18098  addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18099  CWFrameIdx);
18100 
18101  // Set the high part to be round to zero...
18102  addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18103  .addImm(0xC7F);
18104 
18105  // Reload the modified control word now...
18106  addFrameReference(BuildMI(*BB, MI, DL,
18107  TII->get(X86::FLDCW16m)), CWFrameIdx);
18108 
18109  // Restore the memory image of control word to original value
18110  addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18111  .addReg(OldCW);
18112 
18113  // Get the X86 opcode to use.
18114  unsigned Opc;
18115  switch (MI->getOpcode()) {
18116  default: llvm_unreachable("illegal opcode!");
18117  case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18118  case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18119  case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18120  case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18121  case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18122  case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18123  case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18124  case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18125  case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18126  }
18127 
18128  X86AddressMode AM;
18129  MachineOperand &Op = MI->getOperand(0);
18130  if (Op.isReg()) {
18131  AM.BaseType = X86AddressMode::RegBase;
18132  AM.Base.Reg = Op.getReg();
18133  } else {
18134  AM.BaseType = X86AddressMode::FrameIndexBase;
18135  AM.Base.FrameIndex = Op.getIndex();
18136  }
18137  Op = MI->getOperand(1);
18138  if (Op.isImm())
18139  AM.Scale = Op.getImm();
18140  Op = MI->getOperand(2);
18141  if (Op.isImm())
18142  AM.IndexReg = Op.getImm();
18143  Op = MI->getOperand(3);
18144  if (Op.isGlobal()) {
18145  AM.GV = Op.getGlobal();
18146  } else {
18147  AM.Disp = Op.getImm();
18148  }
18149  addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18150  .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18151 
18152  // Reload the original control word now.
18153  addFrameReference(BuildMI(*BB, MI, DL,
18154  TII->get(X86::FLDCW16m)), CWFrameIdx);
18155 
18156  MI->eraseFromParent(); // The pseudo instruction is gone now.
18157  return BB;
18158  }
18159  // String/text processing lowering.
18160  case X86::PCMPISTRM128REG:
18161  case X86::VPCMPISTRM128REG:
18162  case X86::PCMPISTRM128MEM:
18163  case X86::VPCMPISTRM128MEM:
18164  case X86::PCMPESTRM128REG:
18165  case X86::VPCMPESTRM128REG:
18166  case X86::PCMPESTRM128MEM:
18167  case X86::VPCMPESTRM128MEM:
18168  assert(Subtarget->hasSSE42() &&
18169  "Target must have SSE4.2 or AVX features enabled");
18170  return EmitPCMPSTRM(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18171 
18172  // String/text processing lowering.
18173  case X86::PCMPISTRIREG:
18174  case X86::VPCMPISTRIREG:
18175  case X86::PCMPISTRIMEM:
18176  case X86::VPCMPISTRIMEM:
18177  case X86::PCMPESTRIREG:
18178  case X86::VPCMPESTRIREG:
18179  case X86::PCMPESTRIMEM:
18180  case X86::VPCMPESTRIMEM:
18181  assert(Subtarget->hasSSE42() &&
18182  "Target must have SSE4.2 or AVX features enabled");
18183  return EmitPCMPSTRI(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18184 
18185  // Thread synchronization.
18186  case X86::MONITOR:
18187  return EmitMonitor(MI, BB, BB->getParent()->getTarget().getInstrInfo(), Subtarget);
18188 
18189  // xbegin
18190  case X86::XBEGIN:
18191  return EmitXBegin(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18192 
18193  case X86::VASTART_SAVE_XMM_REGS:
18194  return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
18195 
18196  case X86::VAARG_64:
18197  return EmitVAARG64WithCustomInserter(MI, BB);
18198 
18199  case X86::EH_SjLj_SetJmp32:
18200  case X86::EH_SjLj_SetJmp64:
18201  return emitEHSjLjSetJmp(MI, BB);
18202 
18203  case X86::EH_SjLj_LongJmp32:
18204  case X86::EH_SjLj_LongJmp64:
18205  return emitEHSjLjLongJmp(MI, BB);
18206 
18207  case TargetOpcode::STACKMAP:
18208  case TargetOpcode::PATCHPOINT:
18209  return emitPatchPoint(MI, BB);
18210 
18211  case X86::VFMADDPDr213r:
18212  case X86::VFMADDPSr213r:
18213  case X86::VFMADDSDr213r:
18214  case X86::VFMADDSSr213r:
18215  case X86::VFMSUBPDr213r:
18216  case X86::VFMSUBPSr213r:
18217  case X86::VFMSUBSDr213r:
18218  case X86::VFMSUBSSr213r:
18219  case X86::VFNMADDPDr213r:
18220  case X86::VFNMADDPSr213r:
18221  case X86::VFNMADDSDr213r:
18222  case X86::VFNMADDSSr213r:
18223  case X86::VFNMSUBPDr213r:
18224  case X86::VFNMSUBPSr213r:
18225  case X86::VFNMSUBSDr213r:
18226  case X86::VFNMSUBSSr213r:
18227  case X86::VFMADDPDr213rY:
18228  case X86::VFMADDPSr213rY:
18229  case X86::VFMSUBPDr213rY:
18230  case X86::VFMSUBPSr213rY:
18231  case X86::VFNMADDPDr213rY:
18232  case X86::VFNMADDPSr213rY:
18233  case X86::VFNMSUBPDr213rY:
18234  case X86::VFNMSUBPSr213rY:
18235  return emitFMA3Instr(MI, BB);
18236  }
18237 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:433
EmitPCMPSTRI
static MachineBasicBlock * EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB, const TargetInstrInfo *TII)
Definition: X86ISelLowering.cpp:17024
llvm::MachineRegisterInfo::createVirtualRegister
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
Definition: MachineRegisterInfo.cpp:97
EmitXBegin
static MachineBasicBlock * EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB, const TargetInstrInfo *TII)
Utility function to emit xbegin specifying the start of an RTM region.
Definition: X86ISelLowering.cpp:16929
EmitMonitor
static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB, const TargetInstrInfo *TII, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:17059
llvm::X86AddressMode::GV
const GlobalValue * GV
Definition: X86InstrBuilder.h:51
F
F(f)
EmitPCMPSTRM
static MachineBasicBlock * EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB, const TargetInstrInfo *TII)
Definition: X86ISelLowering.cpp:16987
llvm::X86AddressMode::Base
union llvm::X86AddressMode::@262 Base
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:114
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:229
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:227
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Definition: MachineInstrBuilder.h:83
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:245
llvm::X86TargetLowering::emitFMA3Instr
MachineBasicBlock * emitFMA3Instr(MachineInstr *MI, MachineBasicBlock *MBB) const
Definition: X86ISelLowering.cpp:17956
llvm::X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter
MachineBasicBlock * EmitVAStartSaveXMMRegsWithCustomInserter(MachineInstr *BInstr, MachineBasicBlock *BB) const
Utility function to emit the xmm reg save portion of va_start.
Definition: X86ISelLowering.cpp:17339
llvm::MachineInstr::getOpcode
int getOpcode() const
Definition: MachineInstr.h:270
llvm::X86TargetLowering::EmitLoweredTLSCall
MachineBasicBlock * EmitLoweredTLSCall(MachineInstr *MI, MachineBasicBlock *BB) const
Definition: X86ISelLowering.cpp:17694
llvm::TargetLoweringBase::emitPatchPoint
MachineBasicBlock * emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const
Definition: TargetLoweringBase.cpp:946
llvm::X86TargetLowering::emitEHSjLjSetJmp
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr *MI, MachineBasicBlock *MBB) const
Definition: X86ISelLowering.cpp:17753
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:407
llvm::X86TargetLowering::EmitLoweredSelect
MachineBasicBlock * EmitLoweredSelect(MachineInstr *I, MachineBasicBlock *BB) const
Definition: X86ISelLowering.cpp:17454
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
assert
assert(Globals.size() > 1)
llvm::X86TargetLowering::EmitVAARG64WithCustomInserter
MachineBasicBlock * EmitVAARG64WithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const
Definition: X86ISelLowering.cpp:17085
llvm::X86::AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
llvm::X86TargetLowering::emitEHSjLjLongJmp
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr *MI, MachineBasicBlock *MBB) const
Definition: X86ISelLowering.cpp:17890
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
Definition: MachineInstrBuilder.h:228
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
llvm::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0, bool mem=true)
Definition: PPCInstrBuilder.h:33
llvm::TargetMachine::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: Target/TargetMachine.h:118
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
Definition: MachineFunction.h:167
llvm::X86Subtarget::hasSSE42
bool hasSSE42() const
Definition: X86Subtarget.h:316
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Definition: MachineFunction.cpp:513
llvm::MachineOperand::getReg
unsigned getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:264
llvm::X86TargetLowering::EmitLoweredWinAlloca
MachineBasicBlock * EmitLoweredWinAlloca(MachineInstr *MI, MachineBasicBlock *BB) const
Definition: X86ISelLowering.cpp:17642
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Definition: MachineInstrBuilder.h:64
llvm::addFullAddress
static const MachineInstrBuilder & addFullAddress(const MachineInstrBuilder &MIB, const X86AddressMode &AM)
Definition: X86InstrBuilder.h:123
llvm::X86AddressMode::BaseType
enum llvm::X86AddressMode::@261 BaseType
llvm::MachineInstr::getDebugLoc
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
llvm::X86TargetLowering::EmitLoweredSegAlloca
MachineBasicBlock * EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, bool Is64Bit) const
Definition: X86ISelLowering.cpp:17521
virtual Value* llvm::TargetLoweringBase::emitLoadLinked ( IRBuilder<> &  Builder,
Value *  Addr,
AtomicOrdering  Ord 
) const
inlinevirtualinherited

Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type. This may entail some non-trivial operations to truncate or reconstruct types that will be illegal in the backend. See ARMISelLowering for an example implementation.

Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 932 of file TargetLowering.h.

933  {
934  llvm_unreachable("Load linked unimplemented on this target");
935  }
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
MachineBasicBlock * X86TargetLowering::EmitLoweredSegAlloca ( MachineInstr *  MI,
MachineBasicBlock *  BB,
bool  Is64Bit 
) const
private

Definition at line 17521 of file X86ISelLowering.cpp.

17522  {
17523  MachineFunction *MF = BB->getParent();
17524  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17525  DebugLoc DL = MI->getDebugLoc();
17526  const BasicBlock *LLVM_BB = BB->getBasicBlock();
17527 
17528  assert(MF->shouldSplitStack());
17529 
17530  unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
17531  unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
17532 
17533  // BB:
17534  // ... [Till the alloca]
17535  // If stacklet is not large enough, jump to mallocMBB
17536  //
17537  // bumpMBB:
17538  // Allocate by subtracting from RSP
17539  // Jump to continueMBB
17540  //
17541  // mallocMBB:
17542  // Allocate by call to runtime
17543  //
17544  // continueMBB:
17545  // ...
17546  // [rest of original BB]
17547  //
17548 
17549  MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17550  MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17551  MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17552 
17553  MachineRegisterInfo &MRI = MF->getRegInfo();
17554  const TargetRegisterClass *AddrRegClass =
17555  getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
17556 
17557  unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
17558  bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
17559  tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
17560  SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
17561  sizeVReg = MI->getOperand(1).getReg(),
17562  physSPReg = Is64Bit ? X86::RSP : X86::ESP;
17563 
17564  MachineFunction::iterator MBBIter = BB;
17565  ++MBBIter;
17566 
17567  MF->insert(MBBIter, bumpMBB);
17568  MF->insert(MBBIter, mallocMBB);
17569  MF->insert(MBBIter, continueMBB);
17570 
17571  continueMBB->splice(continueMBB->begin(), BB,
17572  std::next(MachineBasicBlock::iterator(MI)), BB->end());
17573  continueMBB->transferSuccessorsAndUpdatePHIs(BB);
17574 
17575  // Add code to the main basic block to check if the stack limit has been hit,
17576  // and if so, jump to mallocMBB otherwise to bumpMBB.
17577  BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
17578  BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
17579  .addReg(tmpSPVReg).addReg(sizeVReg);
17580  BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
17581  .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
17582  .addReg(SPLimitVReg);
17583  BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
17584 
17585  // bumpMBB simply decreases the stack pointer, since we know the current
17586  // stacklet has enough space.
17587  BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
17588  .addReg(SPLimitVReg);
17589  BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
17590  .addReg(SPLimitVReg);
17591  BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
17592 
17593  // Calls into a routine in libgcc to allocate more space from the heap.
17594  const uint32_t *RegMask =
17595  MF->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
17596  if (Is64Bit) {
17597  BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
17598  .addReg(sizeVReg);
17599  BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
17600  .addExternalSymbol("__morestack_allocate_stack_space")
17601  .addRegMask(RegMask)
17602  .addReg(X86::RDI, RegState::Implicit)
17603  .addReg(X86::RAX, RegState::ImplicitDefine);
17604  } else {
17605  BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
17606  .addImm(12);
17607  BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
17608  BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
17609  .addExternalSymbol("__morestack_allocate_stack_space")
17610  .addRegMask(RegMask)
17611  .addReg(X86::EAX, RegState::ImplicitDefine);
17612  }
17613 
17614  if (!Is64Bit)
17615  BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
17616  .addImm(16);
17617 
17618  BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
17619  .addReg(Is64Bit ? X86::RAX : X86::EAX);
17620  BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
17621 
17622  // Set up the CFG correctly.
17623  BB->addSuccessor(bumpMBB);
17624  BB->addSuccessor(mallocMBB);
17625  mallocMBB->addSuccessor(continueMBB);
17626  bumpMBB->addSuccessor(continueMBB);
17627 
17628  // Take care of the PHI nodes.
17629  BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
17630  MI->getOperand(0).getReg())
17631  .addReg(mallocPtrVReg).addMBB(mallocMBB)
17632  .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
17633 
17634  // Delete the original pseudo instruction.
17635  MI->eraseFromParent();
17636 
17637  // And we're done.
17638  return continueMBB;
17639 }
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Definition: MachineBasicBlock.h:137
llvm::MachineRegisterInfo::createVirtualRegister
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
Definition: MachineRegisterInfo.cpp:97
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(CallingConv::ID) const
Definition: TargetRegisterInfo.h:444
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
Definition: MachineBasicBlock.cpp:598
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:114
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Definition: MachineInstrBuilder.h:83
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
Definition: MachineFunction.cpp:215
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Definition: MachineBasicBlock.h:117
assert
assert(Globals.size() > 1)
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:72
llvm::MachineBasicBlock::bundle_iterator
Definition: MachineBasicBlock.h:144
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
llvm::MachineFunction::shouldSplitStack
bool shouldSplitStack()
Should we be emitting segmented stack stuff for the function.
Definition: MachineFunction.cpp:129
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
Definition: MachineInstrBuilder.h:228
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
llvm::TargetMachine::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: Target/TargetMachine.h:118
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Definition: TargetLowering.h:314
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Definition: MachineBasicBlock.h:565
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
Definition: MachineFunction.h:167
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::MachineOperand::getReg
unsigned getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:264
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:331
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:98
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:300
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:149
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Definition: MachineInstrBuilder.h:64
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
Definition: MachineBasicBlock.cpp:488
llvm::MachineInstr::getDebugLoc
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
MachineBasicBlock * X86TargetLowering::EmitLoweredSelect ( MachineInstr *  I,
MachineBasicBlock *  BB 
) const
private

Definition at line 17454 of file X86ISelLowering.cpp.

17455  {
17456  const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
17457  DebugLoc DL = MI->getDebugLoc();
17458 
17459  // To "insert" a SELECT_CC instruction, we actually have to insert the
17460  // diamond control-flow pattern. The incoming instruction knows the
17461  // destination vreg to set, the condition code register to branch on, the
17462  // true/false values to select between, and a branch opcode to use.
17463  const BasicBlock *LLVM_BB = BB->getBasicBlock();
17464  MachineFunction::iterator It = BB;
17465  ++It;
17466 
17467  // thisMBB:
17468  // ...
17469  // TrueVal = ...
17470  // cmpTY ccX, r1, r2
17471  // bCC copy1MBB
17472  // fallthrough --> copy0MBB
17473  MachineBasicBlock *thisMBB = BB;
17474  MachineFunction *F = BB->getParent();
17475  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
17476  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
17477  F->insert(It, copy0MBB);
17478  F->insert(It, sinkMBB);
17479 
17480  // If the EFLAGS register isn't dead in the terminator, then claim that it's
17481  // live into the sink and copy blocks.
17482  const TargetRegisterInfo* TRI = BB->getParent()->getTarget().getRegisterInfo();
17483  if (!MI->killsRegister(X86::EFLAGS) &&
17484  !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
17485  copy0MBB->addLiveIn(X86::EFLAGS);
17486  sinkMBB->addLiveIn(X86::EFLAGS);
17487  }
17488 
17489  // Transfer the remainder of BB and its successor edges to sinkMBB.
17490  sinkMBB->splice(sinkMBB->begin(), BB,
17491  std::next(MachineBasicBlock::iterator(MI)), BB->end());
17492  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
17493 
17494  // Add the true and fallthrough blocks as its successors.
17495  BB->addSuccessor(copy0MBB);
17496  BB->addSuccessor(sinkMBB);
17497 
17498  // Create the conditional branch instruction.
17499  unsigned Opc =
17500  X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
17501  BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
17502 
17503  // copy0MBB:
17504  // %FalseValue = ...
17505  // # fallthrough to sinkMBB
17506  copy0MBB->addSuccessor(sinkMBB);
17507 
17508  // sinkMBB:
17509  // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
17510  // ...
17511  BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17512  TII->get(X86::PHI), MI->getOperand(0).getReg())
17513  .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
17514  .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
17515 
17516  MI->eraseFromParent(); // The pseudo instruction is gone now.
17517  return sinkMBB;
17518 }
llvm::X86::GetCondBranchFromCond
unsigned GetCondBranchFromCond(CondCode CC)
Definition: X86InstrInfo.cpp:2606
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Definition: MachineBasicBlock.h:137
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(unsigned Reg)
Definition: MachineBasicBlock.h:320
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
Definition: MachineBasicBlock.cpp:598
F
F(f)
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:114
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
Definition: MachineFunction.cpp:215
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Definition: MachineBasicBlock.h:117
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:72
llvm::MachineBasicBlock::bundle_iterator
Definition: MachineBasicBlock.h:144
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
Definition: MachineInstrBuilder.h:228
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
llvm::TargetMachine::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: Target/TargetMachine.h:118
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Definition: MachineBasicBlock.h:565
checkAndUpdateEFLAGSKill
static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr, MachineBasicBlock *BB, const TargetRegisterInfo *TRI)
Definition: X86ISelLowering.cpp:17422
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:331
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:300
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Definition: MachineInstrBuilder.h:64
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
Definition: MachineBasicBlock.cpp:488
MachineBasicBlock* llvm::X86TargetLowering::emitLoweredTLSAddr ( MachineInstr *  MI,
MachineBasicBlock *  BB 
) const
private
MachineBasicBlock * X86TargetLowering::EmitLoweredTLSCall ( MachineInstr *  MI,
MachineBasicBlock *  BB 
) const
private

Definition at line 17694 of file X86ISelLowering.cpp.

17695  {
17696  // This is pretty easy. We're taking the value that we received from
17697  // our load from the relocation, sticking it in either RDI (x86-64)
17698  // or EAX and doing an indirect call. The return value will then
17699  // be in the normal return register.
17700  MachineFunction *F = BB->getParent();
17701  const X86InstrInfo *TII
17702  = static_cast<const X86InstrInfo*>(F->getTarget().getInstrInfo());
17703  DebugLoc DL = MI->getDebugLoc();
17704 
17705  assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
17706  assert(MI->getOperand(3).isGlobal() && "This should be a global");
17707 
17708  // Get a register mask for the lowered call.
17709  // FIXME: The 32-bit calls have non-standard calling conventions. Use a
17710  // proper register mask.
17711  const uint32_t *RegMask =
17712  F->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
17713  if (Subtarget->is64Bit()) {
17714  MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17715  TII->get(X86::MOV64rm), X86::RDI)
17716  .addReg(X86::RIP)
17717  .addImm(0).addReg(0)
17718  .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17719  MI->getOperand(3).getTargetFlags())
17720  .addReg(0);
17721  MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
17722  addDirectMem(MIB, X86::RDI);
17723  MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
17724  } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
17725  MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17726  TII->get(X86::MOV32rm), X86::EAX)
17727  .addReg(0)
17728  .addImm(0).addReg(0)
17729  .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17730  MI->getOperand(3).getTargetFlags())
17731  .addReg(0);
17732  MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
17733  addDirectMem(MIB, X86::EAX);
17734  MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
17735  } else {
17736  MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17737  TII->get(X86::MOV32rm), X86::EAX)
17738  .addReg(TII->getGlobalBaseReg(F))
17739  .addImm(0).addReg(0)
17740  .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17741  MI->getOperand(3).getTargetFlags())
17742  .addReg(0);
17743  MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
17744  addDirectMem(MIB, X86::EAX);
17745  MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
17746  }
17747 
17748  MI->eraseFromParent(); // The pseudo instruction is gone now.
17749  return BB;
17750 }
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Definition: MachineBasicBlock.h:137
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:433
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Definition: TargetMachine.cpp:76
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(CallingConv::ID) const
Definition: TargetRegisterInfo.h:444
F
F(f)
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:114
llvm::X86Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: X86Subtarget.h:370
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Definition: MachineInstrBuilder.h:83
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:245
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:190
assert
assert(Globals.size() > 1)
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
Definition: MachineInstrBuilder.h:228
llvm::TargetMachine::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: Target/TargetMachine.h:118
llvm::X86InstrInfo::getGlobalBaseReg
unsigned getGlobalBaseReg(MachineFunction *MF) const
Definition: X86InstrInfo.cpp:5170
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:129
llvm::addDirectMem
static const MachineInstrBuilder & addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg)
Definition: X86InstrBuilder.h:91
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::MachineInstrBuilder::addRegMask
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
Definition: MachineInstrBuilder.h:149
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Definition: MachineInstrBuilder.h:64
llvm::MachineInstr::getDebugLoc
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
MachineBasicBlock * X86TargetLowering::EmitLoweredWinAlloca ( MachineInstr *  MI,
MachineBasicBlock *  BB 
) const
private

Definition at line 17642 of file X86ISelLowering.cpp.

17643  {
17644  const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
17645  DebugLoc DL = MI->getDebugLoc();
17646 
17647  assert(!Subtarget->isTargetMacho());
17648 
17649  // The lowering is pretty easy: we're just emitting the call to _alloca. The
17650  // non-trivial part is impdef of ESP.
17651 
17652  if (Subtarget->isTargetWin64()) {
17653  if (Subtarget->isTargetCygMing()) {
17654  // ___chkstk(Mingw64):
17655  // Clobbers R10, R11, RAX and EFLAGS.
17656  // Updates RSP.
17657  BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
17658  .addExternalSymbol("___chkstk")
17659  .addReg(X86::RAX, RegState::Implicit)
17660  .addReg(X86::RSP, RegState::Implicit)
17661  .addReg(X86::RAX, RegState::Define | RegState::Implicit)
17662  .addReg(X86::RSP, RegState::Define | RegState::Implicit)
17663  .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17664  } else {
17665  // __chkstk(MSVCRT): does not update stack pointer.
17666  // Clobbers R10, R11 and EFLAGS.
17667  BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
17668  .addExternalSymbol("__chkstk")
17669  .addReg(X86::RAX, RegState::Implicit)
17670  .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17671  // RAX has the offset to be subtracted from RSP.
17672  BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
17673  .addReg(X86::RSP)
17674  .addReg(X86::RAX);
17675  }
17676  } else {
17677  const char *StackProbeSymbol =
17678  Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
17679 
17680  BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
17681  .addExternalSymbol(StackProbeSymbol)
17682  .addReg(X86::EAX, RegState::Implicit)
17683  .addReg(X86::ESP, RegState::Implicit)
17684  .addReg(X86::EAX, RegState::Define | RegState::Implicit)
17685  .addReg(X86::ESP, RegState::Define | RegState::Implicit)
17686  .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17687  }
17688 
17689  MI->eraseFromParent(); // The pseudo instruction is gone now.
17690  return BB;
17691 }
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Definition: MachineBasicBlock.h:137
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86Subtarget::isTargetCygMing
bool isTargetCygMing() const
Definition: X86Subtarget.h:403
llvm::X86Subtarget::isTargetMacho
bool isTargetMacho() const
Definition: X86Subtarget.h:380
llvm::X86Subtarget::isTargetKnownWindowsMSVC
bool isTargetKnownWindowsMSVC() const
Definition: X86Subtarget.h:391
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:114
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
assert
assert(Globals.size() > 1)
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
Definition: MachineInstrBuilder.h:228
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
llvm::TargetMachine::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: Target/TargetMachine.h:118
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
llvm::X86Subtarget::isTargetWin64
bool isTargetWin64() const
Definition: X86Subtarget.h:407
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Definition: MachineInstrBuilder.h:64
llvm::MachineInstr::getDebugLoc
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
MachineBasicBlock * TargetLoweringBase::emitPatchPoint ( MachineInstr *  MI,
MachineBasicBlock *  MBB 
) const
protectedinherited

Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that is recognized by PrologEpilogInserter.

Definition at line 946 of file TargetLoweringBase.cpp.

947  {
948  MachineFunction &MF = *MI->getParent()->getParent();
949 
950  // MI changes inside this loop as we grow operands.
951  for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
952  MachineOperand &MO = MI->getOperand(OperIdx);
953  if (!MO.isFI())
954  continue;
955 
956  // foldMemoryOperand builds a new MI after replacing a single FI operand
957  // with the canonical set of five x86 addressing-mode operands.
958  int FI = MO.getIndex();
959  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
960 
961  // Copy operands before the frame-index.
962  for (unsigned i = 0; i < OperIdx; ++i)
963  MIB.addOperand(MI->getOperand(i));
964  // Add frame index operands: direct-mem-ref tag, #FI, offset.
965  MIB.addImm(StackMaps::DirectMemRefOp);
966  MIB.addOperand(MI->getOperand(OperIdx));
967  MIB.addImm(0);
968  // Copy the operands after the frame index.
969  for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
970  MIB.addOperand(MI->getOperand(i));
971 
972  // Inherit previous memory operands.
973  MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
974  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
975 
976  // Add a new memory operand for this FI.
977  const MachineFrameInfo &MFI = *MF.getFrameInfo();
978  assert(MFI.getObjectOffset(FI) != -1);
979  MachineMemOperand *MMO =
980  MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
981  MachineMemOperand::MOLoad,
982  TM.getDataLayout()->getPointerSize(),
983  MFI.getObjectAlignment(FI));
984  MIB->addMemOperand(MF, MMO);
985 
986  // Replace the instruction and update the operand index.
987  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
988  OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
989  MI->eraseFromParent();
990  MI = MIB;
991  }
992  return MBB;
993 }
llvm::MachineMemOperand::MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:101
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Definition: MachineBasicBlock.h:137
llvm::TargetLoweringBase::TM
const TargetMachine & TM
True if this is a little endian target.
Definition: TargetLowering.h:1452
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Definition: MachineInstr.h:266
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
Definition: MachineInstr.cpp:414
llvm::MachineInstr::mayLoad
bool mayLoad(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:520
llvm::MachineFrameInfo
Abstract Stack Frame Information.
Definition: MachineFrameInfo.h:80
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Definition: MachineInstrBuilder.h:83
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Definition: MachineInstr.h:274
llvm::MachineOperand::isFI
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
Definition: MachineOperand.h:237
llvm::MachineInstr::addMemOperand
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Definition: MachineInstr.cpp:761
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:120
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:340
assert
assert(Globals.size() > 1)
llvm::MachineBasicBlock::bundle_iterator
Definition: MachineBasicBlock.h:144
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
Definition: MachineInstrBuilder.h:228
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: MachineFunction.cpp:230
llvm::TargetMachine::getDataLayout
virtual const DataLayout * getDataLayout() const
Definition: Target/TargetMachine.h:126
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
llvm::MachineInstrBuilder::addOperand
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:166
llvm::DataLayout::getPointerSize
unsigned getPointerSize(unsigned AS=0) const
Definition: DataLayout.cpp:602
llvm::MachineInstr::setMemRefs
void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd)
Definition: MachineInstr.h:1098
llvm::MachineInstr::getDebugLoc
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:339
virtual Value* llvm::TargetLoweringBase::emitStoreConditional ( IRBuilder<> &  Builder,
Value *  Val,
Value *  Addr,
AtomicOrdering  Ord 
) const
inlinevirtualinherited

Perform a store-conditional operation to Addr. Return the status of the store. This should be 0 if the store succeeded, non-zero otherwise.

Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 939 of file TargetLowering.h.

940  {
941  llvm_unreachable("Store conditional unimplemented on this target");
942  }
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
SDValue X86TargetLowering::EmitTailCallLoadRetAddr ( SelectionDAG &  DAG,
SDValue &  OutRetAddr,
SDValue  Chain,
bool  IsTailCall,
bool  Is64Bit,
int  FPDiff,
SDLoc  dl 
) const
private

EmitTailCallLoadRetAddr - Emit a load of return address if tail call optimization is performed and it is required.

Definition at line 2550 of file X86ISelLowering.cpp.

2553  {
2554  // Adjust the Return address stack slot.
2555  EVT VT = getPointerTy();
2556  OutRetAddr = getReturnAddressFrameIndex(DAG);
2557 
2558  // Load the "old" Return address.
2559  OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2560  false, false, false, 0);
2561  return SDValue(OutRetAddr.getNode(), 1);
2562 }
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::X86TargetLowering::getReturnAddressFrameIndex
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:3460
SDValue X86TargetLowering::EmitTest ( SDValue  Op,
unsigned  X86CC,
SDLoc  dl,
SelectionDAG &  DAG 
) const
private

Emit nodes that will be selected as "test Op0,Op0", or something equivalent, for use with the given x86 condition code.

Emit nodes that will be selected as "test Op0,Op0", or something equivalent.

Definition at line 11654 of file X86ISelLowering.cpp.

11655  {
11656  if (Op.getValueType() == MVT::i1)
11657  // KORTEST instruction should be selected
11658  return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11659  DAG.getConstant(0, Op.getValueType()));
11660 
11661  // CF and OF aren't always set the way we want. Determine which
11662  // of these we need.
11663  bool NeedCF = false;
11664  bool NeedOF = false;
11665  switch (X86CC) {
11666  default: break;
11667  case X86::COND_A: case X86::COND_AE:
11668  case X86::COND_B: case X86::COND_BE:
11669  NeedCF = true;
11670  break;
11671  case X86::COND_G: case X86::COND_GE:
11672  case X86::COND_L: case X86::COND_LE:
11673  case X86::COND_O: case X86::COND_NO: {
11674  // Check if we really need to set the
11675  // Overflow flag. If NoSignedWrap is present
11676  // that is not actually needed.
11677  switch (Op->getOpcode()) {
11678  case ISD::ADD:
11679  case ISD::SUB:
11680  case ISD::MUL:
11681  case ISD::SHL: {
11682  const BinaryWithFlagsSDNode *BinNode =
11683  cast<BinaryWithFlagsSDNode>(Op.getNode());
11684  if (BinNode->hasNoSignedWrap())
11685  break;
11686  }
11687  default:
11688  NeedOF = true;
11689  break;
11690  }
11691  break;
11692  }
11693  }
11694  // See if we can use the EFLAGS value from the operand instead of
11695  // doing a separate TEST. TEST always sets OF and CF to 0, so unless
11696  // we prove that the arithmetic won't overflow, we can't use OF or CF.
11697  if (Op.getResNo() != 0 || NeedOF || NeedCF) {
11698  // Emit a CMP with 0, which is the TEST pattern.
11699  //if (Op.getValueType() == MVT::i1)
11700  // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
11701  // DAG.getConstant(0, MVT::i1));
11702  return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11703  DAG.getConstant(0, Op.getValueType()));
11704  }
11705  unsigned Opcode = 0;
11706  unsigned NumOperands = 0;
11707 
11708  // Truncate operations may prevent the merge of the SETCC instruction
11709  // and the arithmetic instruction before it. Attempt to truncate the operands
11710  // of the arithmetic instruction and use a reduced bit-width instruction.
11711  bool NeedTruncation = false;
11712  SDValue ArithOp = Op;
11713  if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
11714  SDValue Arith = Op->getOperand(0);
11715  // Both the trunc and the arithmetic op need to have one user each.
11716  if (Arith->hasOneUse())
11717  switch (Arith.getOpcode()) {
11718  default: break;
11719  case ISD::ADD:
11720  case ISD::SUB:
11721  case ISD::AND:
11722  case ISD::OR:
11723  case ISD::XOR: {
11724  NeedTruncation = true;
11725  ArithOp = Arith;
11726  }
11727  }
11728  }
11729 
11730  // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
11731  // which may be the result of a CAST. We use the variable 'Op', which is the
11732  // non-casted variable when we check for possible users.
11733  switch (ArithOp.getOpcode()) {
11734  case ISD::ADD:
11735  // Due to an isel shortcoming, be conservative if this add is likely to be
11736  // selected as part of a load-modify-store instruction. When the root node
11737  // in a match is a store, isel doesn't know how to remap non-chain non-flag
11738  // uses of other nodes in the match, such as the ADD in this case. This
11739  // leads to the ADD being left around and reselected, with the result being
11740  // two adds in the output. Alas, even if none our users are stores, that
11741  // doesn't prove we're O.K. Ergo, if we have any parents that aren't
11742  // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
11743  // climbing the DAG back to the root, and it doesn't seem to be worth the
11744  // effort.
11745  for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11746  UE = Op.getNode()->use_end(); UI != UE; ++UI)
11747  if (UI->getOpcode() != ISD::CopyToReg &&
11748  UI->getOpcode() != ISD::SETCC &&
11749  UI->getOpcode() != ISD::STORE)
11750  goto default_case;
11751 
11752  if (ConstantSDNode *C =
11753  dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
11754  // An add of one will be selected as an INC.
11755  if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
11756  Opcode = X86ISD::INC;
11757  NumOperands = 1;
11758  break;
11759  }
11760 
11761  // An add of negative one (subtract of one) will be selected as a DEC.
11762  if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
11763  Opcode = X86ISD::DEC;
11764  NumOperands = 1;
11765  break;
11766  }
11767  }
11768 
11769  // Otherwise use a regular EFLAGS-setting add.
11770  Opcode = X86ISD::ADD;
11771  NumOperands = 2;
11772  break;
11773  case ISD::SHL:
11774  case ISD::SRL:
11775  // If we have a constant logical shift that's only used in a comparison
11776  // against zero turn it into an equivalent AND. This allows turning it into
11777  // a TEST instruction later.
11778  if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
11779  isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
11780  EVT VT = Op.getValueType();
11781  unsigned BitWidth = VT.getSizeInBits();
11782  unsigned ShAmt = Op->getConstantOperandVal(1);
11783  if (ShAmt >= BitWidth) // Avoid undefined shifts.
11784  break;
11785  APInt Mask = ArithOp.getOpcode() == ISD::SRL
11786  ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
11787  : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
11788  if (!Mask.isSignedIntN(32)) // Avoid large immediates.
11789  break;
11790  SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
11791  DAG.getConstant(Mask, VT));
11792  DAG.ReplaceAllUsesWith(Op, New);
11793  Op = New;
11794  }
11795  break;
11796 
11797  case ISD::AND:
11798  // If the primary and result isn't used, don't bother using X86ISD::AND,
11799  // because a TEST instruction will be better.
11800  if (!hasNonFlagsUse(Op))
11801  break;
11802  // FALL THROUGH
11803  case ISD::SUB:
11804  case ISD::OR:
11805  case ISD::XOR:
11806  // Due to the ISEL shortcoming noted above, be conservative if this op is
11807  // likely to be selected as part of a load-modify-store instruction.
11808  for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11809  UE = Op.getNode()->use_end(); UI != UE; ++UI)
11810  if (UI->getOpcode() == ISD::STORE)
11811  goto default_case;
11812 
11813  // Otherwise use a regular EFLAGS-setting instruction.
11814  switch (ArithOp.getOpcode()) {
11815  default: llvm_unreachable("unexpected operator!");
11816  case ISD::SUB: Opcode = X86ISD::SUB; break;
11817  case ISD::XOR: Opcode = X86ISD::XOR; break;
11818  case ISD::AND: Opcode = X86ISD::AND; break;
11819  case ISD::OR: {
11820  if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
11821  SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
11822  if (EFLAGS.getNode())
11823  return EFLAGS;
11824  }
11825  Opcode = X86ISD::OR;
11826  break;
11827  }
11828  }
11829 
11830  NumOperands = 2;
11831  break;
11832  case X86ISD::ADD:
11833  case X86ISD::SUB:
11834  case X86ISD::INC:
11835  case X86ISD::DEC:
11836  case X86ISD::OR:
11837  case X86ISD::XOR:
11838  case X86ISD::AND:
11839  return SDValue(Op.getNode(), 1);
11840  default:
11841  default_case:
11842  break;
11843  }
11844 
11845  // If we found that truncation is beneficial, perform the truncation and
11846  // update 'Op'.
11847  if (NeedTruncation) {
11848  EVT VT = Op.getValueType();
11849  SDValue WideVal = Op->getOperand(0);
11850  EVT WideVT = WideVal.getValueType();
11851  unsigned ConvertedOp = 0;
11852  // Use a target machine opcode to prevent further DAGCombine
11853  // optimizations that may separate the arithmetic operations
11854  // from the setcc node.
11855  switch (WideVal.getOpcode()) {
11856  default: break;
11857  case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
11858  case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
11859  case ISD::AND: ConvertedOp = X86ISD::AND; break;
11860  case ISD::OR: ConvertedOp = X86ISD::OR; break;
11861  case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
11862  }
11863 
11864  if (ConvertedOp) {
11865  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11866  if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
11867  SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
11868  SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
11869  Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
11870  }
11871  }
11872  }
11873 
11874  if (Opcode == 0)
11875  // Emit a CMP with 0, which is the TEST pattern.
11876  return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11877  DAG.getConstant(0, Op.getValueType()));
11878 
11879  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11880  SmallVector<SDValue, 4> Ops;
11881  for (unsigned i = 0; i != NumOperands; ++i)
11882  Ops.push_back(Op.getOperand(i));
11883 
11884  SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
11885  DAG.ReplaceAllUsesWith(Op, New);
11886  return SDValue(New.getNode(), 1);
11887 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SDNode::hasOneUse
bool hasOneUse() const
Definition: SelectionDAGNodes.h:438
llvm::X86Subtarget::slowIncDec
bool slowIncDec() const
Definition: X86Subtarget.h:357
llvm::SDNode::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:401
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:592
hasNonFlagsUse
static bool hasNonFlagsUse(SDValue Op)
return true if Op has a use that doesn't just read flags.
Definition: X86ISelLowering.cpp:11634
llvm::SDValue::getResNo
unsigned getResNo() const
get the index which selects a specific result in the SDNode
Definition: SelectionDAGNodes.h:127
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::X86ISD::CMP
X86 compare and logical compare instructions.
Definition: X86ISelLowering.h:93
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::APInt::getHighBitsSet
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::TargetLoweringBase::isOperationLegal
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
Definition: TargetLowering.h:512
llvm::SDNode::use_iterator
Definition: SelectionDAGNodes.h:471
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::SDNode::use_begin
use_iterator use_begin() const
Definition: SelectionDAGNodes.h:528
LowerVectorAllZeroTest
static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:11542
llvm::SDNode::getConstantOperandVal
uint64_t getConstantOperandVal(unsigned Num) const
Definition: SelectionDAG.cpp:6446
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::APInt::isSignedIntN
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
Definition: APInt.h:380
llvm::SDNode::use_end
static use_iterator use_end()
Definition: SelectionDAGNodes.h:532
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
llvm::SelectionDAG::ReplaceAllUsesWith
void ReplaceAllUsesWith(SDValue From, SDValue Op)
Definition: SelectionDAG.cpp:5852
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::SelectionDAG::getTargetLoweringInfo
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
MachineBasicBlock * X86TargetLowering::EmitVAARG64WithCustomInserter ( MachineInstr *  MI,
MachineBasicBlock *  MBB 
) const
private

Definition at line 17085 of file X86ISelLowering.cpp.

17087  {
17088  // Emit va_arg instruction on X86-64.
17089 
17090  // Operands to this pseudo-instruction:
17091  // 0 ) Output : destination address (reg)
17092  // 1-5) Input : va_list address (addr, i64mem)
17093  // 6 ) ArgSize : Size (in bytes) of vararg type
17094  // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17095  // 8 ) Align : Alignment of type
17096  // 9 ) EFLAGS (implicit-def)
17097 
17098  assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17099  assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17100 
17101  unsigned DestReg = MI->getOperand(0).getReg();
17102  MachineOperand &Base = MI->getOperand(1);
17103  MachineOperand &Scale = MI->getOperand(2);
17104  MachineOperand &Index = MI->getOperand(3);
17105  MachineOperand &Disp = MI->getOperand(4);
17106  MachineOperand &Segment = MI->getOperand(5);
17107  unsigned ArgSize = MI->getOperand(6).getImm();
17108  unsigned ArgMode = MI->getOperand(7).getImm();
17109  unsigned Align = MI->getOperand(8).getImm();
17110 
17111  // Memory Reference
17112  assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17113  MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17114  MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17115 
17116  // Machine Information
17117  const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
17118  MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17119  const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17120  const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17121  DebugLoc DL = MI->getDebugLoc();
17122 
17123  // struct va_list {
17124  // i32 gp_offset
17125  // i32 fp_offset
17126  // i64 overflow_area (address)
17127  // i64 reg_save_area (address)
17128  // }
17129  // sizeof(va_list) = 24
17130  // alignment(va_list) = 8
17131 
17132  unsigned TotalNumIntRegs = 6;
17133  unsigned TotalNumXMMRegs = 8;
17134  bool UseGPOffset = (ArgMode == 1);
17135  bool UseFPOffset = (ArgMode == 2);
17136  unsigned MaxOffset = TotalNumIntRegs * 8 +
17137  (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17138 
17139  /* Align ArgSize to a multiple of 8 */
17140  unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17141  bool NeedsAlign = (Align > 8);
17142 
17143  MachineBasicBlock *thisMBB = MBB;
17144  MachineBasicBlock *overflowMBB;
17145  MachineBasicBlock *offsetMBB;
17146  MachineBasicBlock *endMBB;
17147 
17148  unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17149  unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17150  unsigned OffsetReg = 0;
17151 
17152  if (!UseGPOffset && !UseFPOffset) {
17153  // If we only pull from the overflow region, we don't create a branch.
17154  // We don't need to alter control flow.
17155  OffsetDestReg = 0; // unused
17156  OverflowDestReg = DestReg;
17157 
17158  offsetMBB = nullptr;
17159  overflowMBB = thisMBB;
17160  endMBB = thisMBB;
17161  } else {
17162  // First emit code to check if gp_offset (or fp_offset) is below the bound.
17163  // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17164  // If not, pull from overflow_area. (branch to overflowMBB)
17165  //
17166  // thisMBB
17167  // | .
17168  // | .
17169  // offsetMBB overflowMBB
17170  // | .
17171  // | .
17172  // endMBB
17173 
17174  // Registers for the PHI in endMBB
17175  OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17176  OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17177 
17178  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17179  MachineFunction *MF = MBB->getParent();
17180  overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17181  offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17182  endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17183 
17184  MachineFunction::iterator MBBIter = MBB;
17185  ++MBBIter;
17186 
17187  // Insert the new basic blocks
17188  MF->insert(MBBIter, offsetMBB);
17189  MF->insert(MBBIter, overflowMBB);
17190  MF->insert(MBBIter, endMBB);
17191 
17192  // Transfer the remainder of MBB and its successor edges to endMBB.
17193  endMBB->splice(endMBB->begin(), thisMBB,
17194  std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
17195  endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
17196 
17197  // Make offsetMBB and overflowMBB successors of thisMBB
17198  thisMBB->addSuccessor(offsetMBB);
17199  thisMBB->addSuccessor(overflowMBB);
17200 
17201  // endMBB is a successor of both offsetMBB and overflowMBB
17202  offsetMBB->addSuccessor(endMBB);
17203  overflowMBB->addSuccessor(endMBB);
17204 
17205  // Load the offset value into a register
17206  OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17207  BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
17208  .addOperand(Base)
17209  .addOperand(Scale)
17210  .addOperand(Index)
17211  .addDisp(Disp, UseFPOffset ? 4 : 0)
17212  .addOperand(Segment)
17213  .setMemRefs(MMOBegin, MMOEnd);
17214 
17215  // Check if there is enough room left to pull this argument.
17216  BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
17217  .addReg(OffsetReg)
17218  .addImm(MaxOffset + 8 - ArgSizeA8);
17219 
17220  // Branch to "overflowMBB" if offset >= max
17221  // Fall through to "offsetMBB" otherwise
17222  BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
17223  .addMBB(overflowMBB);
17224  }
17225 
17226  // In offsetMBB, emit code to use the reg_save_area.
17227  if (offsetMBB) {
17228  assert(OffsetReg != 0);
17229 
17230  // Read the reg_save_area address.
17231  unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
17232  BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
17233  .addOperand(Base)
17234  .addOperand(Scale)
17235  .addOperand(Index)
17236  .addDisp(Disp, 16)
17237  .addOperand(Segment)
17238  .setMemRefs(MMOBegin, MMOEnd);
17239 
17240  // Zero-extend the offset
17241  unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
17242  BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
17243  .addImm(0)
17244  .addReg(OffsetReg)
17245  .addImm(X86::sub_32bit);
17246 
17247  // Add the offset to the reg_save_area to get the final address.
17248  BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
17249  .addReg(OffsetReg64)
17250  .addReg(RegSaveReg);
17251 
17252  // Compute the offset for the next argument
17253  unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17254  BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
17255  .addReg(OffsetReg)
17256  .addImm(UseFPOffset ? 16 : 8);
17257 
17258  // Store it back into the va_list.
17259  BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
17260  .addOperand(Base)
17261  .addOperand(Scale)
17262  .addOperand(Index)
17263  .addDisp(Disp, UseFPOffset ? 4 : 0)
17264  .addOperand(Segment)
17265  .addReg(NextOffsetReg)
17266  .setMemRefs(MMOBegin, MMOEnd);
17267 
17268  // Jump to endMBB
17269  BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
17270  .addMBB(endMBB);
17271  }
17272 
17273  //
17274  // Emit code to use overflow area
17275  //
17276 
17277  // Load the overflow_area address into a register.
17278  unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
17279  BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
17280  .addOperand(Base)
17281  .addOperand(Scale)
17282  .addOperand(Index)
17283  .addDisp(Disp, 8)
17284  .addOperand(Segment)
17285  .setMemRefs(MMOBegin, MMOEnd);
17286 
17287  // If we need to align it, do so. Otherwise, just copy the address
17288  // to OverflowDestReg.
17289  if (NeedsAlign) {
17290  // Align the overflow address
17291  assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
17292  unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
17293 
17294  // aligned_addr = (addr + (align-1)) & ~(align-1)
17295  BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
17296  .addReg(OverflowAddrReg)
17297  .addImm(Align-1);
17298 
17299  BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
17300  .addReg(TmpReg)
17301  .addImm(~(uint64_t)(Align-1));
17302  } else {
17303  BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
17304  .addReg(OverflowAddrReg);
17305  }
17306 
17307  // Compute the next overflow address after this argument.
17308  // (the overflow address should be kept 8-byte aligned)
17309  unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
17310  BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
17311  .addReg(OverflowDestReg)
17312  .addImm(ArgSizeA8);
17313 
17314  // Store the new overflow address.
17315  BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
17316  .addOperand(Base)
17317  .addOperand(Scale)
17318  .addOperand(Index)
17319  .addDisp(Disp, 8)
17320  .addOperand(Segment)
17321  .addReg(NextAddrReg)
17322  .setMemRefs(MMOBegin, MMOEnd);
17323 
17324  // If we branched, emit the PHI to the front of endMBB.
17325  if (offsetMBB) {
17326  BuildMI(*endMBB, endMBB->begin(), DL,
17327  TII->get(X86::PHI), DestReg)
17328  .addReg(OffsetDestReg).addMBB(offsetMBB)
17329  .addReg(OverflowDestReg).addMBB(overflowMBB);
17330  }
17331 
17332  // Erase the pseudo instruction
17333  MI->eraseFromParent();
17334 
17335  return endMBB;
17336 }
llvm::X86::GetCondBranchFromCond
unsigned GetCondBranchFromCond(CondCode CC)
Definition: X86InstrInfo.cpp:2606
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Definition: MachineBasicBlock.h:137
llvm::MachineRegisterInfo::createVirtualRegister
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
Definition: MachineRegisterInfo.cpp:97
MaxOffset
unsigned MaxOffset
Definition: GlobalMerge.cpp:151
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
Definition: MachineBasicBlock.cpp:598
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:114
llvm::MachineInstrBuilder::addDisp
const MachineInstrBuilder & addDisp(const MachineOperand &Disp, int64_t off, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:197
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Definition: MachineInstrBuilder.h:83
llvm::MachineInstr::getNumOperands
unsigned getNumOperands() const
Definition: MachineInstr.h:274
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:407
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
Definition: MachineFunction.cpp:215
llvm::MachineBasicBlock::getBasicBlock
const BasicBlock * getBasicBlock() const
Definition: MachineBasicBlock.h:117
llvm::MachineInstr::memoperands_end
mmo_iterator memoperands_end() const
Definition: MachineInstr.h:340
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(MachineInstr::mmo_iterator b, MachineInstr::mmo_iterator e) const
Definition: MachineInstrBuilder.h:159
assert
assert(Globals.size() > 1)
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:72
llvm::X86::AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:42
llvm::MachineBasicBlock::bundle_iterator
Definition: MachineBasicBlock.h:144
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:276
llvm::MachineInstr::hasOneMemOperand
bool hasOneMemOperand() const
Definition: MachineInstr.h:352
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
Definition: MachineInstrBuilder.h:228
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
llvm::TargetMachine::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: Target/TargetMachine.h:118
Align
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Definition: TargetLowering.h:314
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Definition: MachineBasicBlock.h:565
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
Definition: MachineFunction.h:167
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
llvm::MachineOperand::getReg
unsigned getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:264
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:331
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned char TargetFlags=0) const
Definition: MachineInstrBuilder.h:98
llvm::MachineInstrBuilder::addOperand
const MachineInstrBuilder & addOperand(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:166
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:300
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Definition: MachineInstrBuilder.h:64
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
Definition: MachineBasicBlock.cpp:488
llvm::MachineInstr::getDebugLoc
DebugLoc getDebugLoc() const
Definition: MachineInstr.h:245
llvm::MachineInstr::memoperands_begin
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:339
MachineBasicBlock * X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter ( MachineInstr *  BInstr,
MachineBasicBlock *  BB 
) const
private

Utility function to emit the xmm reg save portion of va_start.

Definition at line 17339 of file X86ISelLowering.cpp.

17341  {
17342  // Emit code to save XMM registers to the stack. The ABI says that the
17343  // number of registers to save is given in %al, so it's theoretically
17344  // possible to do an indirect jump trick to avoid saving all of them,
17345  // however this code takes a simpler approach and just executes all
17346  // of the stores if %al is non-zero. It's less code, and it's probably
17347  // easier on the hardware branch predictor, and stores aren't all that
17348  // expensive anyway.
17349 
17350  // Create the new basic blocks. One block contains all the XMM stores,
17351  // and one block is the final destination regardless of whether any
17352  // stores were performed.
17353  const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17354  MachineFunction *F = MBB->getParent();
17355  MachineFunction::iterator MBBIter = MBB;
17356  ++MBBIter;
17357  MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
17358  MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
17359  F->insert(MBBIter, XMMSaveMBB);
17360  F->insert(MBBIter, EndMBB);
17361 
17362  // Transfer the remainder of MBB and its successor edges to EndMBB.
17363  EndMBB->splice(EndMBB->begin(), MBB,
17364  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17365  EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
17366 
17367  // The original block will now fall through to the XMM save block.
17368  MBB->addSuccessor(XMMSaveMBB);
17369  // The XMMSaveMBB will fall through to the end block.
17370  XMMSaveMBB->addSuccessor(EndMBB);
17371 
17372  // Now add the instructions.
17373  const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
17374  DebugLoc DL = MI->getDebugLoc();
17375 
17376  unsigned CountReg = MI->getOperand(0).getReg();
17377  int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
17378  int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
17379 
17380  if (!Subtarget->isTargetWin64()) {
17381  // If %al is 0, branch around the XMM save block.
17382  BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
17383  BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
17384  MBB->addSuccessor(EndMBB);
17385  }
17386 
17387  // Make sure the last operand is EFLAGS, which gets clobbered by the branch
17388  // that was just emitted, but clearly shouldn't be "saved".
17389  assert((MI->getNumOperands() <= 3 ||
17390  !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
17391  MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
17392  && "Expected last argument to be EFLAGS");
17393  unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
17394  // In the XMM save block, save all the XMM argument registers.
17395  for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
17396  int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
17397  MachineMemOperand *MMO =
17398  F->getMachineMemOperand(
17399  MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
17400  MachineMemOperand::MOStore,
17401  /*Size=*/16, /*Align=*/16);
17402  BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
17403  .addFrameIndex(RegSaveFrameIndex)
17404  .addImm(/*Scale=*/1)
17405  .addReg(/*IndexReg=*/0)
17406  .addImm(/*Disp=*/Offset)
17407  .addReg(/*Segment=*/0)
17408  .addReg(MI->getOperand(i).getReg())
17409  .addMemOperand(MMO);
17410  }
17411 
17412  MI->eraseFromParent(); // The pseudo instruction is gone now.
17413 
17414  return EndMBB;
17415 }
isReg
static bool isReg(const MCInst &MI, unsigned OpNo)
Definition: MipsInstPrinter.cpp:32
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::MachineMemOperand::MOStore
The memory access writes data.
Definition: MachineMemOperand.h:103
llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB)
Definition: MachineBasicBlock.cpp:598
F
F(f)
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
Definition: MachineInstr.cpp:414
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:114
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Definition: MachineInstrBuilder.h:83
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
Definition: MachineFunction.cpp:215
assert
assert(Globals.size() > 1)
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:72
llvm::MachineBasicBlock::bundle_iterator
Definition: MachineBasicBlock.h:144
llvm::X86Subtarget::hasFp256
bool hasFp256() const
Definition: X86Subtarget.h:320
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, const MCInstrDesc &MCID)
Definition: MachineInstrBuilder.h:228
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Definition: MCInstrInfo.h:48
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:386
llvm::MachineBasicBlock::splice
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Definition: MachineBasicBlock.h:565
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: MachineFunction.cpp:230
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:331
llvm::X86Subtarget::isTargetWin64
bool isTargetWin64() const
Definition: X86Subtarget.h:407
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:300
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(unsigned RegNo, unsigned flags=0, unsigned SubReg=0) const
Definition: MachineInstrBuilder.h:64
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *succ, uint32_t weight=0)
Definition: MachineBasicBlock.cpp:488
bool TargetLowering::expandFP_TO_SINT ( SDNode *  N,
SDValue &  Result,
SelectionDAG &  DAG 
) const
inherited

Expand float(f32) to SINT(i64) conversion

Parameters
NNode to expand
Resultoutput after conversion
Returns
True, if the expansion was successful, false otherwise

Definition at line 2889 of file TargetLowering.cpp.

2890  {
2891  EVT VT = Node->getOperand(0).getValueType();
2892  EVT NVT = Node->getValueType(0);
2893  SDLoc dl(SDValue(Node, 0));
2894 
2895  // FIXME: Only f32 to i64 conversions are supported.
2896  if (VT != MVT::f32 || NVT != MVT::i64)
2897  return false;
2898 
2899  // Expand f32 -> i64 conversion
2900  // This algorithm comes from compiler-rt's implementation of fixsfdi:
2901  // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
2902  EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
2903  VT.getSizeInBits());
2904  SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
2905  SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
2906  SDValue Bias = DAG.getConstant(127, IntVT);
2907  SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
2908  IntVT);
2909  SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
2910  SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
2911 
2912  SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
2913 
2914  SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
2915  DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
2916  DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT)));
2917  SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
2918 
2919  SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
2920  DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
2921  DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT)));
2922  Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
2923 
2924  SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
2925  DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
2926  DAG.getConstant(0x00800000, IntVT));
2927 
2928  R = DAG.getZExtOrTrunc(R, dl, NVT);
2929 
2930 
2931  R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
2932  DAG.getNode(ISD::SHL, dl, NVT, R,
2933  DAG.getZExtOrTrunc(
2934  DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
2935  dl, getShiftAmountTy(IntVT))),
2936  DAG.getNode(ISD::SRL, dl, NVT, R,
2937  DAG.getZExtOrTrunc(
2938  DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
2939  dl, getShiftAmountTy(IntVT))),
2940  ISD::SETGT);
2941 
2942  SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
2943  DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
2944  Sign);
2945 
2946  Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT),
2947  DAG.getConstant(0, NVT), Ret, ISD::SETLT);
2948  return true;
2949 }
llvm::APInt::getSignBit
static APInt getSignBit(unsigned BitWidth)
Get the SignBit for a specific bit width.
Definition: APInt.h:441
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::SelectionDAG::getSelectCC
SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Definition: SelectionDAG.h:716
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy) const
Definition: TargetLoweringBase.cpp:860
Node
const DomTreeNodeT * Node
Definition: DominanceFrontierImpl.h:37
llvm::SelectionDAG::getSExtOrTrunc
SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:1003
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::SelectionDAG::getZExtOrTrunc
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:1009
llvm::EVT::getIntegerVT
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Definition: ValueTypes.h:62
bool X86TargetLowering::ExpandInlineAsm ( CallInst *  CI) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 22269 of file X86ISelLowering.cpp.

22269  {
22270  InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
22271 
22272  std::string AsmStr = IA->getAsmString();
22273 
22274  IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
22275  if (!Ty || Ty->getBitWidth() % 16 != 0)
22276  return false;
22277 
22278  // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
22279  SmallVector<StringRef, 4> AsmPieces;
22280  SplitString(AsmStr, AsmPieces, ";\n");
22281 
22282  switch (AsmPieces.size()) {
22283  default: return false;
22284  case 1:
22285  // FIXME: this should verify that we are targeting a 486 or better. If not,
22286  // we will turn this bswap into something that will be lowered to logical
22287  // ops instead of emitting the bswap asm. For now, we don't support 486 or
22288  // lower so don't worry about this.
22289  // bswap $0
22290  if (matchAsm(AsmPieces[0], "bswap", "$0") ||
22291  matchAsm(AsmPieces[0], "bswapl", "$0") ||
22292  matchAsm(AsmPieces[0], "bswapq", "$0") ||
22293  matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
22294  matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
22295  matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
22296  // No need to check constraints, nothing other than the equivalent of
22297  // "=r,0" would be valid here.
22298  return IntrinsicLowering::LowerToByteSwap(CI);
22299  }
22300 
22301  // rorw $$8, ${0:w} --> llvm.bswap.i16
22302  if (CI->getType()->isIntegerTy(16) &&
22303  IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22304  (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
22305  matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
22306  AsmPieces.clear();
22307  const std::string &ConstraintsStr = IA->getConstraintString();
22308  SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22309  array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22310  if (clobbersFlagRegisters(AsmPieces))
22311  return IntrinsicLowering::LowerToByteSwap(CI);
22312  }
22313  break;
22314  case 3:
22315  if (CI->getType()->isIntegerTy(32) &&
22316  IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22317  matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
22318  matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
22319  matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
22320  AsmPieces.clear();
22321  const std::string &ConstraintsStr = IA->getConstraintString();
22322  SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22323  array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22324  if (clobbersFlagRegisters(AsmPieces))
22325  return IntrinsicLowering::LowerToByteSwap(CI);
22326  }
22327 
22328  if (CI->getType()->isIntegerTy(64)) {
22329  InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
22330  if (Constraints.size() >= 2 &&
22331  Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
22332  Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
22333  // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
22334  if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
22335  matchAsm(AsmPieces[1], "bswap", "%edx") &&
22336  matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
22337  return IntrinsicLowering::LowerToByteSwap(CI);
22338  }
22339  }
22340  break;
22341  }
22342  return false;
22343 }
llvm::CallInst::getCalledValue
const Value * getCalledValue() const
Definition: Instructions.h:1461
llvm::InlineAsm::getAsmString
const std::string & getAsmString() const
Definition: InlineAsm.h:86
llvm::InlineAsm::getConstraintString
const std::string & getConstraintString() const
Definition: InlineAsm.h:87
llvm::IntegerType::getBitWidth
unsigned getBitWidth() const
Get the number of bits in this IntegerType.
Definition: DerivedTypes.h:61
testing::internal::string
::std::string string
Definition: gtest-port.h:766
llvm::array_pod_sort
void array_pod_sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:335
llvm::IntegerType
Integer representation type.
Definition: DerivedTypes.h:37
llvm::SplitString
void SplitString(StringRef Source, SmallVectorImpl< StringRef > &OutFragments, StringRef Delimiters=" \t\n\v\f\r")
Definition: StringExtras.cpp:51
llvm::Value::getType
Type * getType() const
Definition: Value.h:215
llvm::Type::isIntegerTy
bool isIntegerTy() const
Definition: Type.h:193
llvm::dyn_cast
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
llvm::IntrinsicLowering::LowerToByteSwap
static bool LowerToByteSwap(CallInst *CI)
Definition: IntrinsicLowering.cpp:551
llvm::InlineAsm::ConstraintInfoVector
std::vector< ConstraintInfo > ConstraintInfoVector
Definition: InlineAsm.h:118
clobbersFlagRegisters
static bool clobbersFlagRegisters(const SmallVector< StringRef, 4 > &AsmPieces)
Definition: X86ISelLowering.cpp:22253
llvm::InlineAsm::ParseConstraints
static ConstraintInfoVector ParseConstraints(StringRef ConstraintString)
Definition: InlineAsm.cpp:203
bool TargetLowering::expandMUL ( SDNode *  N,
SDValue &  Lo,
SDValue &  Hi,
EVT  HiLoVT,
SelectionDAG &  DAG,
SDValue  LL = SDValue(),
SDValue  LH = SDValue(),
SDValue  RL = SDValue(),
SDValue  RH = SDValue() 
) const
inherited

Expand a MUL into two nodes. One that computes the high bits of the result and one that computes the low bits.

Parameters
HiLoVTThe value type to use for the Lo and Hi nodes.
LLLow bits of the LHS of the MUL. You can use this parameter if you want to control how low bits are extracted from the LHS.
LHHigh bits of the LHS of the MUL. See LL for meaning.
RLLow bits of the RHS of the MUL. See LL for meaning
RHHigh bits of the RHS of the MUL. See LL for meaning.
Returns
true if the node has been expanded. false if it has not

Definition at line 2786 of file TargetLowering.cpp.

2788  {
2789  EVT VT = N->getValueType(0);
2790  SDLoc dl(N);
2791 
2792  bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2793  bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2794  bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2795  bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2796  if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2797  unsigned OuterBitSize = VT.getSizeInBits();
2798  unsigned InnerBitSize = HiLoVT.getSizeInBits();
2799  unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2800  unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2801 
2802  // LL, LH, RL, and RH must be either all NULL or all set to a value.
2803  assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2804  (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2805 
2806  if (!LL.getNode() && !RL.getNode() &&
2807  isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2808  LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2809  RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2810  }
2811 
2812  if (!LL.getNode())
2813  return false;
2814 
2815  APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2816  if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2817  DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2818  // The inputs are both zero-extended.
2819  if (HasUMUL_LOHI) {
2820  // We can emit a umul_lohi.
2821  Lo = DAG.getNode(ISD::UMUL_LOHI, dl,
2822  DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2823  Hi = SDValue(Lo.getNode(), 1);
2824  return true;
2825  }
2826  if (HasMULHU) {
2827  // We can emit a mulhu+mul.
2828  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2829  Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2830  return true;
2831  }
2832  }
2833  if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2834  // The input values are both sign-extended.
2835  if (HasSMUL_LOHI) {
2836  // We can emit a smul_lohi.
2837  Lo = DAG.getNode(ISD::SMUL_LOHI, dl,
2838  DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2839  Hi = SDValue(Lo.getNode(), 1);
2840  return true;
2841  }
2842  if (HasMULHS) {
2843  // We can emit a mulhs+mul.
2844  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2845  Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2846  return true;
2847  }
2848  }
2849 
2850  if (!LH.getNode() && !RH.getNode() &&
2851  isOperationLegalOrCustom(ISD::SRL, VT) &&
2852  isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2853  unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2854  SDValue Shift = DAG.getConstant(ShiftAmt, getShiftAmountTy(VT));
2855  LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2856  LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2857  RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2858  RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2859  }
2860 
2861  if (!LH.getNode())
2862  return false;
2863 
2864  if (HasUMUL_LOHI) {
2865  // Lo,Hi = umul LHS, RHS.
2866  SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2867  DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2868  Lo = UMulLOHI;
2869  Hi = UMulLOHI.getValue(1);
2870  RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2871  LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2872  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2873  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2874  return true;
2875  }
2876  if (HasMULHU) {
2877  Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2878  Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2879  RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2880  LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2881  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2882  Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2883  return true;
2884  }
2885  }
2886  return false;
2887 }
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:592
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy) const
Definition: TargetLoweringBase.cpp:860
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Definition: SelectionDAGNodes.h:648
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::APInt::getHighBitsSet
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::isOperationLegalOrCustom
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Definition: TargetLowering.h:489
llvm::SelectionDAG::MaskedValueIsZero
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Definition: SelectionDAG.cpp:1934
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::SelectionDAG::ComputeNumSignBits
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Definition: SelectionDAG.cpp:2380
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
SDValue X86TargetLowering::ExtractBitFromMaskVector ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Extract one bit from mask vector, like v16i1 or v8i1. AVX-512 feature.

Definition at line 9773 of file X86ISelLowering.cpp.

9773  {
9774  SDValue Vec = Op.getOperand(0);
9775  SDLoc dl(Vec);
9776  MVT VecVT = Vec.getSimpleValueType();
9777  SDValue Idx = Op.getOperand(1);
9778  MVT EltVT = Op.getSimpleValueType();
9779 
9780  assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
9781 
9782  // variable index can't be handled in mask registers,
9783  // extend vector to VR512
9784  if (!isa<ConstantSDNode>(Idx)) {
9785  MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9786  SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
9787  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
9788  ExtVT.getVectorElementType(), Ext, Idx);
9789  return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
9790  }
9791 
9792  unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9793  const TargetRegisterClass* rc = getRegClassFor(VecVT);
9794  unsigned MaxSift = rc->getSize()*8 - 1;
9795  Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
9796  DAG.getConstant(MaxSift - IdxVal, MVT::i8));
9797  Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
9798  DAG.getConstant(MaxSift, MVT::i8));
9799  return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
9800  DAG.getIntPtrConstant(0));
9801 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
assert
assert(Globals.size() > 1)
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Definition: TargetLowering.h:314
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:264
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
std::pair< const TargetRegisterClass *, uint8_t > X86TargetLowering::findRepresentativeClass ( MVT  VT) const
overrideprotectedvirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1806 of file X86ISelLowering.cpp.

1806  {
1807  const TargetRegisterClass *RRC = nullptr;
1808  uint8_t Cost = 1;
1809  switch (VT.SimpleTy) {
1810  default:
1811  return TargetLowering::findRepresentativeClass(VT);
1812  case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1813  RRC = Subtarget->is64Bit() ?
1814  (const TargetRegisterClass*)&X86::GR64RegClass :
1815  (const TargetRegisterClass*)&X86::GR32RegClass;
1816  break;
1817  case MVT::x86mmx:
1818  RRC = &X86::VR64RegClass;
1819  break;
1820  case MVT::f32: case MVT::f64:
1821  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1822  case MVT::v4f32: case MVT::v2f64:
1823  case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1824  case MVT::v4f64:
1825  RRC = &X86::VR128RegClass;
1826  break;
1827  }
1828  return std::make_pair(RRC, Cost);
1829 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::TargetLoweringBase::findRepresentativeClass
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(MVT VT) const
Definition: TargetLoweringBase.cpp:998
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:156
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::MSP430ISD::RRC
Y = RRC X, rotate right via carry.
Definition: MSP430ISelLowering.h:37
std::pair< SDValue, SDValue > X86TargetLowering::FP_TO_INTHelper ( SDValue  Op,
SelectionDAG &  DAG,
bool  isSigned,
bool  isReplace 
) const
private

Definition at line 10988 of file X86ISelLowering.cpp.

10989  {
10990  SDLoc DL(Op);
10991 
10992  EVT DstTy = Op.getValueType();
10993 
10994  if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
10995  assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
10996  DstTy = MVT::i64;
10997  }
10998 
10999  assert(DstTy.getSimpleVT() <= MVT::i64 &&
11000  DstTy.getSimpleVT() >= MVT::i16 &&
11001  "Unknown FP_TO_INT to lower!");
11002 
11003  // These are really Legal.
11004  if (DstTy == MVT::i32 &&
11005  isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11006  return std::make_pair(SDValue(), SDValue());
11007  if (Subtarget->is64Bit() &&
11008  DstTy == MVT::i64 &&
11009  isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11010  return std::make_pair(SDValue(), SDValue());
11011 
11012  // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11013  // stack slot, or into the FTOL runtime function.
11014  MachineFunction &MF = DAG.getMachineFunction();
11015  unsigned MemSize = DstTy.getSizeInBits()/8;
11016  int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11017  SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11018 
11019  unsigned Opc;
11020  if (!IsSigned && isIntegerTypeFTOL(DstTy))
11021  Opc = X86ISD::WIN_FTOL;
11022  else
11023  switch (DstTy.getSimpleVT().SimpleTy) {
11024  default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11025  case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11026  case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11027  case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11028  }
11029 
11030  SDValue Chain = DAG.getEntryNode();
11031  SDValue Value = Op.getOperand(0);
11032  EVT TheVT = Op.getOperand(0).getValueType();
11033  // FIXME This causes a redundant load/store if the SSE-class value is already
11034  // in memory, such as if it is on the callstack.
11035  if (isScalarFPTypeInSSEReg(TheVT)) {
11036  assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11037  Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11038  MachinePointerInfo::getFixedStack(SSFI),
11039  false, false, 0);
11040  SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11041  SDValue Ops[] = {
11042  Chain, StackSlot, DAG.getValueType(TheVT)
11043  };
11044 
11045  MachineMemOperand *MMO =
11046  MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11047  MachineMemOperand::MOLoad, MemSize, MemSize);
11048  Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11049  Chain = Value.getValue(1);
11050  SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11051  StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11052  }
11053 
11054  MachineMemOperand *MMO =
11055  MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11056  MachineMemOperand::MOStore, MemSize, MemSize);
11057 
11058  if (Opc != X86ISD::WIN_FTOL) {
11059  // Build the FP_TO_INT*_IN_MEM
11060  SDValue Ops[] = { Chain, Value, StackSlot };
11061  SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11062  Ops, DstTy, MMO);
11063  return std::make_pair(FIST, StackSlot);
11064  } else {
11065  SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11066  DAG.getVTList(MVT::Other, MVT::Glue),
11067  Chain, Value);
11068  SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11069  MVT::i32, ftol.getValue(1));
11070  SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11071  MVT::i32, eax.getValue(2));
11072  SDValue Ops[] = { eax, edx };
11073  SDValue pair = IsReplace
11074  ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11075  : DAG.getMergeValues(Ops, DL);
11076  return std::make_pair(pair, SDValue());
11077  }
11078 }
llvm::MachineMemOperand::MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:101
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::MachineMemOperand::MOStore
The memory access writes data.
Definition: MachineMemOperand.h:103
llvm::SelectionDAG::getMergeValues
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
getMergeValues - Create a MERGE_VALUES node from the given operands.
Definition: SelectionDAG.cpp:4574
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
Definition: MachineInstr.cpp:414
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:156
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
Value
static int Value(bit_value_t V)
Definition: FixedLenDecoderEmitter.cpp:140
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::X86TargetLowering::isIntegerTypeFTOL
bool isIntegerTypeFTOL(EVT VT) const
Definition: X86ISelLowering.h:763
assert
assert(Globals.size() > 1)
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
Definition: SelectionDAG.cpp:4815
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: MachineFunction.cpp:230
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Definition: MachineFunction.cpp:513
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getMemIntrinsicNode
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true)
Definition: SelectionDAG.cpp:4586
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1297
llvm::Value
LLVM Value Representation.
Definition: Value.h:69
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1419
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
llvm::X86TargetLowering::isScalarFPTypeInSSEReg
bool isScalarFPTypeInSSEReg(EVT VT) const
Definition: X86ISelLowering.h:752
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Definition: ValueTypes.h:204
virtual bool llvm::TargetLowering::functionArgumentNeedsConsecutiveRegisters ( Type *  Ty,
CallingConv::ID  CallConv,
bool  isVarArg 
) const
inlinevirtualinherited

For some targets, an LLVM struct type must be broken down into multiple simple types, but the calling convention specifies that the entire struct must be passed in a block of consecutive registers.

Reimplemented in llvm::PPCTargetLowering, and llvm::ARMTargetLowering.

Definition at line 2337 of file TargetLowering.h.

2338  {
2339  return false;
2340  }
virtual bool llvm::TargetLoweringBase::GetAddrModeArguments ( IntrinsicInst *  ,
SmallVectorImpl< Value * > &  ,
Type *&   
) const
inlinevirtualinherited

CodeGenPrepare sinks address calculations into the same BB as Load/Store instructions reading the address. This allows as much computation as possible to be done in the address mode for that operand. This hook lets targets also pass back when this should be done on intrinsics which load/store.

Definition at line 1236 of file TargetLowering.h.

1238  {
1239  return false;
1240  }
unsigned X86TargetLowering::GetAlignedArgumentStackSize ( unsigned  StackSize,
SelectionDAG &  DAG 
) const
private

GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned for a 16 byte align requirement.

Definition at line 3078 of file X86ISelLowering.cpp.

3079  {
3080  MachineFunction &MF = DAG.getMachineFunction();
3081  const TargetMachine &TM = MF.getTarget();
3082  const X86RegisterInfo *RegInfo =
3083  static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
3084  const TargetFrameLowering &TFI = *TM.getFrameLowering();
3085  unsigned StackAlignment = TFI.getStackAlignment();
3086  uint64_t AlignMask = StackAlignment - 1;
3087  int64_t Offset = StackSize;
3088  unsigned SlotSize = RegInfo->getSlotSize();
3089  if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3090  // Number smaller than 12 so just add the difference.
3091  Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3092  } else {
3093  // Mask out lower bits, add stackalignment once plus the 12 bytes.
3094  Offset = ((~AlignMask) & Offset) + StackAlignment +
3095  (StackAlignment-SlotSize);
3096  }
3097  return Offset;
3098 }
llvm::TargetFrameLowering::getStackAlignment
unsigned getStackAlignment() const
Definition: TargetFrameLowering.h:70
llvm::TargetLoweringBase::TM
const TargetMachine & TM
True if this is a little endian target.
Definition: TargetLowering.h:1452
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::TargetMachine::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: Target/TargetMachine.h:119
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
llvm::X86RegisterInfo::getSlotSize
unsigned getSlotSize() const
Definition: X86RegisterInfo.h:128
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
BooleanContent llvm::TargetLoweringBase::getBooleanContents ( bool  isVec,
bool  isFloat 
) const
inlineinherited

For targets without i1 registers, this gives the nature of the high-bits of boolean values held in types wider than i1.

"Boolean values" are special true/false values produced by nodes like SETCC and consumed (as the condition) by nodes like SELECT and BRCOND. Not to be confused with general values promoted from i1. Some cpus distinguish between vectors of boolean and scalars; the isVec parameter selects between the two kinds. For example on X86 a scalar boolean should be zero extended from i1, while the elements of a vector of booleans should be sign extended from i1.

Some cpus also treat floating point types the same way as they treat vectors instead of the way they treat scalars.

Definition at line 290 of file TargetLowering.h.

290  {
291  if (isVec)
292  return BooleanVectorContents;
293  return isFloat ? BooleanFloatContents : BooleanContents;
294  }
llvm::TargetLoweringBase::BooleanVectorContents
BooleanContent BooleanVectorContents
Definition: TargetLowering.h:1524
llvm::TargetLoweringBase::BooleanFloatContents
BooleanContent BooleanFloatContents
Definition: TargetLowering.h:1520
llvm::TargetLoweringBase::BooleanContents
BooleanContent BooleanContents
Definition: TargetLowering.h:1516
BooleanContent llvm::TargetLoweringBase::getBooleanContents ( EVT  Type) const
inlineinherited

Definition at line 296 of file TargetLowering.h.

296  {
297  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
298  }
llvm::TargetLoweringBase::getBooleanContents
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
Definition: TargetLowering.h:290
Type
RelocType Type
Definition: COFFYAML.cpp:285
const DenseMap<unsigned int, unsigned int>& llvm::TargetLoweringBase::getBypassSlowDivWidths ( ) const
inlineinherited

Returns map of slow types for division or remainder with corresponding fast types

Definition at line 222 of file TargetLowering.h.

222  {
223  return BypassSlowDivWidths;
224  }
llvm::TargetLoweringBase::BypassSlowDivWidths
DenseMap< unsigned int, unsigned int > BypassSlowDivWidths
Definition: TargetLowering.h:1486
unsigned X86TargetLowering::getByValTypeAlignment ( Type *  Ty) const
overridevirtual

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. For X86, aggregates that contains are placed at 16-byte boundaries while the rest are at 4-byte boundaries.

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. For X86, aggregates that contain SSE vectors are placed at 16-byte boundaries while the rest are at 4-byte boundaries.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1673 of file X86ISelLowering.cpp.

1673  {
1674  if (Subtarget->is64Bit()) {
1675  // Max of 8 and alignment of type.
1676  unsigned TyAlign = TD->getABITypeAlignment(Ty);
1677  if (TyAlign > 8)
1678  return TyAlign;
1679  return 8;
1680  }
1681 
1682  unsigned Align = 4;
1683  if (Subtarget->hasSSE1())
1684  getMaxByValAlign(Ty, Align);
1685  return Align;
1686 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::DataLayout::getABITypeAlignment
unsigned getABITypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:683
Align
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:311
getMaxByValAlign
static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign)
Definition: X86ISelLowering.cpp:1646
llvm::X86TargetLowering::TD
const DataLayout * TD
Definition: X86ISelLowering.h:810
const char* llvm::X86TargetLowering::getClearCacheBuiltinName ( ) const
inlineoverridevirtual

Intel processors have a unified instruction and data cache.

Reimplemented from llvm::TargetLowering.

Definition at line 773 of file X86ISelLowering.h.

773  {
774  return nullptr; // nothing to do, move along.
775  }
ISD::CondCode llvm::TargetLoweringBase::getCmpLibcallCC ( RTLIB::Libcall  Call) const
inlineinherited

Get the CondCode that's to be used to test the result of the comparison libcall against zero.

Definition at line 1437 of file TargetLowering.h.

1437  {
1438  return CmpLibcallCCs[Call];
1439  }
llvm::TargetLoweringBase::CmpLibcallCCs
ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]
Definition: TargetLowering.h:1781
MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType ( ) const
virtualinherited

Return the ValueType for comparison libcalls. Comparions libcalls include floating point comparion calls, and Ordered/Unordered check calls on floating point numbers.

Definition at line 1214 of file TargetLoweringBase.cpp.

1214  {
1215  return MVT::i32; // return the default value
1216 }
LegalizeAction llvm::TargetLoweringBase::getCondCodeAction ( ISD::CondCode  CC,
MVT  VT 
) const
inlineinherited

Return how the condition code should be treated: either it is legal, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 589 of file TargetLowering.h.

589  {
590  assert((unsigned)CC < array_lengthof(CondCodeActions) &&
591  ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
592  "Table isn't big enough!");
593  // See setCondCodeAction for how this is encoded.
594  uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
595  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
596  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
597  assert(Action != Promote && "Can't promote condition code!");
598  return Action;
599  }
Action
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
Value
static int Value(bit_value_t V)
Definition: FixedLenDecoderEmitter.cpp:140
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::CondCodeActions
uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE+15)/16]
Definition: TargetLowering.h:1623
X86TargetLowering::ConstraintType X86TargetLowering::getConstraintType ( const std::string &  Constraint) const
overridevirtual

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

Reimplemented from llvm::TargetLowering.

Definition at line 22348 of file X86ISelLowering.cpp.

22348  {
22349  if (Constraint.size() == 1) {
22350  switch (Constraint[0]) {
22351  case 'R':
22352  case 'q':
22353  case 'Q':
22354  case 'f':
22355  case 't':
22356  case 'u':
22357  case 'y':
22358  case 'x':
22359  case 'Y':
22360  case 'l':
22361  return C_RegisterClass;
22362  case 'a':
22363  case 'b':
22364  case 'c':
22365  case 'd':
22366  case 'S':
22367  case 'D':
22368  case 'A':
22369  return C_Register;
22370  case 'I':
22371  case 'J':
22372  case 'K':
22373  case 'L':
22374  case 'M':
22375  case 'N':
22376  case 'G':
22377  case 'C':
22378  case 'e':
22379  case 'Z':
22380  return C_Other;
22381  default:
22382  break;
22383  }
22384  }
22385  return TargetLowering::getConstraintType(Constraint);
22386 }
llvm::TargetLowering::getConstraintType
virtual ConstraintType getConstraintType(const std::string &Constraint) const
Given a constraint, return the type of constraint it is for this target.
Definition: TargetLowering.cpp:2048
const DataLayout* llvm::TargetLoweringBase::getDataLayout ( ) const
inlineinherited

Definition at line 150 of file TargetLowering.h.

150 { return DL; }
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
unsigned llvm::TargetLoweringBase::getExceptionPointerRegister ( ) const
inlineinherited

If a physical register, this returns the register that receives the exception address on entry to a landing pad.

Definition at line 845 of file TargetLowering.h.

845  {
846  return ExceptionPointerRegister;
847  }
unsigned llvm::TargetLoweringBase::getExceptionSelectorRegister ( ) const
inlineinherited

If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.

Definition at line 851 of file TargetLowering.h.

851  {
852  return ExceptionSelectorRegister;
853  }
static ISD::NodeType llvm::TargetLoweringBase::getExtendForContent ( BooleanContent  Content)
inlinestaticinherited

Definition at line 124 of file TargetLowering.h.

124  {
125  switch (Content) {
126  case UndefinedBooleanContent:
127  // Extend by adding rubbish bits.
128  return ISD::ANY_EXTEND;
129  case ZeroOrOneBooleanContent:
130  // Extend by adding zero bits.
131  return ISD::ZERO_EXTEND;
132  case ZeroOrNegativeOneBooleanContent:
133  // Extend by copying the sign bit.
134  return ISD::SIGN_EXTEND;
135  }
136  llvm_unreachable("Invalid content kind");
137  }
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
LegalizeAction llvm::TargetLoweringBase::getIndexedLoadAction ( unsigned  IdxMode,
MVT  VT 
) const
inlineinherited

Return how the indexed load should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 553 of file TargetLowering.h.

553  {
554  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
555  "Table isn't big enough!");
556  unsigned Ty = (unsigned)VT.SimpleTy;
557  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
558  }
llvm::TargetLoweringBase::IndexedModeActions
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
Definition: TargetLowering.h:1615
assert
assert(Globals.size() > 1)
LegalizeAction llvm::TargetLoweringBase::getIndexedStoreAction ( unsigned  IdxMode,
MVT  VT 
) const
inlineinherited

Return how the indexed store should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 571 of file TargetLowering.h.

571  {
572  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
573  "Table isn't big enough!");
574  unsigned Ty = (unsigned)VT.SimpleTy;
575  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
576  }
llvm::TargetLoweringBase::IndexedModeActions
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
Definition: TargetLowering.h:1615
assert
assert(Globals.size() > 1)
bool llvm::TargetLoweringBase::getInsertFencesForAtomic ( ) const
inlineinherited

Return whether the DAG builder should automatically insert fences and reduce ordering for atomics.

Definition at line 889 of file TargetLowering.h.

889  {
890  return InsertFencesForAtomic;
891  }
unsigned llvm::TargetLoweringBase::getJumpBufAlignment ( ) const
inlineinherited

Returns the target's jmp_buf alignment in bytes (if never set, the default is 0)

Definition at line 863 of file TargetLowering.h.

863  {
864  return JumpBufAlignment;
865  }
llvm::TargetLoweringBase::JumpBufAlignment
unsigned JumpBufAlignment
The alignment, in bytes, of the target's jmp_buf buffers.
Definition: TargetLowering.h:1534
unsigned llvm::TargetLoweringBase::getJumpBufSize ( ) const
inlineinherited

Returns the target's jmp_buf size in bytes (if never set, the default is 200)

Definition at line 857 of file TargetLowering.h.

857  {
858  return JumpBufSize;
859  }
llvm::TargetLoweringBase::JumpBufSize
unsigned JumpBufSize
The size, in bytes, of the target's jmp_buf buffers.
Definition: TargetLowering.h:1531
unsigned X86TargetLowering::getJumpTableEncoding ( ) const
overridevirtual

getJumpTableEncoding - Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.

Reimplemented from llvm::TargetLowering.

Definition at line 1756 of file X86ISelLowering.cpp.

1756  {
1757  // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1758  // symbol.
1759  if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1760  Subtarget->isPICStyleGOT())
1761  return MachineJumpTableInfo::EK_Custom32;
1762 
1763  // Otherwise, use the normal jump table encoding heuristics.
1764  return TargetLowering::getJumpTableEncoding();
1765 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:149
llvm::X86Subtarget::isPICStyleGOT
bool isPICStyleGOT() const
Definition: X86Subtarget.h:416
llvm::TargetLowering::getJumpTableEncoding
virtual unsigned getJumpTableEncoding() const
Definition: TargetLowering.cpp:222
CallingConv::ID llvm::TargetLoweringBase::getLibcallCallingConv ( RTLIB::Libcall  Call) const
inlineinherited

Get the CallingConv that should be used for the specified libcall.

Definition at line 1447 of file TargetLowering.h.

1447  {
1448  return LibcallCallingConvs[Call];
1449  }
llvm::TargetLoweringBase::LibcallCallingConvs
CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]
Stores the CallingConv that should be used for each libcall.
Definition: TargetLowering.h:1784
const char* llvm::TargetLoweringBase::getLibcallName ( RTLIB::Libcall  Call) const
inlineinherited

Get the libcall routine name for the specified libcall.

Definition at line 1425 of file TargetLowering.h.

1425  {
1426  return LibcallRoutineNames[Call];
1427  }
llvm::TargetLoweringBase::LibcallRoutineNames
const char * LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]
Stores the name each libcall.
Definition: TargetLowering.h:1777
LegalizeAction llvm::TargetLoweringBase::getLoadExtAction ( unsigned  ExtType,
MVT  VT 
) const
inlineinherited

Return how this load with extension should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 520 of file TargetLowering.h.

520  {
521  assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
522  "Table isn't big enough!");
523  return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
524  }
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::LoadExtActions
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]
Definition: TargetLowering.h:1603
virtual unsigned llvm::TargetLoweringBase::getMaximalGlobalOffset ( ) const
inlinevirtualinherited

Returns the maximal possible offset which can be used for loads / stores from the global.

Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 903 of file TargetLowering.h.

903  {
904  return 0;
905  }
unsigned llvm::TargetLoweringBase::getMaxStoresPerMemcpy ( bool  OptSize) const
inlineinherited

Get maximum # of store operations permitted for llvm.memcpy.

This function returns the maximum number of store operations permitted to replace a call to llvm.memcpy. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 758 of file TargetLowering.h.

758  {
759  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
760  }
llvm::TargetLoweringBase::MaxStoresPerMemcpy
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
Definition: TargetLowering.h:1814
unsigned llvm::TargetLoweringBase::getMaxStoresPerMemmove ( bool  OptSize) const
inlineinherited

Get maximum # of store operations permitted for llvm.memmove.

This function returns the maximum number of store operations permitted to replace a call to llvm.memmove. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 768 of file TargetLowering.h.

768  {
769  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
770  }
llvm::TargetLoweringBase::MaxStoresPerMemmove
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Definition: TargetLowering.h:1830
unsigned llvm::TargetLoweringBase::getMaxStoresPerMemset ( bool  OptSize) const
inlineinherited

Get maximum # of store operations permitted for llvm.memset.

This function returns the maximum number of store operations permitted to replace a call to llvm.memset. The value is set by the target at the performance threshold for such a replacement. If OptSize is true, return the limit for functions that have OptSize attribute.

Definition at line 748 of file TargetLowering.h.

748  {
749  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
750  }
llvm::TargetLoweringBase::MaxStoresPerMemset
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition: TargetLowering.h:1797
unsigned llvm::TargetLoweringBase::getMinFunctionAlignment ( ) const
inlineinherited

Return the minimum function alignment.

Definition at line 873 of file TargetLowering.h.

873  {
874  return MinFunctionAlignment;
875  }
int llvm::TargetLoweringBase::getMinimumJumpTableEntries ( ) const
inlineinherited

Return integer threshold on number of blocks to use jump tables rather than if sequence.

Definition at line 833 of file TargetLowering.h.

833  {
834  return MinimumJumpTableEntries;
835  }
llvm::TargetLoweringBase::MinimumJumpTableEntries
int MinimumJumpTableEntries
Number of blocks threshold to use jump tables.
Definition: TargetLowering.h:1512
unsigned llvm::TargetLoweringBase::getMinStackArgumentAlignment ( ) const
inlineinherited

Return the minimum stack alignment of an argument.

Definition at line 868 of file TargetLowering.h.

868  {
869  return MinStackArgumentAlignment;
870  }
llvm::TargetLoweringBase::MinStackArgumentAlignment
unsigned MinStackArgumentAlignment
The minimum alignment that any argument on the stack needs to have.
Definition: TargetLowering.h:1537
TargetLowering::ConstraintWeight TargetLowering::getMultipleConstraintMatchWeight ( AsmOperandInfo &  info,
int  maIndex 
) const
virtualinherited

Examine constraint type and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.

Definition at line 2442 of file TargetLowering.cpp.

2443  {
2444  InlineAsm::ConstraintCodeVector *rCodes;
2445  if (maIndex >= (int)info.multipleAlternatives.size())
2446  rCodes = &info.Codes;
2447  else
2448  rCodes = &info.multipleAlternatives[maIndex].Codes;
2449  ConstraintWeight BestWeight = CW_Invalid;
2450 
2451  // Loop over the options, keeping track of the most general one.
2452  for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2453  ConstraintWeight weight =
2454  getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2455  if (weight > BestWeight)
2456  BestWeight = weight;
2457  }
2458 
2459  return BestWeight;
2460 }
info
lazy value info
Definition: LazyValueInfo.cpp:42
for
for(unsigned i=0, e=MI->getNumOperands();i!=e;++i)
Definition: DeadMachineInstructionElim.cpp:67
llvm::InlineAsm::ConstraintCodeVector
std::vector< std::string > ConstraintCodeVector
Definition: InlineAsm.h:102
llvm::c_str
SmallVectorImpl< T >::const_pointer c_str(SmallVectorImpl< T > &str)
Definition: WindowsSupport.h:158
llvm::TargetLowering::getSingleConstraintMatchWeight
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Definition: TargetLowering.cpp:2466
unsigned llvm::TargetLoweringBase::getNumRegisters ( LLVMContext &  Context,
EVT  VT 
) const
inlineinherited

Return the number of registers that this ValueType will eventually require.

This is one for any types promoted to live in larger registers, but may be more than one for types (like i64) that are split into pieces. For types like i140, which are first promoted then expanded, it is the number of registers needed to hold all the bits of the original type. For an i140 on a 32 bit machine this means 5 registers.

Definition at line 703 of file TargetLowering.h.

703  {
704  if (VT.isSimple()) {
705  assert((unsigned)VT.getSimpleVT().SimpleTy <
706  array_lengthof(NumRegistersForVT));
707  return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
708  }
709  if (VT.isVector()) {
710  EVT VT1;
711  MVT VT2;
712  unsigned NumIntermediates;
713  return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
714  }
715  if (VT.isInteger()) {
716  unsigned BitWidth = VT.getSizeInBits();
717  unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
718  return (BitWidth + RegWidth - 1) / RegWidth;
719  }
720  llvm_unreachable("Unsupported extended type!");
721  }
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::NumRegistersForVT
unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
Definition: TargetLowering.h:1570
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:669
llvm::TargetLoweringBase::getVectorTypeBreakdown
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Definition: TargetLoweringBase.cpp:1227
const TargetLoweringObjectFile& llvm::TargetLoweringBase::getObjFileLowering ( ) const
inlineinherited

Definition at line 151 of file TargetLowering.h.

151 { return TLOF; }
llvm::TargetLoweringBase::TLOF
const TargetLoweringObjectFile & TLOF
True if this is a little endian target.
Definition: TargetLowering.h:1454
LegalizeAction llvm::TargetLoweringBase::getOperationAction ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return how this operation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 477 of file TargetLowering.h.

477  {
478  if (VT.isExtended()) return Expand;
479  // If a target-specific SDNode requires legalization, require the target
480  // to provide custom legalization for it.
481  if (Op > array_lengthof(OpActions[0])) return Custom;
482  unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
483  return (LegalizeAction)OpActions[I][Op];
484  }
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
I
#define I(x, y, z)
Definition: MD5.cpp:54
llvm::TargetLoweringBase::OpActions
uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]
Definition: TargetLowering.h:1598
EVT X86TargetLowering::getOptimalMemOpType ( uint64_t  Size,
unsigned  DstAlign,
unsigned  SrcAlign,
bool  IsMemset,
bool  ZeroMemset,
bool  MemcpyStrSrc,
MachineFunction &  MF 
) const
overridevirtual

getOptimalMemOpType - Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. If DstAlign is zero that means it's safe to destination alignment can satisfy any constraint. Similarly if SrcAlign is zero it means there isn't a need to check it against alignment requirement, probably because the source does not need to be loaded. If 'IsMemset' is true, that means it's expanding a memset. If 'ZeroMemset' is true, that means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it does not need to be loaded. It returns EVT::Other if the type should be determined using generic target-independent logic.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1700 of file X86ISelLowering.cpp.

1704  {
1705  const Function *F = MF.getFunction();
1706  if ((!IsMemset || ZeroMemset) &&
1707  !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1708  Attribute::NoImplicitFloat)) {
1709  if (Size >= 16 &&
1710  (Subtarget->isUnalignedMemAccessFast() ||
1711  ((DstAlign == 0 || DstAlign >= 16) &&
1712  (SrcAlign == 0 || SrcAlign >= 16)))) {
1713  if (Size >= 32) {
1714  if (Subtarget->hasInt256())
1715  return MVT::v8i32;
1716  if (Subtarget->hasFp256())
1717  return MVT::v8f32;
1718  }
1719  if (Subtarget->hasSSE2())
1720  return MVT::v4i32;
1721  if (Subtarget->hasSSE1())
1722  return MVT::v4f32;
1723  } else if (!MemcpyStrSrc && Size >= 8 &&
1724  !Subtarget->is64Bit() &&
1725  Subtarget->hasSSE2()) {
1726  // Do not use f64 to lower memcpy if source is string constant. It's
1727  // better to use i32 to avoid the loads.
1728  return MVT::f64;
1729  }
1730  }
1731  if (Subtarget->is64Bit() && Size >= 8)
1732  return MVT::i64;
1733  return MVT::i32;
1734 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
F
F(f)
llvm::MachineFunction::getFunction
const Function * getFunction() const
Definition: MachineFunction.h:151
llvm::AttributeSet::hasAttribute
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::X86Subtarget::hasSSE2
bool hasSSE2() const
Definition: X86Subtarget.h:312
llvm::X86Subtarget::hasFp256
bool hasFp256() const
Definition: X86Subtarget.h:320
llvm::Function::getAttributes
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
llvm::X86Subtarget::hasInt256
bool hasInt256() const
Definition: X86Subtarget.h:321
llvm::X86Subtarget::isUnalignedMemAccessFast
bool isUnalignedMemAccessFast() const
Definition: X86Subtarget.h:348
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:311
llvm::Attribute::NoImplicitFloat
Disable implicit floating point insts.
Definition: Attributes.h:86
SDValue X86TargetLowering::getPICJumpTableRelocBase ( SDValue  Table,
SelectionDAG &  DAG 
) const
overridevirtual

getPICJumpTableRelocaBase - Returns relocation base for the given PIC jumptable.

Reimplemented from llvm::TargetLowering.

Definition at line 1781 of file X86ISelLowering.cpp.

1782  {
1783  if (!Subtarget->is64Bit())
1784  // This doesn't have SDLoc associated with it, but is not really the
1785  // same as a Register.
1786  return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1787  return Table;
1788 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
const MCExpr * X86TargetLowering::getPICJumpTableRelocBaseExpr ( const MachineFunction *  MF,
unsigned  JTI,
MCContext &  Ctx 
) const
overridevirtual

getPICJumpTableRelocBaseExpr - This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.

Reimplemented from llvm::TargetLowering.

Definition at line 1794 of file X86ISelLowering.cpp.

1795  {
1796  // X86-64 uses RIP relative addressing based on the jump table label.
1797  if (Subtarget->isPICStyleRIPRel())
1798  return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1799 
1800  // Otherwise, the reference is relative to the PIC base.
1801  return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1802 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86Subtarget::isPICStyleRIPRel
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:417
llvm::MCSymbolRefExpr::Create
static const MCSymbolRefExpr * Create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:293
llvm::MachineFunction::getPICBaseSymbol
MCSymbol * getPICBaseSymbol() const
Definition: MachineFunction.cpp:476
llvm::TargetLowering::getPICJumpTableRelocBaseExpr
virtual const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
Definition: TargetLowering.cpp:251
unsigned TargetLoweringBase::getPointerSizeInBits ( uint32_t  AS = 0) const
inherited

Definition at line 847 of file TargetLoweringBase.cpp.

847  {
848  return DL->getPointerSizeInBits(AS);
849 }
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Definition: DataLayout.h:313
MVT TargetLoweringBase::getPointerTy ( uint32_t  AS = 0) const
virtualinherited

Return the pointer type for the given address space, defaults to the pointer type from the data layout. FIXME: The default needs to be removed once all the code is updated.

Definition at line 843 of file TargetLoweringBase.cpp.

843  {
844  return MVT::getIntegerVT(getPointerSizeInBits(AS));
845 }
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:486
llvm::TargetLoweringBase::getPointerSizeInBits
unsigned getPointerSizeInBits(uint32_t AS=0) const
Definition: TargetLoweringBase.cpp:847
unsigned TargetLoweringBase::getPointerTypeSizeInBits ( Type *  Ty) const
inherited

Definition at line 851 of file TargetLoweringBase.cpp.

851  {
852  assert(Ty->isPointerTy());
853  return getPointerSizeInBits(Ty->getPointerAddressSpace());
854 }
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: Type.cpp:212
llvm::TargetLoweringBase::getPointerSizeInBits
unsigned getPointerSizeInBits(uint32_t AS=0) const
Definition: TargetLoweringBase.cpp:847
assert
assert(Globals.size() > 1)
llvm::Type::isPointerTy
bool isPointerTy() const
Definition: Type.h:217
virtual bool llvm::TargetLowering::getPostIndexedAddressParts ( SDNode *  ,
SDNode *  ,
SDValue &  ,
SDValue &  ,
ISD::MemIndexedMode &  ,
SelectionDAG &   
) const
inlinevirtualinherited

Returns true by value, base pointer and offset pointer and addressing mode by reference if this node can be combined with a load / store to form a post-indexed load / store.

Reimplemented in llvm::AArch64TargetLowering, llvm::ARMTargetLowering, llvm::MSP430TargetLowering, and llvm::HexagonTargetLowering.

Definition at line 1881 of file TargetLowering.h.

1885  {
1886  return false;
1887  }
TargetLoweringBase::LegalizeTypeAction X86TargetLowering::getPreferredVectorAction ( EVT  VT) const
overridevirtual

Customize the preferred legalization strategy for certain types.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1622 of file X86ISelLowering.cpp.

1622  {
1623  if (ExperimentalVectorWideningLegalization &&
1624  VT.getVectorNumElements() != 1 &&
1625  VT.getVectorElementType().getSimpleVT() != MVT::i1)
1626  return TypeWidenVector;
1627 
1628  return TargetLoweringBase::getPreferredVectorAction(VT);
1629 }
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Definition: ValueTypes.h:217
llvm::TargetLoweringBase::getPreferredVectorAction
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT) const
Return the preferred vector type legalization action.
Definition: TargetLowering.h:190
ExperimentalVectorWideningLegalization
static cl::opt< bool > ExperimentalVectorWideningLegalization("x86-experimental-vector-widening-legalization", cl::init(false), cl::desc("Enable an experimental vector type legalization through widening ""rather than promotion."), cl::Hidden)
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Definition: ValueTypes.h:204
llvm::EVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
unsigned llvm::TargetLoweringBase::getPrefFunctionAlignment ( ) const
inlineinherited

Return the preferred function alignment.

Definition at line 878 of file TargetLowering.h.

878  {
879  return PrefFunctionAlignment;
880  }
unsigned llvm::TargetLoweringBase::getPrefLoopAlignment ( ) const
inlineinherited

Return the preferred loop alignment.

Definition at line 883 of file TargetLowering.h.

883  {
884  return PrefLoopAlignment;
885  }
llvm::TargetLoweringBase::PrefLoopAlignment
unsigned PrefLoopAlignment
The preferred loop alignment.
Definition: TargetLowering.h:1548
virtual bool llvm::TargetLowering::getPreIndexedAddressParts ( SDNode *  ,
SDValue &  ,
SDValue &  ,
ISD::MemIndexedMode &  ,
SelectionDAG &   
) const
inlinevirtualinherited

Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's address can be legally represented as pre-indexed load / store address.

Reimplemented in llvm::AArch64TargetLowering, llvm::PPCTargetLowering, and llvm::ARMTargetLowering.

Definition at line 1871 of file TargetLowering.h.

1874  {
1875  return false;
1876  }
virtual const TargetRegisterClass* llvm::TargetLoweringBase::getRegClassFor ( MVT  VT) const
inlinevirtualinherited

Return the register class that should be used for the specified value type.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 314 of file TargetLowering.h.

314  {
315  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
316  assert(RC && "This value type is not natively supported!");
317  return RC;
318  }
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::RegClassForVT
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1569
std::pair< unsigned, const TargetRegisterClass * > X86TargetLowering::getRegForInlineAsmConstraint ( const std::string &  Constraint,
MVT  VT 
) const
overridevirtual

getRegForInlineAsmConstraint - Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register. This should only be used for C_Register constraints. On error, this returns a register number of 0.

Reimplemented from llvm::TargetLowering.

Definition at line 22646 of file X86ISelLowering.cpp.

22647  {
22648  // First, see if this is a constraint that directly corresponds to an LLVM
22649  // register class.
22650  if (Constraint.size() == 1) {
22651  // GCC Constraint Letters
22652  switch (Constraint[0]) {
22653  default: break;
22654  // TODO: Slight differences here in allocation order and leaving
22655  // RIP in the class. Do they matter any more here than they do
22656  // in the normal allocation?
22657  case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
22658  if (Subtarget->is64Bit()) {
22659  if (VT == MVT::i32 || VT == MVT::f32)
22660  return std::make_pair(0U, &X86::GR32RegClass);
22661  if (VT == MVT::i16)
22662  return std::make_pair(0U, &X86::GR16RegClass);
22663  if (VT == MVT::i8 || VT == MVT::i1)
22664  return std::make_pair(0U, &X86::GR8RegClass);
22665  if (VT == MVT::i64 || VT == MVT::f64)
22666  return std::make_pair(0U, &X86::GR64RegClass);
22667  break;
22668  }
22669  // 32-bit fallthrough
22670  case 'Q': // Q_REGS
22671  if (VT == MVT::i32 || VT == MVT::f32)
22672  return std::make_pair(0U, &X86::GR32_ABCDRegClass);
22673  if (VT == MVT::i16)
22674  return std::make_pair(0U, &X86::GR16_ABCDRegClass);
22675  if (VT == MVT::i8 || VT == MVT::i1)
22676  return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
22677  if (VT == MVT::i64)
22678  return std::make_pair(0U, &X86::GR64_ABCDRegClass);
22679  break;
22680  case 'r': // GENERAL_REGS
22681  case 'l': // INDEX_REGS
22682  if (VT == MVT::i8 || VT == MVT::i1)
22683  return std::make_pair(0U, &X86::GR8RegClass);
22684  if (VT == MVT::i16)
22685  return std::make_pair(0U, &X86::GR16RegClass);
22686  if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
22687  return std::make_pair(0U, &X86::GR32RegClass);
22688  return std::make_pair(0U, &X86::GR64RegClass);
22689  case 'R': // LEGACY_REGS
22690  if (VT == MVT::i8 || VT == MVT::i1)
22691  return std::make_pair(0U, &X86::GR8_NOREXRegClass);
22692  if (VT == MVT::i16)
22693  return std::make_pair(0U, &X86::GR16_NOREXRegClass);
22694  if (VT == MVT::i32 || !Subtarget->is64Bit())
22695  return std::make_pair(0U, &X86::GR32_NOREXRegClass);
22696  return std::make_pair(0U, &X86::GR64_NOREXRegClass);
22697  case 'f': // FP Stack registers.
22698  // If SSE is enabled for this VT, use f80 to ensure the isel moves the
22699  // value to the correct fpstack register class.
22700  if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
22701  return std::make_pair(0U, &X86::RFP32RegClass);
22702  if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
22703  return std::make_pair(0U, &X86::RFP64RegClass);
22704  return std::make_pair(0U, &X86::RFP80RegClass);
22705  case 'y': // MMX_REGS if MMX allowed.
22706  if (!Subtarget->hasMMX()) break;
22707  return std::make_pair(0U, &X86::VR64RegClass);
22708  case 'Y': // SSE_REGS if SSE2 allowed
22709  if (!Subtarget->hasSSE2()) break;
22710  // FALL THROUGH.
22711  case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
22712  if (!Subtarget->hasSSE1()) break;
22713 
22714  switch (VT.SimpleTy) {
22715  default: break;
22716  // Scalar SSE types.
22717  case MVT::f32:
22718  case MVT::i32:
22719  return std::make_pair(0U, &X86::FR32RegClass);
22720  case MVT::f64:
22721  case MVT::i64:
22722  return std::make_pair(0U, &X86::FR64RegClass);
22723  // Vector types.
22724  case MVT::v16i8:
22725  case MVT::v8i16:
22726  case MVT::v4i32:
22727  case MVT::v2i64:
22728  case MVT::v4f32:
22729  case MVT::v2f64:
22730  return std::make_pair(0U, &X86::VR128RegClass);
22731  // AVX types.
22732  case MVT::v32i8:
22733  case MVT::v16i16:
22734  case MVT::v8i32:
22735  case MVT::v4i64:
22736  case MVT::v8f32:
22737  case MVT::v4f64:
22738  return std::make_pair(0U, &X86::VR256RegClass);
22739  case MVT::v8f64:
22740  case MVT::v16f32:
22741  case MVT::v16i32:
22742  case MVT::v8i64:
22743  return std::make_pair(0U, &X86::VR512RegClass);
22744  }
22745  break;
22746  }
22747  }
22748 
22749  // Use the default implementation in TargetLowering to convert the register
22750  // constraint into a member of a register class.
22751  std::pair<unsigned, const TargetRegisterClass*> Res;
22752  Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
22753 
22754  // Not found as a standard register?
22755  if (!Res.second) {
22756  // Map st(0) -> st(7) -> ST0
22757  if (Constraint.size() == 7 && Constraint[0] == '{' &&
22758  tolower(Constraint[1]) == 's' &&
22759  tolower(Constraint[2]) == 't' &&
22760  Constraint[3] == '(' &&
22761  (Constraint[4] >= '0' && Constraint[4] <= '7') &&
22762  Constraint[5] == ')' &&
22763  Constraint[6] == '}') {
22764 
22765  Res.first = X86::ST0+Constraint[4]-'0';
22766  Res.second = &X86::RFP80RegClass;
22767  return Res;
22768  }
22769 
22770  // GCC allows "st(0)" to be called just plain "st".
22771  if (StringRef("{st}").equals_lower(Constraint)) {
22772  Res.first = X86::ST0;
22773  Res.second = &X86::RFP80RegClass;
22774  return Res;
22775  }
22776 
22777  // flags -> EFLAGS
22778  if (StringRef("{flags}").equals_lower(Constraint)) {
22779  Res.first = X86::EFLAGS;
22780  Res.second = &X86::CCRRegClass;
22781  return Res;
22782  }
22783 
22784  // 'A' means EAX + EDX.
22785  if (Constraint == "A") {
22786  Res.first = X86::EAX;
22787  Res.second = &X86::GR32_ADRegClass;
22788  return Res;
22789  }
22790  return Res;
22791  }
22792 
22793  // Otherwise, check to see if this is a register class of the wrong value
22794  // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
22795  // turn into {ax},{dx}.
22796  if (Res.second->hasType(VT))
22797  return Res; // Correct type already, nothing to do.
22798 
22799  // All of the single-register GCC register classes map their values onto
22800  // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
22801  // really want an 8-bit or 32-bit register, map to the appropriate register
22802  // class and return the appropriate register.
22803  if (Res.second == &X86::GR16RegClass) {
22804  if (VT == MVT::i8 || VT == MVT::i1) {
22805  unsigned DestReg = 0;
22806  switch (Res.first) {
22807  default: break;
22808  case X86::AX: DestReg = X86::AL; break;
22809  case X86::DX: DestReg = X86::DL; break;
22810  case X86::CX: DestReg = X86::CL; break;
22811  case X86::BX: DestReg = X86::BL; break;
22812  }
22813  if (DestReg) {
22814  Res.first = DestReg;
22815  Res.second = &X86::GR8RegClass;
22816  }
22817  } else if (VT == MVT::i32 || VT == MVT::f32) {
22818  unsigned DestReg = 0;
22819  switch (Res.first) {
22820  default: break;
22821  case X86::AX: DestReg = X86::EAX; break;
22822  case X86::DX: DestReg = X86::EDX; break;
22823  case X86::CX: DestReg = X86::ECX; break;
22824  case X86::BX: DestReg = X86::EBX; break;
22825  case X86::SI: DestReg = X86::ESI; break;
22826  case X86::DI: DestReg = X86::EDI; break;
22827  case X86::BP: DestReg = X86::EBP; break;
22828  case X86::SP: DestReg = X86::ESP; break;
22829  }
22830  if (DestReg) {
22831  Res.first = DestReg;
22832  Res.second = &X86::GR32RegClass;
22833  }
22834  } else if (VT == MVT::i64 || VT == MVT::f64) {
22835  unsigned DestReg = 0;
22836  switch (Res.first) {
22837  default: break;
22838  case X86::AX: DestReg = X86::RAX; break;
22839  case X86::DX: DestReg = X86::RDX; break;
22840  case X86::CX: DestReg = X86::RCX; break;
22841  case X86::BX: DestReg = X86::RBX; break;
22842  case X86::SI: DestReg = X86::RSI; break;
22843  case X86::DI: DestReg = X86::RDI; break;
22844  case X86::BP: DestReg = X86::RBP; break;
22845  case X86::SP: DestReg = X86::RSP; break;
22846  }
22847  if (DestReg) {
22848  Res.first = DestReg;
22849  Res.second = &X86::GR64RegClass;
22850  }
22851  }
22852  } else if (Res.second == &X86::FR32RegClass ||
22853  Res.second == &X86::FR64RegClass ||
22854  Res.second == &X86::VR128RegClass ||
22855  Res.second == &X86::VR256RegClass ||
22856  Res.second == &X86::FR32XRegClass ||
22857  Res.second == &X86::FR64XRegClass ||
22858  Res.second == &X86::VR128XRegClass ||
22859  Res.second == &X86::VR256XRegClass ||
22860  Res.second == &X86::VR512RegClass) {
22861  // Handle references to XMM physical registers that got mapped into the
22862  // wrong class. This can happen with constraints like {xmm0} where the
22863  // target independent register mapper will just pick the first match it can
22864  // find, ignoring the required type.
22865 
22866  if (VT == MVT::f32 || VT == MVT::i32)
22867  Res.second = &X86::FR32RegClass;
22868  else if (VT == MVT::f64 || VT == MVT::i64)
22869  Res.second = &X86::FR64RegClass;
22870  else if (X86::VR128RegClass.hasType(VT))
22871  Res.second = &X86::VR128RegClass;
22872  else if (X86::VR256RegClass.hasType(VT))
22873  Res.second = &X86::VR256RegClass;
22874  else if (X86::VR512RegClass.hasType(VT))
22875  Res.second = &X86::VR512RegClass;
22876  }
22877 
22878  return Res;
22879 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:156
llvm::X86Subtarget::hasMMX
bool hasMMX() const
Definition: X86Subtarget.h:310
DL
INITIALIZE_TM_PASS(GlobalMerge,"global-merge","Merge global variables", false, false) bool GlobalMerge const DataLayout * DL
Definition: GlobalMerge.cpp:146
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
Definition: TargetLowering.cpp:2167
llvm::X86Subtarget::hasSSE2
bool hasSSE2() const
Definition: X86Subtarget.h:312
if
* if(!EatIfPresent(lltok::kw_thread_local)) return false
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:311
llvm::StringRef::equals_lower
bool equals_lower(StringRef RHS) const
equals_lower - Check for string equality, ignoring case.
Definition: StringRef.h:141
llvm::X86TargetLowering::isScalarFPTypeInSSEReg
bool isScalarFPTypeInSSEReg(EVT VT) const
Definition: X86ISelLowering.h:752
unsigned X86TargetLowering::getRegisterByName ( const char *  RegName,
EVT  VT 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 14630 of file X86ISelLowering.cpp.

14631  {
14632  unsigned Reg = StringSwitch<unsigned>(RegName)
14633  .Case("esp", X86::ESP)
14634  .Case("rsp", X86::RSP)
14635  .Default(0);
14636  if (Reg)
14637  return Reg;
14638  report_fatal_error("Invalid register name global variable");
14639 }
llvm::StringSwitch::Case
StringSwitch & Case(const char(&S)[N], const T &Value)
Definition: StringSwitch.h:55
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Definition: ErrorHandling.cpp:60
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:429
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:42
llvm::StringSwitch::Default
R Default(const T &Value) const
Definition: StringSwitch.h:111
MVT llvm::TargetLoweringBase::getRegisterType ( MVT  VT) const
inlineinherited

Return the type of registers that this ValueType will eventually require.

Definition at line 669 of file TargetLowering.h.

669  {
670  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
671  return RegisterTypeForVT[VT.SimpleTy];
672  }
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::RegisterTypeForVT
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
Definition: TargetLowering.h:1571
MVT llvm::TargetLoweringBase::getRegisterType ( LLVMContext &  Context,
EVT  VT 
) const
inlineinherited

Return the type of registers that this ValueType will eventually require.

Definition at line 675 of file TargetLowering.h.

675  {
676  if (VT.isSimple()) {
677  assert((unsigned)VT.getSimpleVT().SimpleTy <
678  array_lengthof(RegisterTypeForVT));
679  return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
680  }
681  if (VT.isVector()) {
682  EVT VT1;
683  MVT RegisterVT;
684  unsigned NumIntermediates;
685  (void)getVectorTypeBreakdown(Context, VT, VT1,
686  NumIntermediates, RegisterVT);
687  return RegisterVT;
688  }
689  if (VT.isInteger()) {
690  return getRegisterType(Context, getTypeToTransformTo(Context, VT));
691  }
692  llvm_unreachable("Unsupported extended type!");
693  }
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:669
llvm::TargetLoweringBase::getVectorTypeBreakdown
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Definition: TargetLoweringBase.cpp:1227
llvm::TargetLoweringBase::RegisterTypeForVT
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE]
True if this is a little endian target.
Definition: TargetLowering.h:1571
llvm::TargetLoweringBase::getTypeToTransformTo
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
Definition: TargetLowering.h:388
virtual uint8_t llvm::TargetLoweringBase::getRepRegClassCostFor ( MVT  VT) const
inlinevirtualinherited

Return the cost of the 'representative' register class for the specified value type.

Definition at line 334 of file TargetLowering.h.

334  {
335  return RepRegClassCostForVT[VT.SimpleTy];
336  }
llvm::TargetLoweringBase::RepRegClassCostForVT
uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1584
virtual const TargetRegisterClass* llvm::TargetLoweringBase::getRepRegClassFor ( MVT  VT) const
inlinevirtualinherited

Return the 'representative' register class for the specified value type.

The 'representative' register class is the largest legal super-reg register class for the register class of the value type. For example, on i386 the rep register class for i8, i16, and i32 are GR32; while the rep register class is GR64 on x86_64.

Reimplemented in llvm::MipsSETargetLowering.

Definition at line 327 of file TargetLowering.h.

327  {
328  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
329  return RC;
330  }
llvm::TargetLoweringBase::RepRegClassForVT
const TargetRegisterClass * RepRegClassForVT[MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1579
SDValue X86TargetLowering::getReturnAddressFrameIndex ( SelectionDAG &  DAG) const

Definition at line 3460 of file X86ISelLowering.cpp.

3460  {
3461  MachineFunction &MF = DAG.getMachineFunction();
3462  const X86RegisterInfo *RegInfo =
3463  static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
3464  X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3465  int ReturnAddrIndex = FuncInfo->getRAIndex();
3466 
3467  if (ReturnAddrIndex == 0) {
3468  // Set up a frame object for the return address.
3469  unsigned SlotSize = RegInfo->getSlotSize();
3470  ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3471  -(int64_t)SlotSize,
3472  false);
3473  FuncInfo->setRAIndex(ReturnAddrIndex);
3474  }
3475 
3476  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3477 }
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
llvm::X86RegisterInfo::getSlotSize
unsigned getSlotSize() const
Definition: X86RegisterInfo.h:128
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1297
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
Definition: MachineFunction.cpp:563
MVT llvm::X86TargetLowering::getScalarShiftAmountTy ( EVT  LHSTy) const
inlineoverridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 524 of file X86ISelLowering.h.

524 { return MVT::i8; }
int X86TargetLowering::getScalingFactorCost ( const AddrMode &  AM,
Type *  Ty 
) const
overridevirtual

Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 22881 of file X86ISelLowering.cpp.

22882  {
22883  // Scaling factors are not free at all.
22884  // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
22885  // will take 2 allocations in the out of order engine instead of 1
22886  // for plain addressing mode, i.e. inst (reg1).
22887  // E.g.,
22888  // vaddps (%rsi,%drx), %ymm0, %ymm1
22889  // Requires two allocations (one for the load, one for the computation)
22890  // whereas:
22891  // vaddps (%rsi), %ymm0, %ymm1
22892  // Requires just 1 allocation, i.e., freeing allocations for other operations
22893  // and having less micro operations to execute.
22894  //
22895  // For some X86 architectures, this is even worse because for instance for
22896  // stores, the complex addressing mode forces the instruction to use the
22897  // "load" ports instead of the dedicated "store" port.
22898  // E.g., on Haswell:
22899  // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
22900  // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
22901  if (isLegalAddressingMode(AM, Ty))
22902  // Scale represents reg2 * scale, thus account for 1
22903  // as soon as we use a second register.
22904  return AM.Scale != 0;
22905  return -1;
22906 }
llvm::X86TargetLowering::isLegalAddressingMode
bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override
Definition: X86ISelLowering.cpp:16686
Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( ) const
inlineinherited

Return target scheduling preference.

Definition at line 301 of file TargetLowering.h.

301  {
302  return SchedPreferenceInfo;
303  }
llvm::TargetLoweringBase::SchedPreferenceInfo
Sched::Preference SchedPreferenceInfo
Definition: TargetLowering.h:1528
virtual Sched::Preference llvm::TargetLoweringBase::getSchedulingPreference ( SDNode *  ) const
inlinevirtualinherited

Some scheduler, e.g. hybrid, can switch to different scheduling heuristics for different nodes. This function returns the preference (or none) for the given node.

Reimplemented in llvm::PPCTargetLowering, and llvm::ARMTargetLowering.

Definition at line 308 of file TargetLowering.h.

308  {
309  return Sched::None;
310  }
const MCPhysReg * X86TargetLowering::getScratchRegisters ( CallingConv::ID  CC) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 1875 of file X86ISelLowering.cpp.

1875  {
1876  static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1877  return ScratchRegs;
1878 }
llvm::MCPhysReg
uint16_t MCPhysReg
Definition: MCRegisterInfo.h:27
EVT X86TargetLowering::getSetCCResultType ( LLVMContext &  Context,
EVT  VT 
) const
overridevirtual

getSetCCResultType - Return the value type to use for ISD::SETCC.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1631 of file X86ISelLowering.cpp.

1631  {
1632  if (!VT.isVector())
1633  return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1634 
1635  if (Subtarget->hasAVX512())
1636  switch(VT.getVectorNumElements()) {
1637  case 8: return MVT::v8i1;
1638  case 16: return MVT::v16i1;
1639  }
1640 
1641  return VT.changeVectorElementTypeToInteger();
1642 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::EVT::isVector
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
llvm::X86Subtarget::hasAVX512
bool hasAVX512() const
Definition: X86Subtarget.h:319
llvm::EVT::changeVectorElementTypeToInteger
EVT changeVectorElementTypeToInteger() const
Definition: ValueTypes.h:81
llvm::EVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
EVT TargetLoweringBase::getShiftAmountTy ( EVT  LHSTy) const
inherited

Definition at line 860 of file TargetLoweringBase.cpp.

860  {
861  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
862  if (LHSTy.isVector())
863  return LHSTy;
864  return getScalarShiftAmountTy(LHSTy);
865 }
llvm::TargetLoweringBase::getScalarShiftAmountTy
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const
Definition: TargetLoweringBase.cpp:856
llvm::EVT::isVector
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
llvm::EVT::isInteger
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
assert
assert(Globals.size() > 1)
MVT llvm::TargetLoweringBase::getSimpleValueType ( Type *  Ty,
bool  AllowUnknown = false 
) const
inlineinherited

Return the MVT corresponding to this LLVM type. See getValueType.

Definition at line 659 of file TargetLowering.h.

659  {
660  return getValueType(Ty, AllowUnknown).getSimpleVT();
661  }
llvm::TargetLoweringBase::getValueType
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
Definition: TargetLowering.h:638
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Definition: ValueTypes.h:204
TargetLowering::ConstraintWeight X86TargetLowering::getSingleConstraintMatchWeight ( AsmOperandInfo &  info,
const char *  constraint 
) const
overridevirtual

Examine constraint string and operand type and determine a weight value. The operand object must already have been set up with the operand type.

Examine constraint type and operand type and determine a weight value. This object must already have been set up with the operand type and the current alternative constraint selected.

Reimplemented from llvm::TargetLowering.

Definition at line 22392 of file X86ISelLowering.cpp.

22393  {
22394  ConstraintWeight weight = CW_Invalid;
22395  Value *CallOperandVal = info.CallOperandVal;
22396  // If we don't have a value, we can't do a match,
22397  // but allow it at the lowest weight.
22398  if (!CallOperandVal)
22399  return CW_Default;
22400  Type *type = CallOperandVal->getType();
22401  // Look at the constraint type.
22402  switch (*constraint) {
22403  default:
22404  weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
22405  case 'R':
22406  case 'q':
22407  case 'Q':
22408  case 'a':
22409  case 'b':
22410  case 'c':
22411  case 'd':
22412  case 'S':
22413  case 'D':
22414  case 'A':
22415  if (CallOperandVal->getType()->isIntegerTy())
22416  weight = CW_SpecificReg;
22417  break;
22418  case 'f':
22419  case 't':
22420  case 'u':
22421  if (type->isFloatingPointTy())
22422  weight = CW_SpecificReg;
22423  break;
22424  case 'y':
22425  if (type->isX86_MMXTy() && Subtarget->hasMMX())
22426  weight = CW_SpecificReg;
22427  break;
22428  case 'x':
22429  case 'Y':
22430  if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
22431  ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
22432  weight = CW_Register;
22433  break;
22434  case 'I':
22435  if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
22436  if (C->getZExtValue() <= 31)
22437  weight = CW_Constant;
22438  }
22439  break;
22440  case 'J':
22441  if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22442  if (C->getZExtValue() <= 63)
22443  weight = CW_Constant;
22444  }
22445  break;
22446  case 'K':
22447  if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22448  if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
22449  weight = CW_Constant;
22450  }
22451  break;
22452  case 'L':
22453  if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22454  if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
22455  weight = CW_Constant;
22456  }
22457  break;
22458  case 'M':
22459  if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22460  if (C->getZExtValue() <= 3)
22461  weight = CW_Constant;
22462  }
22463  break;
22464  case 'N':
22465  if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22466  if (C->getZExtValue() <= 0xff)
22467  weight = CW_Constant;
22468  }
22469  break;
22470  case 'G':
22471  case 'C':
22472  if (dyn_cast<ConstantFP>(CallOperandVal)) {
22473  weight = CW_Constant;
22474  }
22475  break;
22476  case 'e':
22477  if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22478  if ((C->getSExtValue() >= -0x80000000LL) &&
22479  (C->getSExtValue() <= 0x7fffffffLL))
22480  weight = CW_Constant;
22481  }
22482  break;
22483  case 'Z':
22484  if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22485  if (C->getZExtValue() <= 0xffffffff)
22486  weight = CW_Constant;
22487  }
22488  break;
22489  }
22490  return weight;
22491 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
info
lazy value info
Definition: LazyValueInfo.cpp:42
llvm::X86Subtarget::hasMMX
bool hasMMX() const
Definition: X86Subtarget.h:310
llvm::Type::isFloatingPointTy
bool isFloatingPointTy() const
Definition: Type.h:159
llvm::Type::isX86_MMXTy
bool isX86_MMXTy() const
isX86_MMXTy - Return true if this is X86 MMX.
Definition: Type.h:179
llvm::X86Subtarget::hasFp256
bool hasFp256() const
Definition: X86Subtarget.h:320
llvm::ConstantInt
Class for constant integers.
Definition: Constants.h:51
llvm::Value::getType
Type * getType() const
Definition: Value.h:215
llvm::Type::isIntegerTy
bool isIntegerTy() const
Definition: Type.h:193
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:311
llvm::Type::getPrimitiveSizeInBits
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
llvm::Value
LLVM Value Representation.
Definition: Value.h:69
llvm::TargetLowering::getSingleConstraintMatchWeight
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Definition: TargetLowering.cpp:2466
bool X86TargetLowering::getStackCookieLocation ( unsigned &  AddressSpace,
unsigned &  Offset 
) const
overridevirtual

getStackCookieLocation - Return true if the target stores stack protector cookies at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1831 of file X86ISelLowering.cpp.

1832  {
1833  if (!Subtarget->isTargetLinux())
1834  return false;
1835 
1836  if (Subtarget->is64Bit()) {
1837  // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1838  Offset = 0x28;
1839  if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1840  AddressSpace = 256;
1841  else
1842  AddressSpace = 257;
1843  } else {
1844  // %gs:0x14 on i386
1845  Offset = 0x14;
1846  AddressSpace = 256;
1847  }
1848  return true;
1849 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:149
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Definition: TargetMachine.cpp:84
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:22
llvm::X86Subtarget::isTargetLinux
bool isTargetLinux() const
Definition: X86Subtarget.h:382
unsigned llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore ( ) const
inlineinherited

If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Definition at line 839 of file TargetLowering.h.

839  {
840  return StackPointerRegisterToSaveRestore;
841  }
llvm::TargetLoweringBase::StackPointerRegisterToSaveRestore
unsigned StackPointerRegisterToSaveRestore
Definition: TargetLowering.h:1557
const X86Subtarget* llvm::X86TargetLowering::getSubtarget ( ) const
inline

Definition at line 746 of file X86ISelLowering.h.

746  {
747  return Subtarget;
748  }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
const TargetMachine& llvm::TargetLoweringBase::getTargetMachine ( ) const
inlineinherited

Definition at line 149 of file TargetLowering.h.

149 { return TM; }
llvm::TargetLoweringBase::TM
const TargetMachine & TM
True if this is a little endian target.
Definition: TargetLowering.h:1452
const char * X86TargetLowering::getTargetNodeName ( unsigned  Opcode) const
overridevirtual

getTargetNodeName - This method returns the name of a target specific DAG node.

Reimplemented from llvm::TargetLowering.

Definition at line 16516 of file X86ISelLowering.cpp.

16516  {
16517  switch (Opcode) {
16518  default: return nullptr;
16519  case X86ISD::BSF: return "X86ISD::BSF";
16520  case X86ISD::BSR: return "X86ISD::BSR";
16521  case X86ISD::SHLD: return "X86ISD::SHLD";
16522  case X86ISD::SHRD: return "X86ISD::SHRD";
16523  case X86ISD::FAND: return "X86ISD::FAND";
16524  case X86ISD::FANDN: return "X86ISD::FANDN";
16525  case X86ISD::FOR: return "X86ISD::FOR";
16526  case X86ISD::FXOR: return "X86ISD::FXOR";
16527  case X86ISD::FSRL: return "X86ISD::FSRL";
16528  case X86ISD::FILD: return "X86ISD::FILD";
16529  case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
16530  case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
16531  case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
16532  case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
16533  case X86ISD::FLD: return "X86ISD::FLD";
16534  case X86ISD::FST: return "X86ISD::FST";
16535  case X86ISD::CALL: return "X86ISD::CALL";
16536  case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
16537  case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
16538  case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
16539  case X86ISD::BT: return "X86ISD::BT";
16540  case X86ISD::CMP: return "X86ISD::CMP";
16541  case X86ISD::COMI: return "X86ISD::COMI";
16542  case X86ISD::UCOMI: return "X86ISD::UCOMI";
16543  case X86ISD::CMPM: return "X86ISD::CMPM";
16544  case X86ISD::CMPMU: return "X86ISD::CMPMU";
16545  case X86ISD::SETCC: return "X86ISD::SETCC";
16546  case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
16547  case X86ISD::FSETCC: return "X86ISD::FSETCC";
16548  case X86ISD::CMOV: return "X86ISD::CMOV";
16549  case X86ISD::BRCOND: return "X86ISD::BRCOND";
16550  case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
16551  case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
16552  case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
16553  case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
16554  case X86ISD::Wrapper: return "X86ISD::Wrapper";
16555  case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
16556  case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
16557  case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
16558  case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
16559  case X86ISD::PINSRB: return "X86ISD::PINSRB";
16560  case X86ISD::PINSRW: return "X86ISD::PINSRW";
16561  case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
16562  case X86ISD::ANDNP: return "X86ISD::ANDNP";
16563  case X86ISD::PSIGN: return "X86ISD::PSIGN";
16564  case X86ISD::BLENDV: return "X86ISD::BLENDV";
16565  case X86ISD::BLENDI: return "X86ISD::BLENDI";
16566  case X86ISD::SUBUS: return "X86ISD::SUBUS";
16567  case X86ISD::HADD: return "X86ISD::HADD";
16568  case X86ISD::HSUB: return "X86ISD::HSUB";
16569  case X86ISD::FHADD: return "X86ISD::FHADD";
16570  case X86ISD::FHSUB: return "X86ISD::FHSUB";
16571  case X86ISD::UMAX: return "X86ISD::UMAX";
16572  case X86ISD::UMIN: return "X86ISD::UMIN";
16573  case X86ISD::SMAX: return "X86ISD::SMAX";
16574  case X86ISD::SMIN: return "X86ISD::SMIN";
16575  case X86ISD::FMAX: return "X86ISD::FMAX";
16576  case X86ISD::FMIN: return "X86ISD::FMIN";
16577  case X86ISD::FMAXC: return "X86ISD::FMAXC";
16578  case X86ISD::FMINC: return "X86ISD::FMINC";
16579  case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
16580  case X86ISD::FRCP: return "X86ISD::FRCP";
16581  case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
16582  case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
16583  case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
16584  case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
16585  case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
16586  case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
16587  case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
16588  case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
16589  case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
16590  case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
16591  case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
16592  case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
16593  case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
16594  case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
16595  case X86ISD::VZEXT: return "X86ISD::VZEXT";
16596  case X86ISD::VSEXT: return "X86ISD::VSEXT";
16597  case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
16598  case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
16599  case X86ISD::VINSERT: return "X86ISD::VINSERT";
16600  case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
16601  case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
16602  case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
16603  case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
16604  case X86ISD::VSHL: return "X86ISD::VSHL";
16605  case X86ISD::VSRL: return "X86ISD::VSRL";
16606  case X86ISD::VSRA: return "X86ISD::VSRA";
16607  case X86ISD::VSHLI: return "X86ISD::VSHLI";
16608  case X86ISD::VSRLI: return "X86ISD::VSRLI";
16609  case X86ISD::VSRAI: return "X86ISD::VSRAI";
16610  case X86ISD::CMPP: return "X86ISD::CMPP";
16611  case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
16612  case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
16613  case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
16614  case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
16615  case X86ISD::ADD: return "X86ISD::ADD";
16616  case X86ISD::SUB: return "X86ISD::SUB";
16617  case X86ISD::ADC: return "X86ISD::ADC";
16618  case X86ISD::SBB: return "X86ISD::SBB";
16619  case X86ISD::SMUL: return "X86ISD::SMUL";
16620  case X86ISD::UMUL: return "X86ISD::UMUL";
16621  case X86ISD::INC: return "X86ISD::INC";
16622  case X86ISD::DEC: return "X86ISD::DEC";
16623  case X86ISD::OR: return "X86ISD::OR";
16624  case X86ISD::XOR: return "X86ISD::XOR";
16625  case X86ISD::AND: return "X86ISD::AND";
16626  case X86ISD::BEXTR: return "X86ISD::BEXTR";
16627  case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
16628  case X86ISD::PTEST: return "X86ISD::PTEST";
16629  case X86ISD::TESTP: return "X86ISD::TESTP";
16630  case X86ISD::TESTM: return "X86ISD::TESTM";
16631  case X86ISD::TESTNM: return "X86ISD::TESTNM";
16632  case X86ISD::KORTEST: return "X86ISD::KORTEST";
16633  case X86ISD::PACKSS: return "X86ISD::PACKSS";
16634  case X86ISD::PACKUS: return "X86ISD::PACKUS";
16635  case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
16636  case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
16637  case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
16638  case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
16639  case X86ISD::SHUFP: return "X86ISD::SHUFP";
16640  case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
16641  case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
16642  case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
16643  case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
16644  case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
16645  case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
16646  case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
16647  case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
16648  case X86ISD::MOVSD: return "X86ISD::MOVSD";
16649  case X86ISD::MOVSS: return "X86ISD::MOVSS";
16650  case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
16651  case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
16652  case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
16653  case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
16654  case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
16655  case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
16656  case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
16657  case X86ISD::VPERMV: return "X86ISD::VPERMV";
16658  case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
16659  case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
16660  case X86ISD::VPERMI: return "X86ISD::VPERMI";
16661  case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
16662  case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
16663  case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
16664  case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
16665  case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
16666  case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
16667  case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
16668  case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
16669  case X86ISD::SAHF: return "X86ISD::SAHF";
16670  case X86ISD::RDRAND: return "X86ISD::RDRAND";
16671  case X86ISD::RDSEED: return "X86ISD::RDSEED";
16672  case X86ISD::FMADD: return "X86ISD::FMADD";
16673  case X86ISD::FMSUB: return "X86ISD::FMSUB";
16674  case X86ISD::FNMADD: return "X86ISD::FNMADD";
16675  case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
16676  case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
16677  case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
16678  case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
16679  case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
16680  case X86ISD::XTEST: return "X86ISD::XTEST";
16681  }
16682 }
llvm::X86ISD::PSIGN
PSIGN - Copy integer sign.
Definition: X86ISelLowering.h:188
llvm::X86ISD::PSHUFB
PSHUFB - Shuffle 16 8-bit values within a vector.
Definition: X86ISelLowering.h:182
llvm::X86ISD::BLENDV
BLENDV - Blend where the selector is a register.
Definition: X86ISelLowering.h:191
llvm::X86ISD::FHSUB
FHSUB - Floating point horizontal sub.
Definition: X86ISelLowering.h:209
llvm::X86ISD::HSUB
HSUB - Integer horizontal sub.
Definition: X86ISelLowering.h:203
llvm::X86ISD::BT
X86 bit-test instructions.
Definition: X86ISelLowering.h:96
llvm::X86ISD::HADD
HADD - Integer horizontal add.
Definition: X86ISelLowering.h:200
llvm::X86ISD::CMP
X86 compare and logical compare instructions.
Definition: X86ISelLowering.h:93
llvm::X86ISD::FMAXC
FMAXC, FMINC - Commutative FMIN and FMAX.
Definition: X86ISelLowering.h:222
llvm::X86ISD::SMAX
SMAX, SMIN - Signed integer max and min.
Definition: X86ISelLowering.h:215
llvm::X86ISD::REP_STOS
REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
Definition: X86ISelLowering.h:135
llvm::X86ISD::REP_MOVS
REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
Definition: X86ISelLowering.h:138
llvm::X86ISD::BLENDI
BLENDI - Blend where the selector is an immediate.
Definition: X86ISelLowering.h:194
llvm::X86ISD::RDPMC_DAG
X86 Read Performance Monitoring Counters.
Definition: X86ISelLowering.h:90
llvm::X86ISD::RDTSCP_DAG
X86 Read Time-Stamp Counter and Processor ID.
Definition: X86ISelLowering.h:87
llvm::X86ISD::UMAX
UMAX, UMIN - Unsigned integer max and min.
Definition: X86ISelLowering.h:212
llvm::X86ISD::ANDNP
ANDNP - Bitwise Logical AND NOT of Packed FP values.
Definition: X86ISelLowering.h:185
llvm::X86ISD::FHADD
FHADD - Floating point horizontal add.
Definition: X86ISelLowering.h:206
virtual bool llvm::TargetLoweringBase::getTgtMemIntrinsic ( IntrinsicInfo &  ,
const CallInst &  ,
unsigned   
) const
inlinevirtualinherited

Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). If this is the case, it returns true and store the intrinsic information into the IntrinsicInfo that was passed to the function.

Reimplemented in llvm::NVPTXTargetLowering, llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 439 of file TargetLowering.h.

440  {
441  return false;
442  }
LegalizeAction llvm::TargetLoweringBase::getTruncStoreAction ( MVT  ValVT,
MVT  MemVT 
) const
inlineinherited

Return how this store with truncation should be treated: either it is legal, needs to be promoted to a larger size, needs to be expanded to some other code sequence, or the target has a custom expander for it.

Definition at line 535 of file TargetLowering.h.

535  {
536  assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
537  "Table isn't big enough!");
538  return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]
539  [MemVT.SimpleTy];
540  }
llvm::TargetLoweringBase::TruncStoreActions
uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1607
assert
assert(Globals.size() > 1)
LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( LLVMContext &  Context,
EVT  VT 
) const
inlineinherited

Return how we should legalize values of this type, either it is already legal (return 'Legal') or we need to promote it to a larger type (return 'Promote'), or we need to expand it into multiple registers of smaller integer type (return 'Expand'). 'Custom' is not an option.

Definition at line 375 of file TargetLowering.h.

375  {
376  return getTypeConversion(Context, VT).first;
377  }
llvm::TargetLoweringBase::getTypeConversion
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
Definition: TargetLowering.h:1629
LegalizeTypeAction llvm::TargetLoweringBase::getTypeAction ( MVT  VT) const
inlineinherited

Definition at line 378 of file TargetLowering.h.

378  {
379  return ValueTypeActions.getTypeAction(VT);
380  }
llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction
LegalizeTypeAction getTypeAction(MVT VT) const
Definition: TargetLowering.h:357
llvm::TargetLoweringBase::ValueTypeActions
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
Definition: TargetLowering.h:1625
LegalizeKind llvm::TargetLoweringBase::getTypeConversion ( LLVMContext &  Context,
EVT  VT 
) const
inlineinherited

Reset the operation actions based on target options.

Definition at line 1629 of file TargetLowering.h.

1629  {
1630  // If this is a simple type, use the ComputeRegisterProp mechanism.
1631  if (VT.isSimple()) {
1632  MVT SVT = VT.getSimpleVT();
1633  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1634  MVT NVT = TransformToType[SVT.SimpleTy];
1635  LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1636 
1637  assert(
1638  (LA == TypeLegal || LA == TypeSoftenFloat ||
1639  ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1640  && "Promote may not follow Expand or Promote");
1641 
1642  if (LA == TypeSplitVector)
1643  return LegalizeKind(LA, EVT::getVectorVT(Context,
1644  SVT.getVectorElementType(),
1645  SVT.getVectorNumElements()/2));
1646  if (LA == TypeScalarizeVector)
1647  return LegalizeKind(LA, SVT.getVectorElementType());
1648  return LegalizeKind(LA, NVT);
1649  }
1650 
1651  // Handle Extended Scalar Types.
1652  if (!VT.isVector()) {
1653  assert(VT.isInteger() && "Float types must be simple");
1654  unsigned BitSize = VT.getSizeInBits();
1655  // First promote to a power-of-two size, then expand if necessary.
1656  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1657  EVT NVT = VT.getRoundIntegerType(Context);
1658  assert(NVT != VT && "Unable to round integer VT");
1659  LegalizeKind NextStep = getTypeConversion(Context, NVT);
1660  // Avoid multi-step promotion.
1661  if (NextStep.first == TypePromoteInteger) return NextStep;
1662  // Return rounded integer type.
1663  return LegalizeKind(TypePromoteInteger, NVT);
1664  }
1665 
1666  return LegalizeKind(TypeExpandInteger,
1667  EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1668  }
1669 
1670  // Handle vector types.
1671  unsigned NumElts = VT.getVectorNumElements();
1672  EVT EltVT = VT.getVectorElementType();
1673 
1674  // Vectors with only one element are always scalarized.
1675  if (NumElts == 1)
1676  return LegalizeKind(TypeScalarizeVector, EltVT);
1677 
1678  // Try to widen vector elements until the element type is a power of two and
1679  // promote it to a legal type later on, for example:
1680  // <3 x i8> -> <4 x i8> -> <4 x i32>
1681  if (EltVT.isInteger()) {
1682  // Vectors with a number of elements that is not a power of two are always
1683  // widened, for example <3 x i8> -> <4 x i8>.
1684  if (!VT.isPow2VectorType()) {
1685  NumElts = (unsigned)NextPowerOf2(NumElts);
1686  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1687  return LegalizeKind(TypeWidenVector, NVT);
1688  }
1689 
1690  // Examine the element type.
1691  LegalizeKind LK = getTypeConversion(Context, EltVT);
1692 
1693  // If type is to be expanded, split the vector.
1694  // <4 x i140> -> <2 x i140>
1695  if (LK.first == TypeExpandInteger)
1696  return LegalizeKind(TypeSplitVector,
1697  EVT::getVectorVT(Context, EltVT, NumElts / 2));
1698 
1699  // Promote the integer element types until a legal vector type is found
1700  // or until the element integer type is too big. If a legal type was not
1701  // found, fallback to the usual mechanism of widening/splitting the
1702  // vector.
1703  EVT OldEltVT = EltVT;
1704  while (1) {
1705  // Increase the bitwidth of the element to the next pow-of-two
1706  // (which is greater than 8 bits).
1707  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1708  ).getRoundIntegerType(Context);
1709 
1710  // Stop trying when getting a non-simple element type.
1711  // Note that vector elements may be greater than legal vector element
1712  // types. Example: X86 XMM registers hold 64bit element on 32bit
1713  // systems.
1714  if (!EltVT.isSimple()) break;
1715 
1716  // Build a new vector type and check if it is legal.
1717  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1718  // Found a legal promoted vector type.
1719  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1720  return LegalizeKind(TypePromoteInteger,
1721  EVT::getVectorVT(Context, EltVT, NumElts));
1722  }
1723 
1724  // Reset the type to the unexpanded type if we did not find a legal vector
1725  // type with a promoted vector element type.
1726  EltVT = OldEltVT;
1727  }
1728 
1729  // Try to widen the vector until a legal type is found.
1730  // If there is no wider legal type, split the vector.
1731  while (1) {
1732  // Round up to the next power of 2.
1733  NumElts = (unsigned)NextPowerOf2(NumElts);
1734 
1735  // If there is no simple vector type with this many elements then there
1736  // cannot be a larger legal vector type. Note that this assumes that
1737  // there are no skipped intermediate vector types in the simple types.
1738  if (!EltVT.isSimple()) break;
1739  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1740  if (LargerVector == MVT()) break;
1741 
1742  // If this type is legal then widen the vector.
1743  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1744  return LegalizeKind(TypeWidenVector, LargerVector);
1745  }
1746 
1747  // Widen odd vectors to next power of two.
1748  if (!VT.isPow2VectorType()) {
1749  EVT NVT = VT.getPow2VectorType(Context);
1750  return LegalizeKind(TypeWidenVector, NVT);
1751  }
1752 
1753  // Vectors with illegal element types are expanded.
1754  EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1755  return LegalizeKind(TypeSplitVector, NVT);
1756  }
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:505
llvm::TargetLoweringBase::TransformToType
MVT TransformToType[MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1591
llvm::TargetLoweringBase::LegalizeKind
std::pair< LegalizeTypeAction, EVT > LegalizeKind
Definition: TargetLowering.h:106
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction
LegalizeTypeAction getTypeAction(MVT VT) const
Definition: TargetLowering.h:357
llvm::NextPowerOf2
uint64_t NextPowerOf2(uint64_t A)
Definition: MathExtras.h:567
llvm::EVT::getVectorVT
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
llvm::TargetLoweringBase::ValueTypeActions
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
Definition: TargetLowering.h:1625
llvm::TargetLoweringBase::getTypeConversion
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
Definition: TargetLowering.h:1629
llvm::isPowerOf2_32
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:363
llvm::EVT::getIntegerVT
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Definition: ValueTypes.h:62
MVT X86TargetLowering::getTypeForExtArgOrReturn ( MVT  VT,
ISD::NodeType  ExtendKind 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2035 of file X86ISelLowering.cpp.

2036  {
2037  MVT ReturnMVT;
2038  // TODO: Is this also valid on 32-bit?
2039  if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2040  ReturnMVT = MVT::i8;
2041  else
2042  ReturnMVT = MVT::i32;
2043 
2044  MVT MinVT = getRegisterType(ReturnMVT);
2045  return VT.bitsLT(MinVT) ? MinVT : VT;
2046 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::MVT::bitsLT
bool bitsLT(MVT VT) const
Return true if this has less bits than VT.
Definition: MachineValueType.h:459
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:669
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
std::pair< unsigned, MVT > TargetLoweringBase::getTypeLegalizationCost ( Type *  Ty) const
inherited

Estimate the cost of type-legalization and the legalized type.

Definition at line 1425 of file TargetLoweringBase.cpp.

1425  {
1426  LLVMContext &C = Ty->getContext();
1427  EVT MTy = getValueType(Ty);
1428 
1429  unsigned Cost = 1;
1430  // We keep legalizing the type until we find a legal kind. We assume that
1431  // the only operation that costs anything is the split. After splitting
1432  // we need to handle two types.
1433  while (true) {
1434  LegalizeKind LK = getTypeConversion(C, MTy);
1435 
1436  if (LK.first == TypeLegal)
1437  return std::make_pair(Cost, MTy.getSimpleVT());
1438 
1439  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1440  Cost *= 2;
1441 
1442  // Keep legalizing the type.
1443  MTy = LK.second;
1444  }
1445 }
llvm::TargetLoweringBase::LegalizeKind
std::pair< LegalizeTypeAction, EVT > LegalizeKind
Definition: TargetLowering.h:106
llvm::TargetLoweringBase::getValueType
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
Definition: TargetLowering.h:638
llvm::Type::getContext
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
llvm::TargetLoweringBase::getTypeConversion
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
Definition: TargetLowering.h:1629
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Definition: ValueTypes.h:204
EVT llvm::TargetLoweringBase::getTypeToExpandTo ( LLVMContext &  Context,
EVT  VT 
) const
inlineinherited

For types supported by the target, this is an identity function. For types that must be expanded (i.e. integer types that are larger than the largest integer register or illegal floating point types), this returns the largest legal type it will be expanded to.

Definition at line 396 of file TargetLowering.h.

396  {
397  assert(!VT.isVector());
398  while (true) {
399  switch (getTypeAction(Context, VT)) {
400  case TypeLegal:
401  return VT;
402  case TypeExpandInteger:
403  VT = getTypeToTransformTo(Context, VT);
404  break;
405  default:
406  llvm_unreachable("Type is not legal nor is it to be expanded!");
407  }
408  }
409  }
llvm::TargetLoweringBase::getTypeAction
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Definition: TargetLowering.h:375
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::getTypeToTransformTo
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
Definition: TargetLowering.h:388
MVT llvm::TargetLoweringBase::getTypeToPromoteTo ( unsigned  Op,
MVT  VT 
) const
inlineinherited

If the action for this operation is to promote, this method returns the ValueType to promote to.

Definition at line 611 of file TargetLowering.h.

611  {
612  assert(getOperationAction(Op, VT) == Promote &&
613  "This operation isn't promoted!");
614 
615  // See if this has an explicit type specified.
616  std::map<std::pair<unsigned, MVT::SimpleValueType>,
617  MVT::SimpleValueType>::const_iterator PTTI =
618  PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
619  if (PTTI != PromoteToType.end()) return PTTI->second;
620 
621  assert((VT.isInteger() || VT.isFloatingPoint()) &&
622  "Cannot autopromote this type, add it with AddPromotedToType.");
623 
624  MVT NVT = VT;
625  do {
626  NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
627  assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
628  "Didn't find type to promote to!");
629  } while (!isTypeLegal(NVT) ||
630  getOperationAction(Op, NVT) == Promote);
631  return NVT;
632  }
llvm::TargetLoweringBase::PromoteToType
std::map< std::pair< unsigned, MVT::SimpleValueType >, MVT::SimpleValueType > PromoteToType
Definition: TargetLowering.h:1774
llvm::TargetLoweringBase::getOperationAction
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Definition: TargetLowering.h:477
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
assert
assert(Globals.size() > 1)
EVT llvm::TargetLoweringBase::getTypeToTransformTo ( LLVMContext &  Context,
EVT  VT 
) const
inlineinherited

For types supported by the target, this is an identity function. For types that must be promoted to larger types, this returns the larger type to promote to. For integer types that are larger than the largest integer register, this contains one step in the expansion to get to the smaller register. For illegal floating point types, this returns the integer type to transform to.

Definition at line 388 of file TargetLowering.h.

388  {
389  return getTypeConversion(Context, VT).second;
390  }
llvm::TargetLoweringBase::getTypeConversion
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Reset the operation actions based on target options.
Definition: TargetLowering.h:1629
EVT llvm::TargetLoweringBase::getValueType ( Type *  Ty,
bool  AllowUnknown = false 
) const
inlineinherited

Return the EVT corresponding to this LLVM type. This is fixed by the LLVM operations except for the pointer size. If AllowUnknown is true, this will return MVT::Other for types with no EVT counterpart (e.g. structs), otherwise it will assert.

Definition at line 638 of file TargetLowering.h.

638  {
639  // Lower scalar pointers to native pointer types.
640  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
641  return getPointerTy(PTy->getAddressSpace());
642 
643  if (Ty->isVectorTy()) {
644  VectorType *VTy = cast<VectorType>(Ty);
645  Type *Elm = VTy->getElementType();
646  // Lower vectors of pointers to native pointer types.
647  if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
648  EVT PointerTy(getPointerTy(PT->getAddressSpace()));
649  Elm = PointerTy.getTypeForEVT(Ty->getContext());
650  }
651 
652  return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
653  VTy->getNumElements());
654  }
655  return EVT::getEVT(Ty, AllowUnknown);
656  }
llvm::PointerTy
void * PointerTy
Definition: GenericValue.h:23
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::EVT::getVectorVT
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
llvm::EVT::getEVT
static EVT getEVT(Type *Ty, bool HandleUnknown=false)
Definition: ValueTypes.cpp:275
Type
RelocType Type
Definition: COFFYAML.cpp:285
const ValueTypeActionImpl& llvm::TargetLoweringBase::getValueTypeActions ( ) const
inlineinherited

Definition at line 367 of file TargetLowering.h.

367  {
368  return ValueTypeActions;
369  }
llvm::TargetLoweringBase::ValueTypeActions
ValueTypeActionImpl ValueTypeActions
True if this is a little endian target.
Definition: TargetLowering.h:1625
virtual MVT llvm::TargetLoweringBase::getVectorIdxTy ( ) const
inlinevirtualinherited

Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 169 of file TargetLowering.h.

169  {
170  return getPointerTy();
171  }
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
unsigned TargetLoweringBase::getVectorTypeBreakdown ( LLVMContext &  Context,
EVT  VT,
EVT &  IntermediateVT,
unsigned &  NumIntermediates,
MVT &  RegisterVT 
) const
inherited

Vector types are broken down into some number of legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

getVectorTypeBreakdown - Vector types are broken down into some number of legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.

This method returns the number of registers needed, and the VT for each register. It also returns the VT and quantity of the intermediate values before they are promoted/expanded.

Definition at line 1227 of file TargetLoweringBase.cpp.

1230  {
1231  unsigned NumElts = VT.getVectorNumElements();
1232 
1233  // If there is a wider vector type with the same element type as this one,
1234  // or a promoted vector type that has the same number of elements which
1235  // are wider, then we should convert to that legal vector type.
1236  // This handles things like <2 x float> -> <4 x float> and
1237  // <4 x i1> -> <4 x i32>.
1238  LegalizeTypeAction TA = getTypeAction(Context, VT);
1239  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1240  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1241  if (isTypeLegal(RegisterEVT)) {
1242  IntermediateVT = RegisterEVT;
1243  RegisterVT = RegisterEVT.getSimpleVT();
1244  NumIntermediates = 1;
1245  return 1;
1246  }
1247  }
1248 
1249  // Figure out the right, legal destination reg to copy into.
1250  EVT EltTy = VT.getVectorElementType();
1251 
1252  unsigned NumVectorRegs = 1;
1253 
1254  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1255  // could break down into LHS/RHS like LegalizeDAG does.
1256  if (!isPowerOf2_32(NumElts)) {
1257  NumVectorRegs = NumElts;
1258  NumElts = 1;
1259  }
1260 
1261  // Divide the input until we get to a supported size. This will always
1262  // end with a scalar if the target doesn't support vectors.
1263  while (NumElts > 1 && !isTypeLegal(
1264  EVT::getVectorVT(Context, EltTy, NumElts))) {
1265  NumElts >>= 1;
1266  NumVectorRegs <<= 1;
1267  }
1268 
1269  NumIntermediates = NumVectorRegs;
1270 
1271  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1272  if (!isTypeLegal(NewVT))
1273  NewVT = EltTy;
1274  IntermediateVT = NewVT;
1275 
1276  MVT DestVT = getRegisterType(Context, NewVT);
1277  RegisterVT = DestVT;
1278  unsigned NewVTSize = NewVT.getSizeInBits();
1279 
1280  // Convert sizes such as i33 to i64.
1281  if (!isPowerOf2_32(NewVTSize))
1282  NewVTSize = NextPowerOf2(NewVTSize);
1283 
1284  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1285  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1286 
1287  // Otherwise, promotion or legal types use the same number of registers as
1288  // the vector decimated to the appropriate level.
1289  return NumVectorRegs;
1290 }
llvm::TargetLoweringBase::getTypeAction
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Definition: TargetLowering.h:375
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Definition: ValueTypes.h:217
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:669
llvm::NextPowerOf2
uint64_t NextPowerOf2(uint64_t A)
Definition: MathExtras.h:567
llvm::EVT::getVectorVT
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
llvm::TargetLoweringBase::getTypeToTransformTo
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
Definition: TargetLowering.h:388
llvm::isPowerOf2_32
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:363
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Definition: ValueTypes.h:204
llvm::EVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
virtual void llvm::TargetLowering::HandleByVal ( CCState *  ,
unsigned &  ,
unsigned   
) const
inlinevirtualinherited

Target-specific cleanup for formal ByVal parameters.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 2266 of file TargetLowering.h.

2266 {}
bool llvm::TargetLoweringBase::hasBigEndianPartOrdering ( EVT  VT) const
inlineinherited

When splitting a value of the specified type into parts, does the Lo or Hi part come first? This usually follows the endianness, except for ppcf128, where the Hi part always comes first.

Definition at line 731 of file TargetLowering.h.

731  {
732  return isBigEndian() || VT == MVT::ppcf128;
733  }
bool llvm::TargetLoweringBase::hasExtractBitsInsn ( ) const
inlineinherited

Return true if the target has BitExtract instructions.

Definition at line 186 of file TargetLowering.h.

186 { return HasExtractBitsInsn; }
bool llvm::TargetLoweringBase::hasMultipleConditionRegisters ( ) const
inlineinherited

Return true if multiple condition registers are available.

Definition at line 181 of file TargetLowering.h.

181  {
182  return HasMultipleConditionRegisters;
183  }
virtual bool llvm::TargetLoweringBase::hasPairedLoad ( Type *  ,
unsigned &   
) const
inlinevirtualinherited

Return true if the target supplies and combines to a paired load two loaded values of type LoadedType next to each other in memory. RequiredAlignment gives the minimal alignment constraints that must be met to be able to select this paired load.

This information is not used to generate actual paired loads, but it is used to generate a sequence of loads that is easier to combine into a paired load. For instance, something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 will be optimized into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32).

In other words, unless the target performs a post-isel load combining, this information should not be provided because it will generate more loads.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1356 of file TargetLowering.h.

1357  {
1358  return false;
1359  }
virtual bool llvm::TargetLoweringBase::hasPairedLoad ( EVT  ,
unsigned &   
) const
inlinevirtualinherited

Specify maximum number of store instructions per memset call.

When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 1361 of file TargetLowering.h.

1362  {
1363  return false;
1364  }
bool llvm::TargetLoweringBase::hasTargetDAGCombine ( ISD::NodeType  NT) const
inlineinherited

If true, the target has custom DAG combine transformations that it can perform for the specified node.

Definition at line 737 of file TargetLowering.h.

737  {
738  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
739  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
740  }
llvm::TargetLoweringBase::TargetDAGCombineArray
unsigned char TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]
Definition: TargetLowering.h:1765
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert
assert(Globals.size() > 1)
void TargetLoweringBase::initActions ( )
protectedinherited

Initialize all of the actions to default values.

Definition at line 733 of file TargetLoweringBase.cpp.

733  {
734  // All operations default to being supported.
735  memset(OpActions, 0, sizeof(OpActions));
736  memset(LoadExtActions, 0, sizeof(LoadExtActions));
737  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
738  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
739  memset(CondCodeActions, 0, sizeof(CondCodeActions));
740  memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
741  memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
742 
743  // Set default actions for various operations.
744  for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
745  // Default all indexed load / store to expand.
746  for (unsigned IM = (unsigned)ISD::PRE_INC;
747  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
748  setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
749  setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
750  }
751 
752  // Most backends expect to see the node which just returns the value loaded.
753  setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS,
754  (MVT::SimpleValueType)VT, Expand);
755 
756  // These operations default to expand.
757  setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
758  setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
759 
760  // These library functions default to expand.
761  setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand);
762 
763  // These operations default to expand for vector types.
764  if (VT >= MVT::FIRST_VECTOR_VALUETYPE &&
765  VT <= MVT::LAST_VECTOR_VALUETYPE) {
766  setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
767  setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG,
768  (MVT::SimpleValueType)VT, Expand);
769  setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG,
770  (MVT::SimpleValueType)VT, Expand);
771  setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG,
772  (MVT::SimpleValueType)VT, Expand);
773  }
774  }
775 
776  // Most targets ignore the @llvm.prefetch intrinsic.
777  setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
778 
779  // ConstantFP nodes default to expand. Targets can either change this to
780  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
781  // to optimize expansions for certain constants.
782  setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
783  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
784  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
785  setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
786  setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
787 
788  // These library functions default to expand.
789  setOperationAction(ISD::FLOG , MVT::f16, Expand);
790  setOperationAction(ISD::FLOG2, MVT::f16, Expand);
791  setOperationAction(ISD::FLOG10, MVT::f16, Expand);
792  setOperationAction(ISD::FEXP , MVT::f16, Expand);
793  setOperationAction(ISD::FEXP2, MVT::f16, Expand);
794  setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
795  setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
796  setOperationAction(ISD::FCEIL, MVT::f16, Expand);
797  setOperationAction(ISD::FRINT, MVT::f16, Expand);
798  setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
799  setOperationAction(ISD::FROUND, MVT::f16, Expand);
800  setOperationAction(ISD::FLOG , MVT::f32, Expand);
801  setOperationAction(ISD::FLOG2, MVT::f32, Expand);
802  setOperationAction(ISD::FLOG10, MVT::f32, Expand);
803  setOperationAction(ISD::FEXP , MVT::f32, Expand);
804  setOperationAction(ISD::FEXP2, MVT::f32, Expand);
805  setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
806  setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
807  setOperationAction(ISD::FCEIL, MVT::f32, Expand);
808  setOperationAction(ISD::FRINT, MVT::f32, Expand);
809  setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
810  setOperationAction(ISD::FROUND, MVT::f32, Expand);
811  setOperationAction(ISD::FLOG , MVT::f64, Expand);
812  setOperationAction(ISD::FLOG2, MVT::f64, Expand);
813  setOperationAction(ISD::FLOG10, MVT::f64, Expand);
814  setOperationAction(ISD::FEXP , MVT::f64, Expand);
815  setOperationAction(ISD::FEXP2, MVT::f64, Expand);
816  setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
817  setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
818  setOperationAction(ISD::FCEIL, MVT::f64, Expand);
819  setOperationAction(ISD::FRINT, MVT::f64, Expand);
820  setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
821  setOperationAction(ISD::FROUND, MVT::f64, Expand);
822  setOperationAction(ISD::FLOG , MVT::f128, Expand);
823  setOperationAction(ISD::FLOG2, MVT::f128, Expand);
824  setOperationAction(ISD::FLOG10, MVT::f128, Expand);
825  setOperationAction(ISD::FEXP , MVT::f128, Expand);
826  setOperationAction(ISD::FEXP2, MVT::f128, Expand);
827  setOperationAction(ISD::FFLOOR, MVT::f128, Expand);
828  setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand);
829  setOperationAction(ISD::FCEIL, MVT::f128, Expand);
830  setOperationAction(ISD::FRINT, MVT::f128, Expand);
831  setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
832  setOperationAction(ISD::FROUND, MVT::f128, Expand);
833 
834  // Default ISD::TRAP to expand (which turns it into abort).
835  setOperationAction(ISD::TRAP, MVT::Other, Expand);
836 
837  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
838  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
839  //
840  setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
841 }
llvm::TargetLoweringBase::IndexedModeActions
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
Definition: TargetLowering.h:1615
llvm::TargetLoweringBase::TruncStoreActions
uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1607
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Definition: TargetLowering.h:1102
llvm::TargetLoweringBase::TargetDAGCombineArray
unsigned char TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]
Definition: TargetLowering.h:1765
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
llvm::TargetLoweringBase::LoadExtActions
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]
Definition: TargetLowering.h:1603
llvm::ISD::TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:622
llvm::ISD::DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:625
llvm::LibFunc::memset
void *memset(void *b, int c, size_t len);
Definition: TargetLibraryInfo.h:414
llvm::TargetLoweringBase::RegClassForVT
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1569
llvm::TargetLoweringBase::setIndexedLoadAction
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Definition: TargetLowering.h:1131
llvm::TargetLoweringBase::CondCodeActions
uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE+15)/16]
Definition: TargetLowering.h:1623
llvm::TargetLoweringBase::OpActions
uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]
Definition: TargetLowering.h:1598
llvm::TargetLoweringBase::setIndexedStoreAction
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Definition: TargetLowering.h:1145
SDValue X86TargetLowering::InsertBitToMaskVector ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Insert one bit to mask vector, like v16i1 or v8i1. AVX-512 feature.

Definition at line 9973 of file X86ISelLowering.cpp.

9973  {
9974  SDLoc dl(Op);
9975  SDValue Vec = Op.getOperand(0);
9976  SDValue Elt = Op.getOperand(1);
9977  SDValue Idx = Op.getOperand(2);
9978  MVT VecVT = Vec.getSimpleValueType();
9979 
9980  if (!isa<ConstantSDNode>(Idx)) {
9981  // Non constant index. Extend source and destination,
9982  // insert element and then truncate the result.
9983  MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9984  MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
9985  SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
9986  DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
9987  DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
9988  return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
9989  }
9990 
9991  unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9992  SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
9993  if (Vec.getOpcode() == ISD::UNDEF)
9994  return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
9995  DAG.getConstant(IdxVal, MVT::i8));
9996  const TargetRegisterClass* rc = getRegClassFor(VecVT);
9997  unsigned MaxSift = rc->getSize()*8 - 1;
9998  EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
9999  DAG.getConstant(MaxSift, MVT::i8));
10000  EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10001  DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10002  return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10003 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::ISD::UNDEF
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Definition: TargetLowering.h:314
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
int TargetLoweringBase::InstructionOpcodeToISD ( unsigned  Opcode) const
inherited

Get the ISD node that corresponds to the Instruction class opcode.

Definition at line 1353 of file TargetLoweringBase.cpp.

1353  {
1354  enum InstructionOpcodes {
1355 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1356 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1357 #include "llvm/IR/Instruction.def"
1358  };
1359  switch (static_cast<InstructionOpcodes>(Opcode)) {
1360  case Ret: return 0;
1361  case Br: return 0;
1362  case Switch: return 0;
1363  case IndirectBr: return 0;
1364  case Invoke: return 0;
1365  case Resume: return 0;
1366  case Unreachable: return 0;
1367  case Add: return ISD::ADD;
1368  case FAdd: return ISD::FADD;
1369  case Sub: return ISD::SUB;
1370  case FSub: return ISD::FSUB;
1371  case Mul: return ISD::MUL;
1372  case FMul: return ISD::FMUL;
1373  case UDiv: return ISD::UDIV;
1374  case SDiv: return ISD::SDIV;
1375  case FDiv: return ISD::FDIV;
1376  case URem: return ISD::UREM;
1377  case SRem: return ISD::SREM;
1378  case FRem: return ISD::FREM;
1379  case Shl: return ISD::SHL;
1380  case LShr: return ISD::SRL;
1381  case AShr: return ISD::SRA;
1382  case And: return ISD::AND;
1383  case Or: return ISD::OR;
1384  case Xor: return ISD::XOR;
1385  case Alloca: return 0;
1386  case Load: return ISD::LOAD;
1387  case Store: return ISD::STORE;
1388  case GetElementPtr: return 0;
1389  case Fence: return 0;
1390  case AtomicCmpXchg: return 0;
1391  case AtomicRMW: return 0;
1392  case Trunc: return ISD::TRUNCATE;
1393  case ZExt: return ISD::ZERO_EXTEND;
1394  case SExt: return ISD::SIGN_EXTEND;
1395  case FPToUI: return ISD::FP_TO_UINT;
1396  case FPToSI: return ISD::FP_TO_SINT;
1397  case UIToFP: return ISD::UINT_TO_FP;
1398  case SIToFP: return ISD::SINT_TO_FP;
1399  case FPTrunc: return ISD::FP_ROUND;
1400  case FPExt: return ISD::FP_EXTEND;
1401  case PtrToInt: return ISD::BITCAST;
1402  case IntToPtr: return ISD::BITCAST;
1403  case BitCast: return ISD::BITCAST;
1404  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1405  case ICmp: return ISD::SETCC;
1406  case FCmp: return ISD::SETCC;
1407  case PHI: return 0;
1408  case Call: return 0;
1409  case Select: return ISD::SELECT;
1410  case UserOp1: return 0;
1411  case UserOp2: return 0;
1412  case VAArg: return 0;
1413  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1414  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1415  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1416  case ExtractValue: return ISD::MERGE_VALUES;
1417  case InsertValue: return ISD::MERGE_VALUES;
1418  case LandingPad: return 0;
1419  }
1420 
1421  llvm_unreachable("Unknown instruction type encountered!");
1422 }
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
ExtractElement
static ConstantInt * ExtractElement(Constant *V, Constant *Idx)
Definition: InstCombineCompares.cpp:33
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::ISD::FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:227
llvm::APIntOps::Or
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1870
llvm::APIntOps::Xor
APInt Xor(const APInt &LHS, const APInt &RHS)
Bitwise XOR function for APInt.
Definition: APInt.h:1875
llvm::ISD::FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::APIntOps::And
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1865
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
bool llvm::TargetLoweringBase::isBigEndian ( ) const
inlineinherited

Definition at line 153 of file TargetLowering.h.

153 { return !IsLittleEndian; }
llvm::TargetLoweringBase::IsLittleEndian
bool IsLittleEndian
True if this is a little endian target.
Definition: TargetLowering.h:1457
bool llvm::X86TargetLowering::IsCalleePop ( bool  isVarArg,
CallingConv::ID  CallConv 
) const
private
bool llvm::TargetLoweringBase::isCondCodeLegal ( ISD::CondCode  CC,
MVT  VT 
) const
inlineinherited

Return true if the specified condition code is legal on this target.

Definition at line 602 of file TargetLowering.h.

602  {
603  return
604  getCondCodeAction(CC, VT) == Legal ||
605  getCondCodeAction(CC, VT) == Custom;
606  }
llvm::TargetLoweringBase::getCondCodeAction
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Definition: TargetLowering.h:589
bool TargetLowering::isConstFalseVal ( const SDNode *  N) const
inherited

Return if the N is a constant or constant vector equal to the false value from getBooleanContents().

Definition at line 1179 of file TargetLowering.cpp.

1179  {
1180  if (!N)
1181  return false;
1182 
1183  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1184  if (!CN) {
1185  const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1186  if (!BV)
1187  return false;
1188 
1189  BitVector UndefElements;
1190  CN = BV->getConstantSplatNode(&UndefElements);
1191  // Only interested in constant splats, and we don't try to handle undef
1192  // elements in identifying boolean constants.
1193  if (!CN || UndefElements.none())
1194  return false;
1195  }
1196 
1197  if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
1198  return !CN->getAPIntValue()[0];
1199 
1200  return CN->isNullValue();
1201 }
llvm::BitVector::none
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:152
llvm::BuildVectorSDNode::getConstantSplatNode
ConstantSDNode * getConstantSplatNode(BitVector *UndefElements=nullptr) const
Returns the splatted constant or null if this is not a constant splat.
Definition: SelectionDAG.cpp:6760
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Definition: SelectionDAGNodes.h:648
llvm::ConstantSDNode::getAPIntValue
const APInt & getAPIntValue() const
Definition: SelectionDAGNodes.h:1349
llvm::TargetLoweringBase::getBooleanContents
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
Definition: TargetLowering.h:290
llvm::dyn_cast
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
N
#define N
bool TargetLowering::isConstTrueVal ( const SDNode *  N) const
inherited

Return if the N is a constant or constant vector equal to the true value from getBooleanContents().

Definition at line 1149 of file TargetLowering.cpp.

1149  {
1150  if (!N)
1151  return false;
1152 
1153  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1154  if (!CN) {
1155  const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1156  if (!BV)
1157  return false;
1158 
1159  BitVector UndefElements;
1160  CN = BV->getConstantSplatNode(&UndefElements);
1161  // Only interested in constant splats, and we don't try to handle undef
1162  // elements in identifying boolean constants.
1163  if (!CN || UndefElements.none())
1164  return false;
1165  }
1166 
1167  switch (getBooleanContents(N->getValueType(0))) {
1168  case UndefinedBooleanContent:
1169  return CN->getAPIntValue()[0];
1170  case ZeroOrOneBooleanContent:
1171  return CN->isOne();
1172  case ZeroOrNegativeOneBooleanContent:
1173  return CN->isAllOnesValue();
1174  }
1175 
1176  llvm_unreachable("Invalid boolean contents");
1177 }
llvm::BitVector::none
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:152
llvm::BuildVectorSDNode::getConstantSplatNode
ConstantSDNode * getConstantSplatNode(BitVector *UndefElements=nullptr) const
Returns the splatted constant or null if this is not a constant splat.
Definition: SelectionDAG.cpp:6760
llvm::ConstantSDNode::isAllOnesValue
bool isAllOnesValue() const
Definition: SelectionDAGNodes.h:1355
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Definition: SelectionDAGNodes.h:648
llvm::ConstantSDNode::getAPIntValue
const APInt & getAPIntValue() const
Definition: SelectionDAGNodes.h:1349
llvm::TargetLoweringBase::getBooleanContents
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
Definition: TargetLowering.h:290
llvm::dyn_cast
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
N
#define N
virtual bool llvm::TargetLowering::isDesirableToCommuteWithShift ( const SDNode *  N) const
inlinevirtualinherited

Return true if it is profitable to move a following shift through this.

Reimplemented in llvm::AArch64TargetLowering.

Definition at line 2060 of file TargetLowering.h.

2060  {
2061  return true;
2062  }
bool X86TargetLowering::IsDesirableToPromoteOp ( SDValue  Op,
EVT &  PVT 
) const
overridevirtual

isTypeDesirable - Return true if the target has native support for the specified value type and it is 'desirable' to use the type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.

IsDesirableToPromoteOp - This method query the target whether it is beneficial for dag combiner to promote the specified node. If true, it should return the desired promotion type by reference.

Reimplemented from llvm::TargetLowering.

Definition at line 22161 of file X86ISelLowering.cpp.

22161  {
22162  EVT VT = Op.getValueType();
22163  if (VT != MVT::i16)
22164  return false;
22165 
22166  bool Promote = false;
22167  bool Commute = false;
22168  switch (Op.getOpcode()) {
22169  default: break;
22170  case ISD::LOAD: {
22171  LoadSDNode *LD = cast<LoadSDNode>(Op);
22172  // If the non-extending load has a single use and it's not live out, then it
22173  // might be folded.
22174  if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
22175  Op.hasOneUse()*/) {
22176  for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
22177  UE = Op.getNode()->use_end(); UI != UE; ++UI) {
22178  // The only case where we'd want to promote LOAD (rather then it being
22179  // promoted as an operand is when it's only use is liveout.
22180  if (UI->getOpcode() != ISD::CopyToReg)
22181  return false;
22182  }
22183  }
22184  Promote = true;
22185  break;
22186  }
22187  case ISD::SIGN_EXTEND:
22188  case ISD::ZERO_EXTEND:
22189  case ISD::ANY_EXTEND:
22190  Promote = true;
22191  break;
22192  case ISD::SHL:
22193  case ISD::SRL: {
22194  SDValue N0 = Op.getOperand(0);
22195  // Look out for (store (shl (load), x)).
22196  if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
22197  return false;
22198  Promote = true;
22199  break;
22200  }
22201  case ISD::ADD:
22202  case ISD::MUL:
22203  case ISD::AND:
22204  case ISD::OR:
22205  case ISD::XOR:
22206  Commute = true;
22207  // fallthrough
22208  case ISD::SUB: {
22209  SDValue N0 = Op.getOperand(0);
22210  SDValue N1 = Op.getOperand(1);
22211  if (!Commute && MayFoldLoad(N1))
22212  return false;
22213  // Avoid disabling potential load folding opportunities.
22214  if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
22215  return false;
22216  if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
22217  return false;
22218  Promote = true;
22219  }
22220  }
22221 
22222  PVT = MVT::i32;
22223  return Promote;
22224 }
MayFoldLoad
static bool MayFoldLoad(SDValue Op)
Definition: X86ISelLowering.cpp:3370
MayFoldIntoStore
static bool MayFoldIntoStore(SDValue Op)
Definition: X86ISelLowering.cpp:3374
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::SDNode::use_iterator
Definition: SelectionDAGNodes.h:471
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::SDNode::use_begin
use_iterator use_begin() const
Definition: SelectionDAGNodes.h:528
llvm::LoadSDNode::getExtensionType
ISD::LoadExtType getExtensionType() const
Definition: SelectionDAGNodes.h:1854
llvm::SDNode::use_end
static use_iterator use_end()
Definition: SelectionDAGNodes.h:532
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
virtual bool llvm::TargetLowering::isDesirableToTransformToIntegerOp ( unsigned  ,
EVT   
) const
inlinevirtualinherited

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode to a equivalent op of an integer type. e.g. f32 load -> i32 load can be profitable on ARM.

Reimplemented in llvm::ARMTargetLowering.

Definition at line 2076 of file TargetLowering.h.

2077  {
2078  return false;
2079  }
bool X86TargetLowering::IsEligibleForTailCallOptimization ( SDValue  Callee,
CallingConv::ID  CalleeCC,
bool  isVarArg,
bool  isCalleeStructRet,
bool  isCallerStructRet,
Type *  RetTy,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
const SmallVectorImpl< SDValue > &  OutVals,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SelectionDAG &  DAG 
) const
private

IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization. Targets which want to do tail call optimization should implement this function.

Definition at line 3158 of file X86ISelLowering.cpp.

3167  {
3168  if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3169  return false;
3170 
3171  // If -tailcallopt is specified, make fastcc functions tail-callable.
3172  const MachineFunction &MF = DAG.getMachineFunction();
3173  const Function *CallerF = MF.getFunction();
3174 
3175  // If the function return type is x86_fp80 and the callee return type is not,
3176  // then the FP_EXTEND of the call result is not a nop. It's not safe to
3177  // perform a tailcall optimization here.
3178  if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3179  return false;
3180 
3181  CallingConv::ID CallerCC = CallerF->getCallingConv();
3182  bool CCMatch = CallerCC == CalleeCC;
3183  bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3184  bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3185 
3186  if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3187  if (IsTailCallConvention(CalleeCC) && CCMatch)
3188  return true;
3189  return false;
3190  }
3191 
3192  // Look for obvious safe cases to perform tail call optimization that do not
3193  // require ABI changes. This is what gcc calls sibcall.
3194 
3195  // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3196  // emit a special epilogue.
3197  const X86RegisterInfo *RegInfo =
3198  static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
3199  if (RegInfo->needsStackRealignment(MF))
3200  return false;
3201 
3202  // Also avoid sibcall optimization if either caller or callee uses struct
3203  // return semantics.
3204  if (isCalleeStructRet || isCallerStructRet)
3205  return false;
3206 
3207  // An stdcall/thiscall caller is expected to clean up its arguments; the
3208  // callee isn't going to do that.
3209  // FIXME: this is more restrictive than needed. We could produce a tailcall
3210  // when the stack adjustment matches. For example, with a thiscall that takes
3211  // only one argument.
3212  if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3213  CallerCC == CallingConv::X86_ThisCall))
3214  return false;
3215 
3216  // Do not sibcall optimize vararg calls unless all arguments are passed via
3217  // registers.
3218  if (isVarArg && !Outs.empty()) {
3219 
3220  // Optimizing for varargs on Win64 is unlikely to be safe without
3221  // additional testing.
3222  if (IsCalleeWin64 || IsCallerWin64)
3223  return false;
3224 
3225  SmallVector<CCValAssign, 16> ArgLocs;
3226  CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3227  DAG.getTarget(), ArgLocs, *DAG.getContext());
3228 
3229  CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3230  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3231  if (!ArgLocs[i].isRegLoc())
3232  return false;
3233  }
3234 
3235  // If the call result is in ST0 / ST1, it needs to be popped off the x87
3236  // stack. Therefore, if it's not used by the call it is not safe to optimize
3237  // this into a sibcall.
3238  bool Unused = false;
3239  for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3240  if (!Ins[i].Used) {
3241  Unused = true;
3242  break;
3243  }
3244  }
3245  if (Unused) {
3246  SmallVector<CCValAssign, 16> RVLocs;
3247  CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3248  DAG.getTarget(), RVLocs, *DAG.getContext());
3249  CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3250  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3251  CCValAssign &VA = RVLocs[i];
3252  if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3253  return false;
3254  }
3255  }
3256 
3257  // If the calling conventions do not match, then we'd better make sure the
3258  // results are returned in the same way as what the caller expects.
3259  if (!CCMatch) {
3260  SmallVector<CCValAssign, 16> RVLocs1;
3261  CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3262  DAG.getTarget(), RVLocs1, *DAG.getContext());
3263  CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3264 
3265  SmallVector<CCValAssign, 16> RVLocs2;
3266  CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3267  DAG.getTarget(), RVLocs2, *DAG.getContext());
3268  CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3269 
3270  if (RVLocs1.size() != RVLocs2.size())
3271  return false;
3272  for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3273  if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3274  return false;
3275  if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3276  return false;
3277  if (RVLocs1[i].isRegLoc()) {
3278  if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3279  return false;
3280  } else {
3281  if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3282  return false;
3283  }
3284  }
3285  }
3286 
3287  // If the callee takes no arguments then go on to check the results of the
3288  // call.
3289  if (!Outs.empty()) {
3290  // Check if stack adjustment is needed. For now, do not do this if any
3291  // argument is passed on the stack.
3292  SmallVector<CCValAssign, 16> ArgLocs;
3293  CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3294  DAG.getTarget(), ArgLocs, *DAG.getContext());
3295 
3296  // Allocate shadow area for Win64
3297  if (IsCalleeWin64)
3298  CCInfo.AllocateStack(32, 8);
3299 
3300  CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3301  if (CCInfo.getNextStackOffset()) {
3302  MachineFunction &MF = DAG.getMachineFunction();
3303  if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3304  return false;
3305 
3306  // Check if the arguments are already laid out in the right way as
3307  // the caller's fixed stack objects.
3308  MachineFrameInfo *MFI = MF.getFrameInfo();
3309  const MachineRegisterInfo *MRI = &MF.getRegInfo();
3310  const X86InstrInfo *TII =
3311  static_cast<const X86InstrInfo *>(DAG.getTarget().getInstrInfo());
3312  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3313  CCValAssign &VA = ArgLocs[i];
3314  SDValue Arg = OutVals[i];
3315  ISD::ArgFlagsTy Flags = Outs[i].Flags;
3316  if (VA.getLocInfo() == CCValAssign::Indirect)
3317  return false;
3318  if (!VA.isRegLoc()) {
3319  if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3320  MFI, MRI, TII))
3321  return false;
3322  }
3323  }
3324  }
3325 
3326  // If the tailcall address may be in a register, then make sure it's
3327  // possible to register allocate for it. In 32-bit, the call address can
3328  // only target EAX, EDX, or ECX since the tail call must be scheduled after
3329  // callee-saved registers are restored. These happen to be the same
3330  // registers used to pass 'inreg' arguments so watch out for those.
3331  if (!Subtarget->is64Bit() &&
3332  ((!isa<GlobalAddressSDNode>(Callee) &&
3333  !isa<ExternalSymbolSDNode>(Callee)) ||
3334  DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3335  unsigned NumInRegs = 0;
3336  // In PIC we need an extra register to formulate the address computation
3337  // for the callee.
3338  unsigned MaxInRegs =
3339  (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3340 
3341  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3342  CCValAssign &VA = ArgLocs[i];
3343  if (!VA.isRegLoc())
3344  continue;
3345  unsigned Reg = VA.getLocReg();
3346  switch (Reg) {
3347  default: break;
3348  case X86::EAX: case X86::EDX: case X86::ECX:
3349  if (++NumInRegs == MaxInRegs)
3350  return false;
3351  break;
3352  }
3353  }
3354  }
3355  }
3356 
3357  return true;
3358 }
llvm::CCState::AnalyzeCallResult
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
Definition: CallingConvLower.cpp:155
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Definition: TargetMachine.cpp:76
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:144
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::Function::getReturnType
Type * getReturnType() const
Definition: Function.cpp:214
llvm::MachineFunction::getFunction
const Function * getFunction() const
Definition: MachineFunction.h:151
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:135
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
Definition: Function.h:161
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:114
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:429
llvm::MachineFrameInfo
Abstract Stack Frame Information.
Definition: MachineFrameInfo.h:80
llvm::CallingConv::ID
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
llvm::CCValAssign::getLocReg
unsigned getLocReg() const
Definition: CallingConvLower.h:140
llvm::SmallVectorBase::empty
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
IsTailCallConvention
static bool IsTailCallConvention(CallingConv::ID CC)
Definition: X86ISelLowering.cpp:2172
llvm::X86Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:431
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
Definition: TargetOptions.h:148
llvm::TargetMachine::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: Target/TargetMachine.h:118
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
MatchingStackOffset
static bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, const X86InstrInfo *TII)
Definition: X86ISelLowering.cpp:3104
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
llvm::CCState::AnalyzeCallOperands
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
Definition: CallingConvLower.cpp:118
llvm::Type::isX86_FP80Ty
bool isX86_FP80Ty() const
isX86_FP80Ty - Return true if this is x86 long double.
Definition: Type.h:149
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
Definition: MachineFunction.h:167
IsCCallConvention
static bool IsCCallConvention(CallingConv::ID CC)
Return true if the calling convention is a C calling convention.
Definition: X86ISelLowering.cpp:2178
llvm::X86RegisterInfo::needsStackRealignment
bool needsStackRealignment(const MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:441
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:141
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, unsigned Align)
Definition: CallingConvLower.h:379
virtual bool llvm::TargetLoweringBase::isFAbsFree ( EVT  VT) const
inlinevirtualinherited

Return true if an fabs operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 1382 of file TargetLowering.h.

1382  {
1383  assert(VT.isFloatingPoint());
1384  return false;
1385  }
assert
assert(Globals.size() > 1)
bool X86TargetLowering::isFMAFasterThanFMulAndFAdd ( EVT  VT) const
overridevirtual

isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd instructions. fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16830 of file X86ISelLowering.cpp.

16830  {
16831  if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
16832  return false;
16833 
16834  VT = VT.getScalarType();
16835 
16836  if (!VT.isSimple())
16837  return false;
16838 
16839  switch (VT.getSimpleVT().SimpleTy) {
16840  case MVT::f32:
16841  case MVT::f64:
16842  return true;
16843  default:
16844  break;
16845  }
16846 
16847  return false;
16848 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86Subtarget::hasFMA4
bool hasFMA4() const
Definition: X86Subtarget.h:330
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:156
llvm::EVT::getScalarType
EVT getScalarType() const
Definition: ValueTypes.h:211
llvm::EVT::isSimple
bool isSimple() const
Definition: ValueTypes.h:95
llvm::X86Subtarget::hasFMA
bool hasFMA() const
Definition: X86Subtarget.h:328
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Definition: ValueTypes.h:204
virtual bool llvm::TargetLoweringBase::isFNegFree ( EVT  VT) const
inlinevirtualinherited

Return true if an fneg operation is free to the point where it is never worthwhile to replace it with a bitwise operation.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 1375 of file TargetLowering.h.

1375  {
1376  assert(VT.isFloatingPoint());
1377  return false;
1378  }
assert
assert(Globals.size() > 1)
bool X86TargetLowering::isFPImmLegal ( const APFloat &  Imm,
EVT  VT 
) const
overridevirtual

isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively. If false, the legalizer will materialize the FP immediate as a load from a constant pool.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 3662 of file X86ISelLowering.cpp.

3662  {
3663  for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3664  if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3665  return true;
3666  }
3667  return false;
3668 }
llvm::APFloat::bitwiseIsEqual
bool bitwiseIsEqual(const APFloat &) const
Bitwise comparison for equality (QNaNs compare equal, 0!=-0).
Definition: APFloat.cpp:769
llvm::X86TargetLowering::LegalFPImmediates
std::vector< APFloat > LegalFPImmediates
LegalFPImmediates - A list of legal fp immediates.
Definition: X86ISelLowering.h:824
bool X86TargetLowering::isGAPlusOffset ( SDNode *  N,
const GlobalValue *&  GA,
int64_t &  Offset 
) const
overridevirtual

isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.

Reimplemented from llvm::TargetLowering.

Definition at line 18324 of file X86ISelLowering.cpp.

18326  {
18327  if (N->getOpcode() == X86ISD::Wrapper) {
18328  if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
18329  GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
18330  Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
18331  return true;
18332  }
18333  }
18334  return TargetLowering::isGAPlusOffset(N, GA, Offset);
18335 }
llvm::SDNode::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:401
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:592
llvm::TargetLowering::isGAPlusOffset
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Definition: TargetLowering.cpp:2005
llvm::getOffset
static std::error_code getOffset(const SymbolRef &Sym, uint64_t &Result)
Definition: RuntimeDyld.cpp:76
bool llvm::TargetLoweringBase::isIndexedLoadLegal ( unsigned  IdxMode,
EVT  VT 
) const
inlineinherited

Return true if the specified indexed load is legal on this target.

Definition at line 561 of file TargetLowering.h.

561  {
562  return VT.isSimple() &&
563  (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
564  getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
565  }
llvm::TargetLoweringBase::getIndexedLoadAction
LegalizeAction getIndexedLoadAction(unsigned IdxMode, MVT VT) const
Definition: TargetLowering.h:553
bool llvm::TargetLoweringBase::isIndexedStoreLegal ( unsigned  IdxMode,
EVT  VT 
) const
inlineinherited

Return true if the specified indexed load is legal on this target.

Definition at line 579 of file TargetLowering.h.

579  {
580  return VT.isSimple() &&
581  (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
582  getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
583  }
llvm::TargetLoweringBase::getIndexedStoreAction
LegalizeAction getIndexedStoreAction(unsigned IdxMode, MVT VT) const
Definition: TargetLowering.h:571
bool TargetLowering::isInTailCallPosition ( SelectionDAG &  DAG,
SDNode *  Node,
SDValue &  Chain 
) const
inherited

Check whether a given call node is in tail position within its function. If so, it sets Chain to the input chain of the tail call.

Definition at line 48 of file TargetLowering.cpp.

49  {
50  const Function *F = DAG.getMachineFunction().getFunction();
51 
52  // Conservatively require the attributes of the call to match those of
53  // the return. Ignore noalias because it doesn't affect the call sequence.
54  AttributeSet CallerAttrs = F->getAttributes();
55  if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56  .removeAttribute(Attribute::NoAlias).hasAttributes())
57  return false;
58 
59  // It's not safe to eliminate the sign / zero extension of the return value.
60  if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
61  CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
62  return false;
63 
64  // Check if the only use is a function return node.
65  return isUsedByReturnOnly(Node, Chain);
66 }
llvm::Attribute::SExt
Sign extended before/after call.
Definition: Attributes.h:101
F
F(f)
llvm::MachineFunction::getFunction
const Function * getFunction() const
Definition: MachineFunction.h:151
llvm::AttributeSet::hasAttribute
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::TargetLowering::isUsedByReturnOnly
virtual bool isUsedByReturnOnly(SDNode *, SDValue &) const
Definition: TargetLowering.h:2297
llvm::Attribute::NoAlias
Considered to not alias after call.
Definition: Attributes.h:82
llvm::Attribute::ZExt
Zero extended before/after call.
Definition: Attributes.h:114
llvm::Function::getAttributes
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
bool llvm::TargetLoweringBase::isIntDivCheap ( ) const
inlineinherited

Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target.

Definition at line 215 of file TargetLowering.h.

215 { return IntDivIsCheap; }
bool llvm::X86TargetLowering::isIntegerTypeFTOL ( EVT  VT) const
inline

isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be used for fptoui to the given type.

Definition at line 763 of file X86ISelLowering.h.

763  {
764  return isTargetFTOL() && VT == MVT::i64;
765  }
bool llvm::TargetLoweringBase::isJumpExpensive ( ) const
inlineinherited

Return true if Flow Control is an expensive operation that should be avoided.

Definition at line 231 of file TargetLowering.h.

231 { return JumpIsExpensive; }
bool X86TargetLowering::isLegalAddImmediate ( int64_t  Imm) const
overridevirtual

isLegalAddImmediate - Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16782 of file X86ISelLowering.cpp.

16782  {
16783  // Can also use sub to handle negated immediates.
16784  return isInt<32>(Imm);
16785 }
llvm::isInt< 32 >
bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:285
bool X86TargetLowering::isLegalAddressingMode ( const AddrMode &  AM,
Type *  Ty 
) const
overridevirtual

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16686 of file X86ISelLowering.cpp.

16687  {
16688  // X86 supports extremely general addressing modes.
16689  CodeModel::Model M = getTargetMachine().getCodeModel();
16690  Reloc::Model R = getTargetMachine().getRelocationModel();
16691 
16692  // X86 allows a sign-extended 32-bit immediate field as a displacement.
16693  if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
16694  return false;
16695 
16696  if (AM.BaseGV) {
16697  unsigned GVFlags =
16698  Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
16699 
16700  // If a reference to this global requires an extra load, we can't fold it.
16701  if (isGlobalStubReference(GVFlags))
16702  return false;
16703 
16704  // If BaseGV requires a register for the PIC base, we cannot also have a
16705  // BaseReg specified.
16706  if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
16707  return false;
16708 
16709  // If lower 4G is not available, then we must use rip-relative addressing.
16710  if ((M != CodeModel::Small || R != Reloc::Static) &&
16711  Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
16712  return false;
16713  }
16714 
16715  switch (AM.Scale) {
16716  case 0:
16717  case 1:
16718  case 2:
16719  case 4:
16720  case 8:
16721  // These scales always work.
16722  break;
16723  case 3:
16724  case 5:
16725  case 9:
16726  // These scales are formed with basereg+scalereg. Only accept if there is
16727  // no basereg yet.
16728  if (AM.HasBaseReg)
16729  return false;
16730  break;
16731  default: // Other stuff never works.
16732  return false;
16733  }
16734 
16735  return true;
16736 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Definition: TargetMachine.cpp:76
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:149
llvm::X86Subtarget::ClassifyGlobalReference
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
Definition: X86Subtarget.cpp:64
llvm::isGlobalStubReference
static bool isGlobalStubReference(unsigned char TargetFlag)
Definition: X86InstrInfo.h:85
llvm::isGlobalRelativeToPICBase
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
Definition: X86InstrInfo.h:102
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Definition: TargetMachine.cpp:84
llvm::X86::isOffsetSuitableForCodeModel
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement=true)
Definition: X86ISelLowering.cpp:3479
bool X86TargetLowering::isLegalICmpImmediate ( int64_t  Imm) const
overridevirtual

isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16778 of file X86ISelLowering.cpp.

16778  {
16779  return isInt<32>(Imm);
16780 }
llvm::isInt< 32 >
bool isInt< 32 >(int64_t x)
Definition: MathExtras.h:285
bool TargetLoweringBase::isLegalRC ( const TargetRegisterClass *  RC) const
protectedinherited

Return true if the value types that can be represented by the specified register class are all legal.

isLegalRC - Return true if the value types that can be represented by the specified register class are all legal.

Definition at line 934 of file TargetLoweringBase.cpp.

934  {
935  for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
936  I != E; ++I) {
937  if (isTypeLegal(*I))
938  return true;
939  }
940  return false;
941 }
llvm::TargetRegisterClass::vt_end
vt_iterator vt_end() const
Definition: TargetRegisterInfo.h:117
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
I
#define I(x, y, z)
Definition: MD5.cpp:54
llvm::TargetRegisterClass::vt_begin
vt_iterator vt_begin() const
Definition: TargetRegisterInfo.h:113
bool llvm::TargetLoweringBase::isLittleEndian ( ) const
inlineinherited

Definition at line 154 of file TargetLowering.h.

154 { return IsLittleEndian; }
llvm::TargetLoweringBase::IsLittleEndian
bool IsLittleEndian
True if this is a little endian target.
Definition: TargetLowering.h:1457
virtual bool llvm::TargetLoweringBase::isLoadBitCastBeneficial ( EVT  ,
EVT   
) const
inlinevirtualinherited

isLoadBitCastBeneficial() - Return true if the following transform is beneficial. fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.

Reimplemented in llvm::AMDGPUTargetLowering.

Definition at line 246 of file TargetLowering.h.

246  {
247  return true;
248  }
bool llvm::TargetLoweringBase::isLoadExtLegal ( unsigned  ExtType,
EVT  VT 
) const
inlineinherited

Return true if the specified load with extension is legal on this target.

Definition at line 527 of file TargetLowering.h.

527  {
528  return VT.isSimple() &&
529  getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
530  }
llvm::TargetLoweringBase::getLoadExtAction
LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const
Definition: TargetLowering.h:520
bool llvm::TargetLoweringBase::isMaskAndBranchFoldingLegal ( ) const
inlineinherited

Return if the target supports combining a chain like:

%andResult = and %val1, #imm-with-one-bit-set;
%icmpResult = icmp %andResult, 0
br i1 %icmpResult, label %dest1, label %dest2

into a single machine instruction of a form like:

brOnBitSet %register, #bitNumber, dest

Definition at line 261 of file TargetLowering.h.

261  {
262  return MaskAndBranchFoldingIsLegal;
263  }
bool X86TargetLowering::isNarrowingProfitable ( EVT  VT1,
EVT  VT2 
) const
overridevirtual

isNarrowingProfitable - Return true if it's profitable to narrow operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16850 of file X86ISelLowering.cpp.

16850  {
16851  // i16 instructions are longer (0x66 prefix) and potentially slower.
16852  return !(VT1 == MVT::i32 && VT2 == MVT::i16);
16853 }
bool X86TargetLowering::isNoopAddrSpaceCast ( unsigned  SrcAS,
unsigned  DestAS 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1851 of file X86ISelLowering.cpp.

1852  {
1853  assert(SrcAS != DestAS && "Expected different address spaces!");
1854 
1855  return SrcAS < 256 && DestAS < 256;
1856 }
assert
assert(Globals.size() > 1)
bool TargetLowering::isOffsetFoldingLegal ( const GlobalAddressSDNode *  GA) const
virtualinherited

Return true if folding a constant offset with the given GlobalAddress is legal. It is frequently not legal in PIC relocation models.

Reimplemented in llvm::MipsTargetLowering, llvm::PPCTargetLowering, llvm::ARMTargetLowering, llvm::AArch64TargetLowering, and llvm::SparcTargetLowering.

Definition at line 258 of file TargetLowering.cpp.

258  {
259  // Assume that everything is safe in static mode.
260  if (getTargetMachine().getRelocationModel() == Reloc::Static)
261  return true;
262 
263  // In dynamic-no-pic mode, assume that known defined values are safe.
264  if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
265  GA &&
266  !GA->getGlobal()->isDeclaration() &&
267  !GA->getGlobal()->isWeakForLinker())
268  return true;
269 
270  // Otherwise assume nothing is safe.
271  return false;
272 }
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:149
llvm::GlobalAddressSDNode::getGlobal
const GlobalValue * getGlobal() const
Definition: SelectionDAGNodes.h:1418
llvm::GlobalValue::isWeakForLinker
static bool isWeakForLinker(LinkageTypes Linkage)
Definition: GlobalValue.h:235
llvm::GlobalValue::isDeclaration
bool isDeclaration() const
Definition: Globals.cpp:113
bool llvm::TargetLoweringBase::isOperationExpand ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is illegal on this target or unlikely to be made legal with custom lowering. This is used to help guide high-level lowering decisions.

Definition at line 507 of file TargetLowering.h.

507  {
508  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
509  }
llvm::TargetLoweringBase::getOperationAction
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Definition: TargetLowering.h:477
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
bool llvm::TargetLoweringBase::isOperationLegal ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is legal on this target.

Definition at line 512 of file TargetLowering.h.

512  {
513  return (VT == MVT::Other || isTypeLegal(VT)) &&
514  getOperationAction(Op, VT) == Legal;
515  }
llvm::TargetLoweringBase::getOperationAction
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Definition: TargetLowering.h:477
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
bool llvm::TargetLoweringBase::isOperationLegalOrCustom ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is legal on this target or can be made legal with custom lowering. This is used to help guide high-level lowering decisions.

Definition at line 489 of file TargetLowering.h.

489  {
490  return (VT == MVT::Other || isTypeLegal(VT)) &&
491  (getOperationAction(Op, VT) == Legal ||
492  getOperationAction(Op, VT) == Custom);
493  }
llvm::TargetLoweringBase::getOperationAction
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Definition: TargetLowering.h:477
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
bool llvm::TargetLoweringBase::isOperationLegalOrPromote ( unsigned  Op,
EVT  VT 
) const
inlineinherited

Return true if the specified operation is legal on this target or can be made legal using promotion. This is used to help guide high-level lowering decisions.

Definition at line 498 of file TargetLowering.h.

498  {
499  return (VT == MVT::Other || isTypeLegal(VT)) &&
500  (getOperationAction(Op, VT) == Legal ||
501  getOperationAction(Op, VT) == Promote);
502  }
llvm::TargetLoweringBase::getOperationAction
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Definition: TargetLowering.h:477
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
bool llvm::TargetLoweringBase::isPow2DivCheap ( ) const
inlineinherited

Return true if pow2 div is cheaper than a chain of srl/add/sra.

Definition at line 227 of file TargetLowering.h.

227 { return Pow2DivIsCheap; }
bool llvm::TargetLoweringBase::isPredictableSelectExpensive ( ) const
inlineinherited

Return true if selects are only cheaper than branches if the branch is unlikely to be predicted right.

Definition at line 235 of file TargetLowering.h.

235  {
236  return PredictableSelectIsExpensive;
237  }
bool X86TargetLowering::isSafeMemOpType ( MVT  VT) const
overridevirtual

isSafeMemOpType - Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 1736 of file X86ISelLowering.cpp.

1736  {
1737  if (VT == MVT::f32)
1738  return X86ScalarSSEf32;
1739  else if (VT == MVT::f64)
1740  return X86ScalarSSEf64;
1741  return true;
1742 }
bool llvm::X86TargetLowering::isScalarFPTypeInSSEReg ( EVT  VT) const
inline

isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating point stack.

Definition at line 752 of file X86ISelLowering.h.

752  {
753  return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
754  (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1
755  }
bool llvm::TargetLoweringBase::isSelectExpensive ( ) const
inlineinherited

Return true if the select operation is expensive for this target.

Definition at line 174 of file TargetLowering.h.

174 { return SelectIsExpensive; }
virtual bool llvm::TargetLoweringBase::isSelectSupported ( SelectSupportKind  ) const
inlinevirtualinherited

Reimplemented in llvm::ARMTargetLowering, and llvm::AMDGPUTargetLowering.

Definition at line 176 of file TargetLowering.h.

176  {
177  return true;
178  }
bool X86TargetLowering::isShuffleMaskLegal ( const SmallVectorImpl< int > &  M,
EVT  VT 
) const
overridevirtual

isShuffleMaskLegal - Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16860 of file X86ISelLowering.cpp.

16861  {
16862  if (!VT.isSimple())
16863  return false;
16864 
16865  MVT SVT = VT.getSimpleVT();
16866 
16867  // Very little shuffling can be done for 64-bit vectors right now.
16868  if (VT.getSizeInBits() == 64)
16869  return false;
16870 
16871  // If this is a single-input shuffle with no 128 bit lane crossings we can
16872  // lower it into pshufb.
16873  if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
16874  (SVT.is256BitVector() && Subtarget->hasInt256())) {
16875  bool isLegal = true;
16876  for (unsigned I = 0, E = M.size(); I != E; ++I) {
16877  if (M[I] >= (int)SVT.getVectorNumElements() ||
16878  ShuffleCrosses128bitLane(SVT, I, M[I])) {
16879  isLegal = false;
16880  break;
16881  }
16882  }
16883  if (isLegal)
16884  return true;
16885  }
16886 
16887  // FIXME: blends, shifts.
16888  return (SVT.getVectorNumElements() == 2 ||
16889  ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
16890  isMOVLMask(M, SVT) ||
16891  isMOVHLPSMask(M, SVT) ||
16892  isSHUFPMask(M, SVT) ||
16893  isPSHUFDMask(M, SVT) ||
16894  isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
16895  isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
16896  isPALIGNRMask(M, SVT, Subtarget) ||
16897  isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
16898  isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
16899  isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
16900  isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
16901  isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
16902 }
isPSHUFDMask
static bool isPSHUFDMask(ArrayRef< int > Mask, MVT VT)
Definition: X86ISelLowering.cpp:3708
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
isPSHUFHWMask
static bool isPSHUFHWMask(ArrayRef< int > Mask, MVT VT, bool HasInt256)
Definition: X86ISelLowering.cpp:3718
isMOVHLPSMask
static bool isMOVHLPSMask(ArrayRef< int > Mask, MVT VT)
Definition: X86ISelLowering.cpp:3925
ShuffleCrosses128bitLane
static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx, unsigned OutputIdx)
Definition: X86ISelLowering.cpp:8086
llvm::X86Subtarget::hasSSE41
bool hasSSE41() const
Definition: X86Subtarget.h:315
isUNPCKL_v_undef_Mask
static bool isUNPCKL_v_undef_Mask(ArrayRef< int > Mask, MVT VT, bool HasInt256)
Definition: X86ISelLowering.cpp:4179
isBlendMask
static bool isBlendMask(ArrayRef< int > MaskVals, MVT VT, bool hasSSE41, bool hasInt256, unsigned *MaskOut=nullptr)
Definition: X86ISelLowering.cpp:8009
isMOVLMask
static bool isMOVLMask(ArrayRef< int > Mask, EVT VT)
Definition: X86ISelLowering.cpp:4279
llvm::X86Subtarget::hasSSSE3
bool hasSSSE3() const
Definition: X86Subtarget.h:314
isSHUFPMask
static bool isSHUFPMask(ArrayRef< int > Mask, MVT VT, bool Commuted=false)
Definition: X86ISelLowering.cpp:3866
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:312
isUNPCKLMask
static bool isUNPCKLMask(ArrayRef< int > Mask, MVT VT, bool HasInt256, bool V2IsSplat=false)
Definition: X86ISelLowering.cpp:4083
llvm::MVT::is128BitVector
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
Definition: MachineValueType.h:210
llvm::X86Subtarget::hasInt256
bool hasInt256() const
Definition: X86Subtarget.h:321
isUNPCKH_v_undef_Mask
static bool isUNPCKH_v_undef_Mask(ArrayRef< int > Mask, MVT VT, bool HasInt256)
Definition: X86ISelLowering.cpp:4222
llvm::MVT::is256BitVector
bool is256BitVector() const
is256BitVector - Return true if this is a 256-bit vector type.
Definition: MachineValueType.h:217
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
I
#define I(x, y, z)
Definition: MD5.cpp:54
isUNPCKHMask
static bool isUNPCKHMask(ArrayRef< int > Mask, MVT VT, bool HasInt256, bool V2IsSplat=false)
Definition: X86ISelLowering.cpp:4131
llvm::EVT::isSimple
bool isSimple() const
Definition: ValueTypes.h:95
isPALIGNRMask
static bool isPALIGNRMask(ArrayRef< int > Mask, MVT VT, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:3776
isPSHUFLWMask
static bool isPSHUFLWMask(ArrayRef< int > Mask, MVT VT, bool HasInt256)
Definition: X86ISelLowering.cpp:3747
llvm::ShuffleVectorSDNode::isSplatMask
static bool isSplatMask(const int *Mask, EVT VT)
Definition: SelectionDAG.cpp:6780
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Definition: ValueTypes.h:204
bool llvm::TargetLoweringBase::isSlowDivBypassed ( ) const
inlineinherited

Returns true if target has indicated at least one type should be bypassed.

Definition at line 218 of file TargetLowering.h.

218 { return !BypassSlowDivWidths.empty(); }
llvm::TargetLoweringBase::BypassSlowDivWidths
DenseMap< unsigned int, unsigned int > BypassSlowDivWidths
Definition: TargetLowering.h:1486
llvm::DenseMapBase::empty
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: DenseMap.h:68
bool X86TargetLowering::isTargetFTOL ( ) const

isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine for fptoui.

Definition at line 22908 of file X86ISelLowering.cpp.

22908  {
22909  return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();
22910 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86Subtarget::isTargetKnownWindowsMSVC
bool isTargetKnownWindowsMSVC() const
Definition: X86Subtarget.h:391
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
bool X86TargetLowering::isTruncateFree ( Type *  Ty1,
Type *  Ty2 
) const
overridevirtual

isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16756 of file X86ISelLowering.cpp.

16756  {
16757  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
16758  return false;
16759  unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
16760  unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
16761  return NumBits1 > NumBits2;
16762 }
llvm::Type::isIntegerTy
bool isIntegerTy() const
Definition: Type.h:193
llvm::Type::getPrimitiveSizeInBits
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
bool X86TargetLowering::isTruncateFree ( EVT  VT1,
EVT  VT2 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16787 of file X86ISelLowering.cpp.

16787  {
16788  if (!VT1.isInteger() || !VT2.isInteger())
16789  return false;
16790  unsigned NumBits1 = VT1.getSizeInBits();
16791  unsigned NumBits2 = VT2.getSizeInBits();
16792  return NumBits1 > NumBits2;
16793 }
llvm::EVT::isInteger
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
bool llvm::TargetLoweringBase::isTruncStoreLegal ( EVT  ValVT,
EVT  MemVT 
) const
inlineinherited

Return true if the specified store with truncation is legal on this target.

Definition at line 544 of file TargetLowering.h.

544  {
545  return isTypeLegal(ValVT) && MemVT.isSimple() &&
546  getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
547  }
llvm::TargetLoweringBase::getTruncStoreAction
LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const
Definition: TargetLowering.h:535
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
bool X86TargetLowering::isTypeDesirableForOp ( unsigned  Opc,
EVT  VT 
) const
overridevirtual

isTypeDesirableForOp - Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.

Reimplemented from llvm::TargetLowering.

Definition at line 22133 of file X86ISelLowering.cpp.

22133  {
22134  if (!isTypeLegal(VT))
22135  return false;
22136  if (VT != MVT::i16)
22137  return true;
22138 
22139  switch (Opc) {
22140  default:
22141  return true;
22142  case ISD::LOAD:
22143  case ISD::SIGN_EXTEND:
22144  case ISD::ZERO_EXTEND:
22145  case ISD::ANY_EXTEND:
22146  case ISD::SHL:
22147  case ISD::SRL:
22148  case ISD::SUB:
22149  case ISD::ADD:
22150  case ISD::MUL:
22151  case ISD::AND:
22152  case ISD::OR:
22153  case ISD::XOR:
22154  return false;
22155  }
22156 }
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
bool llvm::TargetLoweringBase::isTypeLegal ( EVT  VT) const
inlineinherited

Return true if the target has native support for the specified value type. This means that it has a register that directly holds it without promotions or expansions.

Definition at line 341 of file TargetLowering.h.

341  {
342  assert(!VT.isSimple() ||
343  (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
344  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
345  }
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::RegClassForVT
const TargetRegisterClass * RegClassForVT[MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1569
bool X86TargetLowering::isUsedByReturnOnly ( SDNode *  N,
SDValue &  Chain 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2002 of file X86ISelLowering.cpp.

2002  {
2003  if (N->getNumValues() != 1)
2004  return false;
2005  if (!N->hasNUsesOfValue(1, 0))
2006  return false;
2007 
2008  SDValue TCChain = Chain;
2009  SDNode *Copy = *N->use_begin();
2010  if (Copy->getOpcode() == ISD::CopyToReg) {
2011  // If the copy has a glue operand, we conservatively assume it isn't safe to
2012  // perform a tail call.
2013  if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2014  return false;
2015  TCChain = Copy->getOperand(0);
2016  } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2017  return false;
2018 
2019  bool HasRet = false;
2020  for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2021  UI != UE; ++UI) {
2022  if (UI->getOpcode() != X86ISD::RET_FLAG)
2023  return false;
2024  HasRet = true;
2025  }
2026 
2027  if (!HasRet)
2028  return false;
2029 
2030  Chain = TCChain;
2031  return true;
2032 }
llvm::SDNode::hasNUsesOfValue
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const
Definition: SelectionDAG.cpp:6317
llvm::SDNode::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:401
llvm::SDNode::getNumOperands
unsigned getNumOperands() const
Definition: SelectionDAGNodes.h:586
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:592
llvm::TargetLoweringBase::getValueType
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
Definition: TargetLowering.h:638
llvm::SDNode::getNumValues
unsigned getNumValues() const
Definition: SelectionDAGNodes.h:644
llvm::SDNode::use_iterator
Definition: SelectionDAGNodes.h:471
llvm::SDNode::use_begin
use_iterator use_begin() const
Definition: SelectionDAGNodes.h:528
llvm::ISD::FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
llvm::SDNode::use_end
static use_iterator use_end()
Definition: SelectionDAGNodes.h:532
bool X86TargetLowering::isVectorClearMaskLegal ( const SmallVectorImpl< int > &  Mask,
EVT  VT 
) const
overridevirtual

isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is used by Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16905 of file X86ISelLowering.cpp.

16906  {
16907  if (!VT.isSimple())
16908  return false;
16909 
16910  MVT SVT = VT.getSimpleVT();
16911  unsigned NumElts = SVT.getVectorNumElements();
16912  // FIXME: This collection of masks seems suspect.
16913  if (NumElts == 2)
16914  return true;
16915  if (NumElts == 4 && SVT.is128BitVector()) {
16916  return (isMOVLMask(Mask, SVT) ||
16917  isCommutedMOVLMask(Mask, SVT, true) ||
16918  isSHUFPMask(Mask, SVT) ||
16919  isSHUFPMask(Mask, SVT, /* Commuted */ true));
16920  }
16921  return false;
16922 }
isMOVLMask
static bool isMOVLMask(ArrayRef< int > Mask, EVT VT)
Definition: X86ISelLowering.cpp:4279
isSHUFPMask
static bool isSHUFPMask(ArrayRef< int > Mask, MVT VT, bool Commuted=false)
Definition: X86ISelLowering.cpp:3866
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:312
llvm::MVT::is128BitVector
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
Definition: MachineValueType.h:210
llvm::EVT::isSimple
bool isSimple() const
Definition: ValueTypes.h:95
isCommutedMOVLMask
static bool isCommutedMOVLMask(ArrayRef< int > Mask, MVT VT, bool V2IsSplat=false, bool V2IsUndef=false)
Definition: X86ISelLowering.cpp:4433
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Definition: ValueTypes.h:204
bool X86TargetLowering::isVectorShiftByScalarCheap ( Type *  Ty) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16738 of file X86ISelLowering.cpp.

16738  {
16739  unsigned Bits = Ty->getScalarSizeInBits();
16740 
16741  // 8-bit shifts are always expensive, but versions with a scalar amount aren't
16742  // particularly cheaper than those without.
16743  if (Bits == 8)
16744  return false;
16745 
16746  // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
16747  // variable shifts just as cheap as scalar ones.
16748  if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
16749  return false;
16750 
16751  // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
16752  // fully general vector.
16753  return true;
16754 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
Definition: Type.cpp:135
llvm::X86Subtarget::hasInt256
bool hasInt256() const
Definition: X86Subtarget.h:321
bool X86TargetLowering::isZExtFree ( Type *  Ty1,
Type *  Ty2 
) const
overridevirtual

isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the value to Ty2 in the result register. This does not necessarily include registers defined in unknown ways, such as incoming arguments, or copies from unknown virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to truncate instructions. e.g. on x86-64, all instructions that define 32-bit values implicit zero-extend the result out to 64 bits.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16795 of file X86ISelLowering.cpp.

16795  {
16796  // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
16797  return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
16798 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::Type::isIntegerTy
bool isIntegerTy() const
Definition: Type.h:193
bool X86TargetLowering::isZExtFree ( EVT  VT1,
EVT  VT2 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16800 of file X86ISelLowering.cpp.

16800  {
16801  // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
16802  return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
16803 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
bool X86TargetLowering::isZExtFree ( SDValue  Val,
EVT  VT2 
) const
overridevirtual

Reimplemented from llvm::TargetLoweringBase.

Definition at line 16805 of file X86ISelLowering.cpp.

16805  {
16806  EVT VT1 = Val.getValueType();
16807  if (isZExtFree(VT1, VT2))
16808  return true;
16809 
16810  if (Val.getOpcode() != ISD::LOAD)
16811  return false;
16812 
16813  if (!VT1.isSimple() || !VT1.isInteger() ||
16814  !VT2.isSimple() || !VT2.isInteger())
16815  return false;
16816 
16817  switch (VT1.getSimpleVT().SimpleTy) {
16818  default: break;
16819  case MVT::i8:
16820  case MVT::i16:
16821  case MVT::i32:
16822  // X86 has 8, 16, and 32-bit zero-extending loads.
16823  return true;
16824  }
16825 
16826  return false;
16827 }
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:156
llvm::EVT::isInteger
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::EVT::isSimple
bool isSimple() const
Definition: ValueTypes.h:95
llvm::X86TargetLowering::isZExtFree
bool isZExtFree(Type *Ty1, Type *Ty2) const override
Definition: X86ISelLowering.cpp:16795
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Definition: ValueTypes.h:204
void X86TargetLowering::LowerAsmOperandForConstraint ( SDValue  Op,
std::string &  Constraint,
std::vector< SDValue > &  Ops,
SelectionDAG &  DAG 
) const
overridevirtual

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops. If hasMemory is true it means one of the asm constraint of the inline asm instruction being processed is 'm'.

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops.

Reimplemented from llvm::TargetLowering.

Definition at line 22512 of file X86ISelLowering.cpp.

22515  {
22516  SDValue Result;
22517 
22518  // Only support length 1 constraints for now.
22519  if (Constraint.length() > 1) return;
22520 
22521  char ConstraintLetter = Constraint[0];
22522  switch (ConstraintLetter) {
22523  default: break;
22524  case 'I':
22525  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22526  if (C->getZExtValue() <= 31) {
22527  Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22528  break;
22529  }
22530  }
22531  return;
22532  case 'J':
22533  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22534  if (C->getZExtValue() <= 63) {
22535  Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22536  break;
22537  }
22538  }
22539  return;
22540  case 'K':
22541  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22542  if (isInt<8>(C->getSExtValue())) {
22543  Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22544  break;
22545  }
22546  }
22547  return;
22548  case 'N':
22549  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22550  if (C->getZExtValue() <= 255) {
22551  Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22552  break;
22553  }
22554  }
22555  return;
22556  case 'e': {
22557  // 32-bit signed value
22558  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22559  if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
22560  C->getSExtValue())) {
22561  // Widen to 64 bits here to get it sign extended.
22562  Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
22563  break;
22564  }
22565  // FIXME gcc accepts some relocatable values here too, but only in certain
22566  // memory models; it's complicated.
22567  }
22568  return;
22569  }
22570  case 'Z': {
22571  // 32-bit unsigned value
22572  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22573  if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
22574  C->getZExtValue())) {
22575  Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22576  break;
22577  }
22578  }
22579  // FIXME gcc accepts some relocatable values here too, but only in certain
22580  // memory models; it's complicated.
22581  return;
22582  }
22583  case 'i': {
22584  // Literal immediates are always ok.
22585  if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
22586  // Widen to 64 bits here to get it sign extended.
22587  Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
22588  break;
22589  }
22590 
22591  // In any sort of PIC mode addresses need to be computed at runtime by
22592  // adding in a register or some sort of table lookup. These can't
22593  // be used as immediates.
22594  if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
22595  return;
22596 
22597  // If we are in non-pic codegen mode, we allow the address of a global (with
22598  // an optional displacement) to be used with 'i'.
22599  GlobalAddressSDNode *GA = nullptr;
22600  int64_t Offset = 0;
22601 
22602  // Match either (GA), (GA+C), (GA+C1+C2), etc.
22603  while (1) {
22604  if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
22605  Offset += GA->getOffset();
22606  break;
22607  } else if (Op.getOpcode() == ISD::ADD) {
22608  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
22609  Offset += C->getZExtValue();
22610  Op = Op.getOperand(0);
22611  continue;
22612  }
22613  } else if (Op.getOpcode() == ISD::SUB) {
22614  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
22615  Offset += -C->getZExtValue();
22616  Op = Op.getOperand(0);
22617  continue;
22618  }
22619  }
22620 
22621  // Otherwise, this isn't something we can handle, reject it.
22622  return;
22623  }
22624 
22625  const GlobalValue *GV = GA->getGlobal();
22626  // If we require an extra load to get this address, as in PIC mode, we
22627  // can't accept it.
22628  if (isGlobalStubReference(
22629  Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
22630  return;
22631 
22632  Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
22633  GA->getValueType(0), Offset);
22634  break;
22635  }
22636  }
22637 
22638  if (Result.getNode()) {
22639  Ops.push_back(Result);
22640  return;
22641  }
22642  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
22643 }
llvm::ConstantInt::isValueValidForType
static bool isValueValidForType(Type *Ty, uint64_t V)
Determine if the value is in range for the given type.
Definition: Constants.cpp:1197
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::GlobalAddressSDNode::getGlobal
const GlobalValue * getGlobal() const
Definition: SelectionDAGNodes.h:1418
llvm::X86Subtarget::ClassifyGlobalReference
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
Definition: X86Subtarget.cpp:64
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Definition: SelectionDAGNodes.h:648
llvm::isGlobalStubReference
static bool isGlobalStubReference(unsigned char TargetFlag)
Definition: X86InstrInfo.h:85
llvm::isInt< 8 >
bool isInt< 8 >(int64_t x)
Definition: MathExtras.h:277
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::X86Subtarget::isPICStyleStubPIC
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:419
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::X86Subtarget::isPICStyleGOT
bool isPICStyleGOT() const
Definition: X86Subtarget.h:416
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:406
llvm::Type::getInt32Ty
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:235
llvm::TargetLowering::LowerAsmOperandForConstraint
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Definition: TargetLowering.cpp:2101
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
SDValue X86TargetLowering::LowerBlockAddress ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 10258 of file X86ISelLowering.cpp.

10258  {
10259  // Create the TargetBlockAddressAddress node.
10260  unsigned char OpFlags =
10261  Subtarget->ClassifyBlockAddressReference();
10262  CodeModel::Model M = DAG.getTarget().getCodeModel();
10263  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10264  int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10265  SDLoc dl(Op);
10266  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10267  OpFlags);
10268 
10269  if (Subtarget->isPICStyleRIPRel() &&
10270  (M == CodeModel::Small || M == CodeModel::Kernel))
10271  Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10272  else
10273  Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10274 
10275  // With PIC, the address is actually $g + Offset.
10276  if (isGlobalRelativeToPICBase(OpFlags)) {
10277  Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10278  DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10279  Result);
10280  }
10281 
10282  return Result;
10283 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::isGlobalRelativeToPICBase
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
Definition: X86InstrInfo.h:102
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::X86Subtarget::isPICStyleRIPRel
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:417
llvm::X86Subtarget::ClassifyBlockAddressReference
unsigned char ClassifyBlockAddressReference() const
Definition: X86Subtarget.cpp:49
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Definition: TargetMachine.cpp:84
llvm::getOffset
static std::error_code getOffset(const SymbolRef &Sym, uint64_t &Result)
Definition: RuntimeDyld.cpp:76
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::SelectionDAG::getTargetBlockAddress
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:480
SDValue X86TargetLowering::LowerBRCOND ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 12840 of file X86ISelLowering.cpp.

12840  {
12841  bool addTest = true;
12842  SDValue Chain = Op.getOperand(0);
12843  SDValue Cond = Op.getOperand(1);
12844  SDValue Dest = Op.getOperand(2);
12845  SDLoc dl(Op);
12846  SDValue CC;
12847  bool Inverted = false;
12848 
12849  if (Cond.getOpcode() == ISD::SETCC) {
12850  // Check for setcc([su]{add,sub,mul}o == 0).
12851  if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
12852  isa<ConstantSDNode>(Cond.getOperand(1)) &&
12853  cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
12854  Cond.getOperand(0).getResNo() == 1 &&
12855  (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
12856  Cond.getOperand(0).getOpcode() == ISD::UADDO ||
12857  Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
12858  Cond.getOperand(0).getOpcode() == ISD::USUBO ||
12859  Cond.getOperand(0).getOpcode() == ISD::SMULO ||
12860  Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
12861  Inverted = true;
12862  Cond = Cond.getOperand(0);
12863  } else {
12864  SDValue NewCond = LowerSETCC(Cond, DAG);
12865  if (NewCond.getNode())
12866  Cond = NewCond;
12867  }
12868  }
12869 #if 0
12870  // FIXME: LowerXALUO doesn't handle these!!
12871  else if (Cond.getOpcode() == X86ISD::ADD ||
12872  Cond.getOpcode() == X86ISD::SUB ||
12873  Cond.getOpcode() == X86ISD::SMUL ||
12874  Cond.getOpcode() == X86ISD::UMUL)
12875  Cond = LowerXALUO(Cond, DAG);
12876 #endif
12877 
12878  // Look pass (and (setcc_carry (cmp ...)), 1).
12879  if (Cond.getOpcode() == ISD::AND &&
12880  Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12881  ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12882  if (C && C->getAPIntValue() == 1)
12883  Cond = Cond.getOperand(0);
12884  }
12885 
12886  // If condition flag is set by a X86ISD::CMP, then use it as the condition
12887  // setting operand in place of the X86ISD::SETCC.
12888  unsigned CondOpcode = Cond.getOpcode();
12889  if (CondOpcode == X86ISD::SETCC ||
12890  CondOpcode == X86ISD::SETCC_CARRY) {
12891  CC = Cond.getOperand(0);
12892 
12893  SDValue Cmp = Cond.getOperand(1);
12894  unsigned Opc = Cmp.getOpcode();
12895  // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
12896  if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
12897  Cond = Cmp;
12898  addTest = false;
12899  } else {
12900  switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
12901  default: break;
12902  case X86::COND_O:
12903  case X86::COND_B:
12904  // These can only come from an arithmetic instruction with overflow,
12905  // e.g. SADDO, UADDO.
12906  Cond = Cond.getNode()->getOperand(1);
12907  addTest = false;
12908  break;
12909  }
12910  }
12911  }
12912  CondOpcode = Cond.getOpcode();
12913  if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12914  CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12915  ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12916  Cond.getOperand(0).getValueType() != MVT::i8)) {
12917  SDValue LHS = Cond.getOperand(0);
12918  SDValue RHS = Cond.getOperand(1);
12919  unsigned X86Opcode;
12920  unsigned X86Cond;
12921  SDVTList VTs;
12922  // Keep this in sync with LowerXALUO, otherwise we might create redundant
12923  // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
12924  // X86ISD::INC).
12925  switch (CondOpcode) {
12926  case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12927  case ISD::SADDO:
12928  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12929  if (C->isOne()) {
12930  X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
12931  break;
12932  }
12933  X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12934  case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12935  case ISD::SSUBO:
12936  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12937  if (C->isOne()) {
12938  X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
12939  break;
12940  }
12941  X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12942  case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12943  case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12944  default: llvm_unreachable("unexpected overflowing operator");
12945  }
12946  if (Inverted)
12947  X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
12948  if (CondOpcode == ISD::UMULO)
12949  VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12950  MVT::i32);
12951  else
12952  VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12953 
12954  SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
12955 
12956  if (CondOpcode == ISD::UMULO)
12957  Cond = X86Op.getValue(2);
12958  else
12959  Cond = X86Op.getValue(1);
12960 
12961  CC = DAG.getConstant(X86Cond, MVT::i8);
12962  addTest = false;
12963  } else {
12964  unsigned CondOpc;
12965  if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
12966  SDValue Cmp = Cond.getOperand(0).getOperand(1);
12967  if (CondOpc == ISD::OR) {
12968  // Also, recognize the pattern generated by an FCMP_UNE. We can emit
12969  // two branches instead of an explicit OR instruction with a
12970  // separate test.
12971  if (Cmp == Cond.getOperand(1).getOperand(1) &&
12972  isX86LogicalCmp(Cmp)) {
12973  CC = Cond.getOperand(0).getOperand(0);
12974  Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
12975  Chain, Dest, CC, Cmp);
12976  CC = Cond.getOperand(1).getOperand(0);
12977  Cond = Cmp;
12978  addTest = false;
12979  }
12980  } else { // ISD::AND
12981  // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
12982  // two branches instead of an explicit AND instruction with a
12983  // separate test. However, we only do this if this block doesn't
12984  // have a fall-through edge, because this requires an explicit
12985  // jmp when the condition is false.
12986  if (Cmp == Cond.getOperand(1).getOperand(1) &&
12987  isX86LogicalCmp(Cmp) &&
12988  Op.getNode()->hasOneUse()) {
12989  X86::CondCode CCode =
12990  (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
12991  CCode = X86::GetOppositeBranchCondition(CCode);
12992  CC = DAG.getConstant(CCode, MVT::i8);
12993  SDNode *User = *Op.getNode()->use_begin();
12994  // Look for an unconditional branch following this conditional branch.
12995  // We need this because we need to reverse the successors in order
12996  // to implement FCMP_OEQ.
12997  if (User->getOpcode() == ISD::BR) {
12998  SDValue FalseBB = User->getOperand(1);
12999  SDNode *NewBR =
13000  DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13001  assert(NewBR == User);
13002  (void)NewBR;
13003  Dest = FalseBB;
13004 
13005  Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13006  Chain, Dest, CC, Cmp);
13007  X86::CondCode CCode =
13008  (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
13009  CCode = X86::GetOppositeBranchCondition(CCode);
13010  CC = DAG.getConstant(CCode, MVT::i8);
13011  Cond = Cmp;
13012  addTest = false;
13013  }
13014  }
13015  }
13016  } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
13017  // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
13018  // It should be transformed during dag combiner except when the condition
13019  // is set by a arithmetics with overflow node.
13020  X86::CondCode CCode =
13021  (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13022  CCode = X86::GetOppositeBranchCondition(CCode);
13023  CC = DAG.getConstant(CCode, MVT::i8);
13024  Cond = Cond.getOperand(0).getOperand(1);
13025  addTest = false;
13026  } else if (Cond.getOpcode() == ISD::SETCC &&
13027  cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
13028  // For FCMP_OEQ, we can emit
13029  // two branches instead of an explicit AND instruction with a
13030  // separate test. However, we only do this if this block doesn't
13031  // have a fall-through edge, because this requires an explicit
13032  // jmp when the condition is false.
13033  if (Op.getNode()->hasOneUse()) {
13034  SDNode *User = *Op.getNode()->use_begin();
13035  // Look for an unconditional branch following this conditional branch.
13036  // We need this because we need to reverse the successors in order
13037  // to implement FCMP_OEQ.
13038  if (User->getOpcode() == ISD::BR) {
13039  SDValue FalseBB = User->getOperand(1);
13040  SDNode *NewBR =
13041  DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13042  assert(NewBR == User);
13043  (void)NewBR;
13044  Dest = FalseBB;
13045 
13046  SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13047  Cond.getOperand(0), Cond.getOperand(1));
13048  Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13049  CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13050  Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13051  Chain, Dest, CC, Cmp);
13052  CC = DAG.getConstant(X86::COND_P, MVT::i8);
13053  Cond = Cmp;
13054  addTest = false;
13055  }
13056  }
13057  } else if (Cond.getOpcode() == ISD::SETCC &&
13058  cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13059  // For FCMP_UNE, we can emit
13060  // two branches instead of an explicit AND instruction with a
13061  // separate test. However, we only do this if this block doesn't
13062  // have a fall-through edge, because this requires an explicit
13063  // jmp when the condition is false.
13064  if (Op.getNode()->hasOneUse()) {
13065  SDNode *User = *Op.getNode()->use_begin();
13066  // Look for an unconditional branch following this conditional branch.
13067  // We need this because we need to reverse the successors in order
13068  // to implement FCMP_UNE.
13069  if (User->getOpcode() == ISD::BR) {
13070  SDValue FalseBB = User->getOperand(1);
13071  SDNode *NewBR =
13072  DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13073  assert(NewBR == User);
13074  (void)NewBR;
13075 
13076  SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13077  Cond.getOperand(0), Cond.getOperand(1));
13078  Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13079  CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13080  Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13081  Chain, Dest, CC, Cmp);
13082  CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13083  Cond = Cmp;
13084  addTest = false;
13085  Dest = FalseBB;
13086  }
13087  }
13088  }
13089  }
13090 
13091  if (addTest) {
13092  // Look pass the truncate if the high bits are known zero.
13093  if (isTruncWithZeroHighBitsInput(Cond, DAG))
13094  Cond = Cond.getOperand(0);
13095 
13096  // We know the result of AND is compared against zero. Try to match
13097  // it to BT.
13098  if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13099  SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
13100  if (NewSetCC.getNode()) {
13101  CC = NewSetCC.getOperand(0);
13102  Cond = NewSetCC.getOperand(1);
13103  addTest = false;
13104  }
13105  }
13106  }
13107 
13108  if (addTest) {
13109  X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
13110  CC = DAG.getConstant(X86Cond, MVT::i8);
13111  Cond = EmitTest(Cond, X86Cond, dl, DAG);
13112  }
13113  Cond = ConvertCmpIfNecessary(Cond, DAG);
13114  return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13115  Chain, Dest, CC, Cond);
13116 }
llvm::X86TargetLowering::ConvertCmpIfNecessary
SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const
Convert a comparison if required by the subtarget.
Definition: X86ISelLowering.cpp:11926
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::SDNode::hasOneUse
bool hasOneUse() const
Definition: SelectionDAGNodes.h:438
llvm::SDValue::hasOneUse
bool hasOneUse() const
Definition: SelectionDAGNodes.h:910
llvm::SDNode::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:401
llvm::X86TargetLowering::LowerToBT
SDValue LowerToBT(SDValue And, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:11956
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:592
llvm::X86TargetLowering::EmitTest
SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:11654
llvm::ISD::SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:221
llvm::SDValue::getResNo
unsigned getResNo() const
get the index which selects a specific result in the SDNode
Definition: SelectionDAGNodes.h:127
llvm::X86TargetLowering::LowerSETCC
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:12407
llvm::X86ISD::BT
X86 bit-test instructions.
Definition: X86ISelLowering.h:96
isX86LogicalCmp
static bool isX86LogicalCmp(SDValue Op)
Definition: X86ISelLowering.cpp:12481
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::X86ISD::CMP
X86 compare and logical compare instructions.
Definition: X86ISelLowering.h:93
llvm::ConstantSDNode::getAPIntValue
const APInt & getAPIntValue() const
Definition: SelectionDAGNodes.h:1349
isTruncWithZeroHighBitsInput
static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:12506
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::ISD::BR
Control flow instructions. These all have token chains.
Definition: ISDOpcodes.h:511
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
isAndOrOfSetCCs
static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc)
Definition: X86ISelLowering.cpp:12817
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::SDNode::use_begin
use_iterator use_begin() const
Definition: SelectionDAGNodes.h:528
isXor1OfSetCC
static bool isXor1OfSetCC(SDValue Op)
Definition: X86ISelLowering.cpp:12829
llvm::SelectionDAG::UpdateNodeOperands
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Definition: SelectionDAG.cpp:5256
llvm::X86::GetOppositeBranchCondition
CondCode GetOppositeBranchCondition(CondCode CC)
Definition: X86InstrInfo.cpp:2630
llvm::dyn_cast
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::SDValue::getConstantOperandVal
uint64_t getConstantOperandVal(unsigned i) const
Definition: SelectionDAGNodes.h:892
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
llvm::ISD::SMULO
Same for multiplication.
Definition: ISDOpcodes.h:224
LowerXALUO
static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:15808
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
SDValue X86TargetLowering::LowerBUILD_VECTOR ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 6493 of file X86ISelLowering.cpp.

6493  {
6494  SDLoc dl(Op);
6495 
6496  MVT VT = Op.getSimpleValueType();
6497  MVT ExtVT = VT.getVectorElementType();
6498  unsigned NumElems = Op.getNumOperands();
6499 
6500  // Generate vectors for predicate vectors.
6501  if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6502  return LowerBUILD_VECTORvXi1(Op, DAG);
6503 
6504  // Vectors containing all zeros can be matched by pxor and xorps later
6505  if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6506  // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6507  // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6508  if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6509  return Op;
6510 
6511  return getZeroVector(VT, Subtarget, DAG, dl);
6512  }
6513 
6514  // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6515  // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6516  // vpcmpeqd on 256-bit vectors.
6517  if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6518  if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6519  return Op;
6520 
6521  if (!VT.is512BitVector())
6522  return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6523  }
6524 
6525  SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6526  if (Broadcast.getNode())
6527  return Broadcast;
6528 
6529  unsigned EVTBits = ExtVT.getSizeInBits();
6530 
6531  unsigned NumZero = 0;
6532  unsigned NumNonZero = 0;
6533  unsigned NonZeros = 0;
6534  bool IsAllConstants = true;
6535  SmallSet<SDValue, 8> Values;
6536  for (unsigned i = 0; i < NumElems; ++i) {
6537  SDValue Elt = Op.getOperand(i);
6538  if (Elt.getOpcode() == ISD::UNDEF)
6539  continue;
6540  Values.insert(Elt);
6541  if (Elt.getOpcode() != ISD::Constant &&
6542  Elt.getOpcode() != ISD::ConstantFP)
6543  IsAllConstants = false;
6544  if (X86::isZeroNode(Elt))
6545  NumZero++;
6546  else {
6547  NonZeros |= (1 << i);
6548  NumNonZero++;
6549  }
6550  }
6551 
6552  // All undef vector. Return an UNDEF. All zero vectors were handled above.
6553  if (NumNonZero == 0)
6554  return DAG.getUNDEF(VT);
6555 
6556  // Special case for single non-zero, non-undef, element.
6557  if (NumNonZero == 1) {
6558  unsigned Idx = countTrailingZeros(NonZeros);
6559  SDValue Item = Op.getOperand(Idx);
6560 
6561  // If this is an insertion of an i64 value on x86-32, and if the top bits of
6562  // the value are obviously zero, truncate the value to i32 and do the
6563  // insertion that way. Only do this if the value is non-constant or if the
6564  // value is a constant being inserted into element 0. It is cheaper to do
6565  // a constant pool load than it is to do a movd + shuffle.
6566  if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6567  (!IsAllConstants || Idx == 0)) {
6568  if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6569  // Handle SSE only.
6570  assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6571  EVT VecVT = MVT::v4i32;
6572  unsigned VecElts = 4;
6573 
6574  // Truncate the value (which may itself be a constant) to i32, and
6575  // convert it to a vector with movd (S2V+shuffle to zero extend).
6576  Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6577  Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6578  Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6579 
6580  // Now we have our 32-bit value zero extended in the low element of
6581  // a vector. If Idx != 0, swizzle it into place.
6582  if (Idx != 0) {
6583  SmallVector<int, 4> Mask;
6584  Mask.push_back(Idx);
6585  for (unsigned i = 1; i != VecElts; ++i)
6586  Mask.push_back(i);
6587  Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6588  &Mask[0]);
6589  }
6590  return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6591  }
6592  }
6593 
6594  // If we have a constant or non-constant insertion into the low element of
6595  // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6596  // the rest of the elements. This will be matched as movd/movq/movss/movsd
6597  // depending on what the source datatype is.
6598  if (Idx == 0) {
6599  if (NumZero == 0)
6600  return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6601 
6602  if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6603  (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6604  if (VT.is256BitVector() || VT.is512BitVector()) {
6605  SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6606  return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6607  Item, DAG.getIntPtrConstant(0));
6608  }
6609  assert(VT.is128BitVector() && "Expected an SSE value type!");
6610  Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6611  // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6612  return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6613  }
6614 
6615  if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6616  Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6617  Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6618  if (VT.is256BitVector()) {
6619  SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6620  Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6621  } else {
6622  assert(VT.is128BitVector() && "Expected an SSE value type!");
6623  Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6624  }
6625  return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6626  }
6627  }
6628 
6629  // Is it a vector logical left shift?
6630  if (NumElems == 2 && Idx == 1 &&
6631  X86::isZeroNode(Op.getOperand(0)) &&
6632  !X86::isZeroNode(Op.getOperand(1))) {
6633  unsigned NumBits = VT.getSizeInBits();
6634  return getVShift(true, VT,
6635  DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6636  VT, Op.getOperand(1)),
6637  NumBits/2, DAG, *this, dl);
6638  }
6639 
6640  if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6641  return SDValue();
6642 
6643  // Otherwise, if this is a vector with i32 or f32 elements, and the element
6644  // is a non-constant being inserted into an element other than the low one,
6645  // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6646  // movd/movss) to move this into the low element, then shuffle it into
6647  // place.
6648  if (EVTBits == 32) {
6649  Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6650 
6651  // Turn it into a shuffle of zero and zero-extended scalar to vector.
6652  Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6653  SmallVector<int, 8> MaskVec;
6654  for (unsigned i = 0; i != NumElems; ++i)
6655  MaskVec.push_back(i == Idx ? 0 : 1);
6656  return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6657  }
6658  }
6659 
6660  // Splat is obviously ok. Let legalizer expand it to a shuffle.
6661  if (Values.size() == 1) {
6662  if (EVTBits == 32) {
6663  // Instead of a shuffle like this:
6664  // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6665  // Check if it's possible to issue this instead.
6666  // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6667  unsigned Idx = countTrailingZeros(NonZeros);
6668  SDValue Item = Op.getOperand(Idx);
6669  if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6670  return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6671  }
6672  return SDValue();
6673  }
6674 
6675  // A vector full of immediates; various special cases are already
6676  // handled, so this is best done with a single constant-pool load.
6677  if (IsAllConstants)
6678  return SDValue();
6679 
6680  // For AVX-length vectors, build the individual 128-bit pieces and use
6681  // shuffles to put them in place.
6682  if (VT.is256BitVector() || VT.is512BitVector()) {
6683  SmallVector<SDValue, 64> V;
6684  for (unsigned i = 0; i != NumElems; ++i)
6685  V.push_back(Op.getOperand(i));
6686 
6687  EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6688 
6689  // Build both the lower and upper subvector.
6690  SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6691  makeArrayRef(&V[0], NumElems/2));
6692  SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6693  makeArrayRef(&V[NumElems / 2], NumElems/2));
6694 
6695  // Recreate the wider vector with the lower and upper part.
6696  if (VT.is256BitVector())
6697  return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6698  return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6699  }
6700 
6701  // Let legalizer expand 2-wide build_vectors.
6702  if (EVTBits == 64) {
6703  if (NumNonZero == 1) {
6704  // One half is zero or undef.
6705  unsigned Idx = countTrailingZeros(NonZeros);
6706  SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6707  Op.getOperand(Idx));
6708  return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6709  }
6710  return SDValue();
6711  }
6712 
6713  // If element VT is < 32 bits, convert it to inserts into a zero vector.
6714  if (EVTBits == 8 && NumElems == 16) {
6715  SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6716  Subtarget, *this);
6717  if (V.getNode()) return V;
6718  }
6719 
6720  if (EVTBits == 16 && NumElems == 8) {
6721  SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6722  Subtarget, *this);
6723  if (V.getNode()) return V;
6724  }
6725 
6726  // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6727  if (EVTBits == 32 && NumElems == 4) {
6728  SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6729  NumZero, DAG, Subtarget, *this);
6730  if (V.getNode())
6731  return V;
6732  }
6733 
6734  // If element VT is == 32 bits, turn it into a number of shuffles.
6735  SmallVector<SDValue, 8> V(NumElems);
6736  if (NumElems == 4 && NumZero > 0) {
6737  for (unsigned i = 0; i < 4; ++i) {
6738  bool isZero = !(NonZeros & (1 << i));
6739  if (isZero)
6740  V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6741  else
6742  V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6743  }
6744 
6745  for (unsigned i = 0; i < 2; ++i) {
6746  switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6747  default: break;
6748  case 0:
6749  V[i] = V[i*2]; // Must be a zero vector.
6750  break;
6751  case 1:
6752  V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6753  break;
6754  case 2:
6755  V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6756  break;
6757  case 3:
6758  V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6759  break;
6760  }
6761  }
6762 
6763  bool Reverse1 = (NonZeros & 0x3) == 2;
6764  bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6765  int MaskVec[] = {
6766  Reverse1 ? 1 : 0,
6767  Reverse1 ? 0 : 1,
6768  static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6769  static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6770  };
6771  return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6772  }
6773 
6774  if (Values.size() > 1 && VT.is128BitVector()) {
6775  // Check for a build vector of consecutive loads.
6776  for (unsigned i = 0; i < NumElems; ++i)
6777  V[i] = Op.getOperand(i);
6778 
6779  // Check for elements which are consecutive loads.
6780  SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6781  if (LD.getNode())
6782  return LD;
6783 
6784  // Check for a build vector from mostly shuffle plus few inserting.
6785  SDValue Sh = buildFromShuffleMostly(Op, DAG);
6786  if (Sh.getNode())
6787  return Sh;
6788 
6789  // For SSE 4.1, use insertps to put the high elements into the low element.
6790  if (getSubtarget()->hasSSE41()) {
6791  SDValue Result;
6792  if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6793  Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6794  else
6795  Result = DAG.getUNDEF(VT);
6796 
6797  for (unsigned i = 1; i < NumElems; ++i) {
6798  if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6799  Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6800  Op.getOperand(i), DAG.getIntPtrConstant(i));
6801  }
6802  return Result;
6803  }
6804 
6805  // Otherwise, expand into a number of unpckl*, start by extending each of
6806  // our (non-undef) elements to the full vector width with the element in the
6807  // bottom slot of the vector (which generates no code for SSE).
6808  for (unsigned i = 0; i < NumElems; ++i) {
6809  if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6810  V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6811  else
6812  V[i] = DAG.getUNDEF(VT);
6813  }
6814 
6815  // Next, we iteratively mix elements, e.g. for v4f32:
6816  // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6817  // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6818  // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6819  unsigned EltStride = NumElems >> 1;
6820  while (EltStride != 0) {
6821  for (unsigned i = 0; i < EltStride; ++i) {
6822  // If V[i+EltStride] is undef and this is the first round of mixing,
6823  // then it is safe to just drop this shuffle: V[i] is already in the
6824  // right place, the one element (since it's the first round) being
6825  // inserted as undef can be dropped. This isn't safe for successive
6826  // rounds because they will permute elements within both vectors.
6827  if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6828  EltStride == NumElems/2)
6829  continue;
6830 
6831  V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6832  }
6833  EltStride >>= 1;
6834  }
6835  return V[0];
6836  }
6837  return SDValue();
6838 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
LowerBuildVectorv8i16
static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget *Subtarget, const TargetLowering &TLI)
Definition: X86ISelLowering.cpp:5442
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition: SmallVector.h:225
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
getOnesVector
static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG, SDLoc dl)
Definition: X86ISelLowering.cpp:4932
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
getVShift
static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits, SelectionDAG &DAG, const TargetLowering &TLI, SDLoc dl)
Definition: X86ISelLowering.cpp:5547
getZeroVector
static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, SelectionDAG &DAG, SDLoc dl)
Definition: X86ISelLowering.cpp:4885
getMOVL
static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1, SDValue V2)
Definition: X86ISelLowering.cpp:4966
llvm::MVT::is512BitVector
bool is512BitVector() const
is512BitVector - Return true if this is a 512-bit vector type.
Definition: MachineValueType.h:224
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
isZero
static bool isZero(SDValue V)
isZero - Returns true if Elt is a constant integer zero
Definition: X86ISelLowering.cpp:4755
llvm::X86Subtarget::hasSSE41
bool hasSSE41() const
Definition: X86Subtarget.h:315
llvm::SDValue::getNumOperands
unsigned getNumOperands() const
Definition: SelectionDAGNodes.h:886
llvm::X86TargetLowering::getSubtarget
const X86Subtarget * getSubtarget() const
Definition: X86ISelLowering.h:746
Insert128BitVector
static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl)
Definition: X86ISelLowering.cpp:162
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:276
llvm::ISD::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const SDNode *N)
Definition: SelectionDAG.cpp:144
LowerAsSplatVectorLoad
static SDValue LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:5561
LowerBuildVectorv4x32
static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget *Subtarget, const TargetLowering &TLI)
LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
Definition: X86ISelLowering.cpp:5473
EltsFromConsecutiveLoads
static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl< SDValue > &Elts, SDLoc &DL, SelectionDAG &DAG, bool isAfterLegalize)
Definition: X86ISelLowering.cpp:5643
llvm::MVT::getScalarType
MVT getScalarType() const
Definition: MachineValueType.h:260
llvm::SmallSet::size
size_type size() const
Definition: SmallSet.h:47
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::SelectionDAG::getVectorShuffle
SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, const int *MaskElts)
Definition: SelectionDAG.cpp:1479
llvm::SelectionDAG::getUNDEF
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
llvm::SmallSet::insert
bool insert(const T &V)
Definition: SmallSet.h:63
llvm::ISD::UNDEF
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
llvm::X86Subtarget::hasSSE2
bool hasSSE2() const
Definition: X86Subtarget.h:312
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
buildFromShuffleMostly
static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:5913
getUnpackl
static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, SDValue V2)
getUnpackl - Returns a vector_shuffle node for an unpackl operation.
Definition: X86ISelLowering.cpp:4977
LowerBuildVectorv16i8
static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget *Subtarget, const TargetLowering &TLI)
Definition: X86ISelLowering.cpp:5394
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
LowerVectorBroadcast
static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:5743
llvm::SelectionDAG::MaskedValueIsZero
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Definition: SelectionDAG.cpp:1934
llvm::EVT::getVectorVT
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
llvm::ISD::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const SDNode *N)
Node predicates.
Definition: SelectionDAG.cpp:96
llvm::X86TargetLowering::LowerBUILD_VECTORvXi1
SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:5987
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::MVT::is128BitVector
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
Definition: MachineValueType.h:210
llvm::X86Subtarget::hasInt256
bool hasInt256() const
Definition: X86Subtarget.h:321
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::APInt::getBitsSet
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
Definition: APInt.h:493
llvm::MVT::is256BitVector
bool is256BitVector() const
is256BitVector - Return true if this is a 256-bit vector type.
Definition: MachineValueType.h:217
Concat128BitVectors
static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, unsigned NumElems, SelectionDAG &DAG, SDLoc dl)
Definition: X86ISelLowering.cpp:180
getShuffleVectorZeroOrUndef
static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, bool IsZero, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:5090
llvm::X86Subtarget::hasAVX512
bool hasAVX512() const
Definition: X86Subtarget.h:319
llvm::X86::isZeroNode
bool isZeroNode(SDValue Elt)
Definition: X86ISelLowering.cpp:4762
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:264
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
llvm::SDNode::isOnlyUserOf
bool isOnlyUserOf(SDNode *N) const
Definition: SelectionDAG.cpp:6349
llvm::countTrailingZeros
std::enable_if< std::numeric_limits< T >::is_integer &&!std::numeric_limits< T >::is_signed, std::size_t >::type countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:49
Concat256BitVectors
static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT, unsigned NumElems, SelectionDAG &DAG, SDLoc dl)
Definition: X86ISelLowering.cpp:187
SDValue X86TargetLowering::LowerBUILD_VECTORvXi1 ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 5987 of file X86ISelLowering.cpp.

5987  {
5988 
5989  MVT VT = Op.getSimpleValueType();
5990  assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5991  "Unexpected type in LowerBUILD_VECTORvXi1!");
5992 
5993  SDLoc dl(Op);
5994  if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5995  SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5996  SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5997  return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5998  }
5999 
6000  if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6001  SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6002  SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6003  return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6004  }
6005 
6006  bool AllContants = true;
6007  uint64_t Immediate = 0;
6008  int NonConstIdx = -1;
6009  bool IsSplat = true;
6010  unsigned NumNonConsts = 0;
6011  unsigned NumConsts = 0;
6012  for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6013  SDValue In = Op.getOperand(idx);
6014  if (In.getOpcode() == ISD::UNDEF)
6015  continue;
6016  if (!isa<ConstantSDNode>(In)) {
6017  AllContants = false;
6018  NonConstIdx = idx;
6019  NumNonConsts++;
6020  }
6021  else {
6022  NumConsts++;
6023  if (cast<ConstantSDNode>(In)->getZExtValue())
6024  Immediate |= (1ULL << idx);
6025  }
6026  if (In != Op.getOperand(0))
6027  IsSplat = false;
6028  }
6029 
6030  if (AllContants) {
6031  SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6032  DAG.getConstant(Immediate, MVT::i16));
6033  return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6034  DAG.getIntPtrConstant(0));
6035  }
6036 
6037  if (NumNonConsts == 1 && NonConstIdx != 0) {
6038  SDValue DstVec;
6039  if (NumConsts) {
6040  SDValue VecAsImm = DAG.getConstant(Immediate,
6041  MVT::getIntegerVT(VT.getSizeInBits()));
6042  DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6043  }
6044  else
6045  DstVec = DAG.getUNDEF(VT);
6046  return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6047  Op.getOperand(NonConstIdx),
6048  DAG.getIntPtrConstant(NonConstIdx));
6049  }
6050  if (!IsSplat && (NonConstIdx != 0))
6051  llvm_unreachable("Unsupported BUILD_VECTOR operation");
6052  MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6053  SDValue Select;
6054  if (IsSplat)
6055  Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6056  DAG.getConstant(-1, SelectVT),
6057  DAG.getConstant(0, SelectVT));
6058  else
6059  Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6060  DAG.getConstant((Immediate | 1), SelectVT),
6061  DAG.getConstant(Immediate, SelectVT));
6062  return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6063 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:486
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm::SDValue::getNumOperands
unsigned getNumOperands() const
Definition: SelectionDAGNodes.h:886
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::ISD::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const SDNode *N)
Definition: SelectionDAG.cpp:144
llvm::SelectionDAG::getUNDEF
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
llvm::ISD::UNDEF
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:312
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::ISD::isBuildVectorAllOnes
bool isBuildVectorAllOnes(const SDNode *N)
Node predicates.
Definition: SelectionDAG.cpp:96
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:406
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:264
SDValue X86TargetLowering::LowerCall ( TargetLowering::CallLoweringInfo &  CLI,
SmallVectorImpl< SDValue > &  InVals 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2584 of file X86ISelLowering.cpp.

2585  {
2586  SelectionDAG &DAG = CLI.DAG;
2587  SDLoc &dl = CLI.DL;
2588  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2589  SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2590  SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2591  SDValue Chain = CLI.Chain;
2592  SDValue Callee = CLI.Callee;
2593  CallingConv::ID CallConv = CLI.CallConv;
2594  bool &isTailCall = CLI.IsTailCall;
2595  bool isVarArg = CLI.IsVarArg;
2596 
2597  MachineFunction &MF = DAG.getMachineFunction();
2598  bool Is64Bit = Subtarget->is64Bit();
2599  bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2600  StructReturnType SR = callIsStructReturn(Outs);
2601  bool IsSibcall = false;
2602 
2603  if (MF.getTarget().Options.DisableTailCalls)
2604  isTailCall = false;
2605 
2606  bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2607  if (IsMustTail) {
2608  // Force this to be a tail call. The verifier rules are enough to ensure
2609  // that we can lower this successfully without moving the return address
2610  // around.
2611  isTailCall = true;
2612  } else if (isTailCall) {
2613  // Check if it's really possible to do a tail call.
2614  isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2615  isVarArg, SR != NotStructReturn,
2616  MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2617  Outs, OutVals, Ins, DAG);
2618 
2619  // Sibcalls are automatically detected tailcalls which do not require
2620  // ABI changes.
2621  if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2622  IsSibcall = true;
2623 
2624  if (isTailCall)
2625  ++NumTailCalls;
2626  }
2627 
2628  assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2629  "Var args not supported with calling convention fastcc, ghc or hipe");
2630 
2631  // Analyze operands of the call, assigning locations to each operand.
2632  SmallVector<CCValAssign, 16> ArgLocs;
2633  CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
2634  ArgLocs, *DAG.getContext());
2635 
2636  // Allocate shadow area for Win64
2637  if (IsWin64)
2638  CCInfo.AllocateStack(32, 8);
2639 
2640  CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2641 
2642  // Get a count of how many bytes are to be pushed on the stack.
2643  unsigned NumBytes = CCInfo.getNextStackOffset();
2644  if (IsSibcall)
2645  // This is a sibcall. The memory operands are available in caller's
2646  // own caller's stack.
2647  NumBytes = 0;
2648  else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2649  IsTailCallConvention(CallConv))
2650  NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2651 
2652  int FPDiff = 0;
2653  if (isTailCall && !IsSibcall && !IsMustTail) {
2654  // Lower arguments at fp - stackoffset + fpdiff.
2655  X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2656  unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2657 
2658  FPDiff = NumBytesCallerPushed - NumBytes;
2659 
2660  // Set the delta of movement of the returnaddr stackslot.
2661  // But only set if delta is greater than previous delta.
2662  if (FPDiff < X86Info->getTCReturnAddrDelta())
2663  X86Info->setTCReturnAddrDelta(FPDiff);
2664  }
2665 
2666  unsigned NumBytesToPush = NumBytes;
2667  unsigned NumBytesToPop = NumBytes;
2668 
2669  // If we have an inalloca argument, all stack space has already been allocated
2670  // for us and be right at the top of the stack. We don't support multiple
2671  // arguments passed in memory when using inalloca.
2672  if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2673  NumBytesToPush = 0;
2674  assert(ArgLocs.back().getLocMemOffset() == 0 &&
2675  "an inalloca argument must be the only memory argument");
2676  }
2677 
2678  if (!IsSibcall)
2679  Chain = DAG.getCALLSEQ_START(
2680  Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2681 
2682  SDValue RetAddrFrIdx;
2683  // Load return address for tail calls.
2684  if (isTailCall && FPDiff)
2685  Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2686  Is64Bit, FPDiff, dl);
2687 
2688  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2689  SmallVector<SDValue, 8> MemOpChains;
2690  SDValue StackPtr;
2691 
2692  // Walk the register/memloc assignments, inserting copies/loads. In the case
2693  // of tail call optimization arguments are handle later.
2694  const X86RegisterInfo *RegInfo =
2695  static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
2696  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2697  // Skip inalloca arguments, they have already been written.
2698  ISD::ArgFlagsTy Flags = Outs[i].Flags;
2699  if (Flags.isInAlloca())
2700  continue;
2701 
2702  CCValAssign &VA = ArgLocs[i];
2703  EVT RegVT = VA.getLocVT();
2704  SDValue Arg = OutVals[i];
2705  bool isByVal = Flags.isByVal();
2706 
2707  // Promote the value if needed.
2708  switch (VA.getLocInfo()) {
2709  default: llvm_unreachable("Unknown loc info!");
2710  case CCValAssign::Full: break;
2711  case CCValAssign::SExt:
2712  Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2713  break;
2714  case CCValAssign::ZExt:
2715  Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2716  break;
2717  case CCValAssign::AExt:
2718  if (RegVT.is128BitVector()) {
2719  // Special case: passing MMX values in XMM registers.
2720  Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2721  Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2722  Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2723  } else
2724  Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2725  break;
2726  case CCValAssign::BCvt:
2727  Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2728  break;
2729  case CCValAssign::Indirect: {
2730  // Store the argument.
2731  SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2732  int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2733  Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2734  MachinePointerInfo::getFixedStack(FI),
2735  false, false, 0);
2736  Arg = SpillSlot;
2737  break;
2738  }
2739  }
2740 
2741  if (VA.isRegLoc()) {
2742  RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2743  if (isVarArg && IsWin64) {
2744  // Win64 ABI requires argument XMM reg to be copied to the corresponding
2745  // shadow reg if callee is a varargs function.
2746  unsigned ShadowReg = 0;
2747  switch (VA.getLocReg()) {
2748  case X86::XMM0: ShadowReg = X86::RCX; break;
2749  case X86::XMM1: ShadowReg = X86::RDX; break;
2750  case X86::XMM2: ShadowReg = X86::R8; break;
2751  case X86::XMM3: ShadowReg = X86::R9; break;
2752  }
2753  if (ShadowReg)
2754  RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2755  }
2756  } else if (!IsSibcall && (!isTailCall || isByVal)) {
2757  assert(VA.isMemLoc());
2758  if (!StackPtr.getNode())
2759  StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2760  getPointerTy());
2761  MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2762  dl, DAG, VA, Flags));
2763  }
2764  }
2765 
2766  if (!MemOpChains.empty())
2767  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2768 
2769  if (Subtarget->isPICStyleGOT()) {
2770  // ELF / PIC requires GOT in the EBX register before function calls via PLT
2771  // GOT pointer.
2772  if (!isTailCall) {
2773  RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2774  DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2775  } else {
2776  // If we are tail calling and generating PIC/GOT style code load the
2777  // address of the callee into ECX. The value in ecx is used as target of
2778  // the tail jump. This is done to circumvent the ebx/callee-saved problem
2779  // for tail calls on PIC/GOT architectures. Normally we would just put the
2780  // address of GOT into ebx and then call target@PLT. But for tail calls
2781  // ebx would be restored (since ebx is callee saved) before jumping to the
2782  // target@PLT.
2783 
2784  // Note: The actual moving to ECX is done further down.
2785  GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2786  if (G && !G->getGlobal()->hasHiddenVisibility() &&
2787  !G->getGlobal()->hasProtectedVisibility())
2788  Callee = LowerGlobalAddress(Callee, DAG);
2789  else if (isa<ExternalSymbolSDNode>(Callee))
2790  Callee = LowerExternalSymbol(Callee, DAG);
2791  }
2792  }
2793 
2794  if (Is64Bit && isVarArg && !IsWin64) {
2795  // From AMD64 ABI document:
2796  // For calls that may call functions that use varargs or stdargs
2797  // (prototype-less calls or calls to functions containing ellipsis (...) in
2798  // the declaration) %al is used as hidden argument to specify the number
2799  // of SSE registers used. The contents of %al do not need to match exactly
2800  // the number of registers, but must be an ubound on the number of SSE
2801  // registers used and is in the range 0 - 8 inclusive.
2802 
2803  // Count the number of XMM registers allocated.
2804  static const MCPhysReg XMMArgRegs[] = {
2805  X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2806  X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2807  };
2808  unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2809  assert((Subtarget->hasSSE1() || !NumXMMRegs)
2810  && "SSE registers cannot be used when SSE is disabled");
2811 
2812  RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2813  DAG.getConstant(NumXMMRegs, MVT::i8)));
2814  }
2815 
2816  // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2817  // don't need this because the eligibility check rejects calls that require
2818  // shuffling arguments passed in memory.
2819  if (!IsSibcall && isTailCall) {
2820  // Force all the incoming stack arguments to be loaded from the stack
2821  // before any new outgoing arguments are stored to the stack, because the
2822  // outgoing stack slots may alias the incoming argument stack slots, and
2823  // the alias isn't otherwise explicit. This is slightly more conservative
2824  // than necessary, because it means that each store effectively depends
2825  // on every argument instead of just those arguments it would clobber.
2826  SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2827 
2828  SmallVector<SDValue, 8> MemOpChains2;
2829  SDValue FIN;
2830  int FI = 0;
2831  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2832  CCValAssign &VA = ArgLocs[i];
2833  if (VA.isRegLoc())
2834  continue;
2835  assert(VA.isMemLoc());
2836  SDValue Arg = OutVals[i];
2837  ISD::ArgFlagsTy Flags = Outs[i].Flags;
2838  // Skip inalloca arguments. They don't require any work.
2839  if (Flags.isInAlloca())
2840  continue;
2841  // Create frame index.
2842  int32_t Offset = VA.getLocMemOffset()+FPDiff;
2843  uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2844  FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2845  FIN = DAG.getFrameIndex(FI, getPointerTy());
2846 
2847  if (Flags.isByVal()) {
2848  // Copy relative to framepointer.
2849  SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2850  if (!StackPtr.getNode())
2851  StackPtr = DAG.getCopyFromReg(Chain, dl,
2852  RegInfo->getStackRegister(),
2853  getPointerTy());
2854  Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2855 
2856  MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2857  ArgChain,
2858  Flags, DAG, dl));
2859  } else {
2860  // Store relative to framepointer.
2861  MemOpChains2.push_back(
2862  DAG.getStore(ArgChain, dl, Arg, FIN,
2863  MachinePointerInfo::getFixedStack(FI),
2864  false, false, 0));
2865  }
2866  }
2867 
2868  if (!MemOpChains2.empty())
2869  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2870 
2871  // Store the return address to the appropriate stack slot.
2872  Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2873  getPointerTy(), RegInfo->getSlotSize(),
2874  FPDiff, dl);
2875  }
2876 
2877  // Build a sequence of copy-to-reg nodes chained together with token chain
2878  // and flag operands which copy the outgoing args into registers.
2879  SDValue InFlag;
2880  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2881  Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2882  RegsToPass[i].second, InFlag);
2883  InFlag = Chain.getValue(1);
2884  }
2885 
2886  if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2887  assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2888  // In the 64-bit large code model, we have to make all calls
2889  // through a register, since the call instruction's 32-bit
2890  // pc-relative offset may not be large enough to hold the whole
2891  // address.
2892  } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2893  // If the callee is a GlobalAddress node (quite common, every direct call
2894  // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2895  // it.
2896 
2897  // We should use extra load for direct calls to dllimported functions in
2898  // non-JIT mode.
2899  const GlobalValue *GV = G->getGlobal();
2900  if (!GV->hasDLLImportStorageClass()) {
2901  unsigned char OpFlags = 0;
2902  bool ExtraLoad = false;
2903  unsigned WrapperKind = ISD::DELETED_NODE;
2904 
2905  // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2906  // external symbols most go through the PLT in PIC mode. If the symbol
2907  // has hidden or protected visibility, or if it is static or local, then
2908  // we don't need to use the PLT - we can directly call it.
2909  if (Subtarget->isTargetELF() &&
2910  DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
2911  GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2912  OpFlags = X86II::MO_PLT;
2913  } else if (Subtarget->isPICStyleStubAny() &&
2914  (GV->isDeclaration() || GV->isWeakForLinker()) &&
2915  (!Subtarget->getTargetTriple().isMacOSX() ||
2916  Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2917  // PC-relative references to external symbols should go through $stub,
2918  // unless we're building with the leopard linker or later, which
2919  // automatically synthesizes these stubs.
2920  OpFlags = X86II::MO_DARWIN_STUB;
2921  } else if (Subtarget->isPICStyleRIPRel() &&
2922  isa<Function>(GV) &&
2923  cast<Function>(GV)->getAttributes().
2924  hasAttribute(AttributeSet::FunctionIndex,
2925  Attribute::NonLazyBind)) {
2926  // If the function is marked as non-lazy, generate an indirect call
2927  // which loads from the GOT directly. This avoids runtime overhead
2928  // at the cost of eager binding (and one extra byte of encoding).
2929  OpFlags = X86II::MO_GOTPCREL;
2930  WrapperKind = X86ISD::WrapperRIP;
2931  ExtraLoad = true;
2932  }
2933 
2934  Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2935  G->getOffset(), OpFlags);
2936 
2937  // Add a wrapper if needed.
2938  if (WrapperKind != ISD::DELETED_NODE)
2939  Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2940  // Add extra indirection if needed.
2941  if (ExtraLoad)
2942  Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2943  MachinePointerInfo::getGOT(),
2944  false, false, false, 0);
2945  }
2946  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2947  unsigned char OpFlags = 0;
2948 
2949  // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2950  // external symbols should go through the PLT.
2951  if (Subtarget->isTargetELF() &&
2952  DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
2953  OpFlags = X86II::MO_PLT;
2954  } else if (Subtarget->isPICStyleStubAny() &&
2955  (!Subtarget->getTargetTriple().isMacOSX() ||
2956  Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2957  // PC-relative references to external symbols should go through $stub,
2958  // unless we're building with the leopard linker or later, which
2959  // automatically synthesizes these stubs.
2960  OpFlags = X86II::MO_DARWIN_STUB;
2961  }
2962 
2963  Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2964  OpFlags);
2965  }
2966 
2967  // Returns a chain & a flag for retval copy to use.
2968  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2969  SmallVector<SDValue, 8> Ops;
2970 
2971  if (!IsSibcall && isTailCall) {
2972  Chain = DAG.getCALLSEQ_END(Chain,
2973  DAG.getIntPtrConstant(NumBytesToPop, true),
2974  DAG.getIntPtrConstant(0, true), InFlag, dl);
2975  InFlag = Chain.getValue(1);
2976  }
2977 
2978  Ops.push_back(Chain);
2979  Ops.push_back(Callee);
2980 
2981  if (isTailCall)
2982  Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2983 
2984  // Add argument registers to the end of the list so that they are known live
2985  // into the call.
2986  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2987  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2988  RegsToPass[i].second.getValueType()));
2989 
2990  // Add a register mask operand representing the call-preserved registers.
2991  const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
2992  const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2993  assert(Mask && "Missing call preserved mask for calling convention");
2994  Ops.push_back(DAG.getRegisterMask(Mask));
2995 
2996  if (InFlag.getNode())
2997  Ops.push_back(InFlag);
2998 
2999  if (isTailCall) {
3000  // We used to do:
3001  //// If this is the first return lowered for this function, add the regs
3002  //// to the liveout set for the function.
3003  // This isn't right, although it's probably harmless on x86; liveouts
3004  // should be computed from returns not tail calls. Consider a void
3005  // function making a tail call to a function returning int.
3006  return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3007  }
3008 
3009  Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3010  InFlag = Chain.getValue(1);
3011 
3012  // Create the CALLSEQ_END node.
3013  unsigned NumBytesForCalleeToPop;
3014  if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3015  DAG.getTarget().Options.GuaranteedTailCallOpt))
3016  NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3017  else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3018  !Subtarget->getTargetTriple().isOSMSVCRT() &&
3019  SR == StackStructReturn)
3020  // If this is a call to a struct-return function, the callee
3021  // pops the hidden struct pointer, so we have to push it back.
3022  // This is common for Darwin/X86, Linux & Mingw32 targets.
3023  // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3024  NumBytesForCalleeToPop = 4;
3025  else
3026  NumBytesForCalleeToPop = 0; // Callee pops nothing.
3027 
3028  // Returns a flag for retval copy to use.
3029  if (!IsSibcall) {
3030  Chain = DAG.getCALLSEQ_END(Chain,
3031  DAG.getIntPtrConstant(NumBytesToPop, true),
3032  DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3033  true),
3034  InFlag, dl);
3035  InFlag = Chain.getValue(1);
3036  }
3037 
3038  // Handle result values, copying them out of physregs into vregs that we
3039  // return.
3040  return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3041  Ins, dl, DAG, InVals);
3042 }
llvm::X86TargetLowering::LowerCallResult
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
Definition: X86ISelLowering.cpp:2052
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:133
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Definition: SelectionDAG.h:612
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Definition: TargetMachine.cpp:76
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:144
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(CallingConv::ID) const
Definition: TargetRegisterInfo.h:444
getMOVL
static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1, SDValue V2)
Definition: X86ISelLowering.cpp:4966
llvm::GlobalAddressSDNode::getGlobal
const GlobalValue * getGlobal() const
Definition: SelectionDAGNodes.h:1418
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm::X86TargetLowering::LowerExternalSymbol
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10212
llvm::MachineFunction::getFunction
const Function * getFunction() const
Definition: MachineFunction.h:151
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.cpp:1441
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:135
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
Definition: MachineInstr.cpp:414
llvm::Triple::isMacOSX
bool isMacOSX() const
Definition: Triple.h:350
llvm::GlobalValue::hasDefaultVisibility
bool hasDefaultVisibility() const
Definition: GlobalValue.h:121
EmitTailCallStoreRetAddr
static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT, unsigned SlotSize, int FPDiff, SDLoc dl)
Definition: X86ISelLowering.cpp:2566
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
llvm::X86Subtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:368
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::CallingConv::ID
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
llvm::X86TargetLowering::IsEligibleForTailCallOptimization
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:3158
G
#define G(x, y, z)
Definition: MD5.cpp:52
llvm::TargetLowering::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 32 > Ins
Definition: TargetLowering.h:2155
llvm::X86TargetLowering::LowerMemOpCallTo
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const
Definition: X86ISelLowering.cpp:2531
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Definition: SelectionDAG.h:603
llvm::Triple::isMacOSXVersionLT
unsigned isMacOSXVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
Definition: Triple.h:335
llvm::CCValAssign::getLocReg
unsigned getLocReg() const
Definition: CallingConvLower.h:140
llvm::SmallVectorBase::empty
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
llvm::SelectionDAG::getRegisterMask
SDValue getRegisterMask(const uint32_t *RegMask)
Definition: SelectionDAG.cpp:1661
llvm::Function::hasStructRetAttr
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
Definition: Function.h:305
llvm::MCPhysReg
uint16_t MCPhysReg
Definition: MCRegisterInfo.h:27
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::X86Subtarget::isPICStyleRIPRel
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:417
llvm::TargetLowering::CallLoweringInfo::Outs
SmallVector< ISD::OutputArg, 32 > Outs
Definition: TargetLowering.h:2153
llvm::X86Subtarget::isPICStyleStubAny
bool isPICStyleStubAny() const
Definition: X86Subtarget.h:426
llvm::SelectionDAG::getUNDEF
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
IsTailCallConvention
static bool IsTailCallConvention(CallingConv::ID CC)
Definition: X86ISelLowering.cpp:2172
llvm::GlobalValue::isWeakForLinker
static bool isWeakForLinker(LinkageTypes Linkage)
Definition: GlobalValue.h:235
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::X86Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:431
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Definition: TargetMachine.cpp:84
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:142
llvm::GlobalValue::hasHiddenVisibility
bool hasHiddenVisibility() const
Definition: GlobalValue.h:122
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
Definition: TargetOptions.h:148
llvm::X86TargetLowering::GetAlignedArgumentStackSize
unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:3078
llvm::X86Subtarget::isPICStyleGOT
bool isPICStyleGOT() const
Definition: X86Subtarget.h:416
llvm::X86TargetLowering::EmitTailCallLoadRetAddr
SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall, bool Is64Bit, int FPDiff, SDLoc dl) const
Definition: X86ISelLowering.cpp:2550
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
Definition: SelectionDAG.cpp:4815
llvm::SelectionDAG::CreateStackTemporary
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Definition: SelectionDAG.cpp:1782
llvm::X86RegisterInfo::getStackRegister
unsigned getStackRegister() const
Definition: X86RegisterInfo.h:125
callIsStructReturn
static StructReturnType callIsStructReturn(const SmallVectorImpl< ISD::OutputArg > &Outs)
Definition: X86ISelLowering.cpp:2128
llvm::GlobalValue::hasDLLImportStorageClass
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:148
llvm::X86Subtarget::isTargetELF
bool isTargetELF() const
Definition: X86Subtarget.h:378
StructReturnType
StructReturnType
Definition: X86ISelLowering.cpp:2122
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:136
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::dyn_cast
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:311
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT()
Definition: MachineInstr.cpp:422
llvm::SelectionDAG::getStackArgumentTokenFactor
SDValue getStackArgumentTokenFactor(SDValue Chain)
Definition: SelectionDAG.cpp:3705
llvm::TargetLowering::CallLoweringInfo::OutVals
SmallVector< SDValue, 32 > OutVals
Definition: TargetLowering.h:2154
llvm::GlobalValue::isDeclaration
bool isDeclaration() const
Definition: Globals.cpp:113
llvm::Triple::isOSMSVCRT
bool isOSMSVCRT() const
Is this a "Windows" OS targeting a "MSVCRT.dll" environment.
Definition: Triple.h:398
llvm::GlobalValue::hasProtectedVisibility
bool hasProtectedVisibility() const
Definition: GlobalValue.h:123
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
llvm::X86RegisterInfo::getSlotSize
unsigned getSlotSize() const
Definition: X86RegisterInfo.h:128
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::GlobalValue::hasLocalLinkage
bool hasLocalLinkage() const
Definition: GlobalValue.h:261
llvm::EVT::is128BitVector
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:136
llvm::X86::isCalleePop
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool TailCallOpt)
Definition: X86ISelLowering.cpp:3511
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1297
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:1647
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:141
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
Definition: MachineFunction.cpp:563
llvm::X86TargetLowering::LowerGlobalAddress
SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl, int64_t Offset, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10286
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, unsigned Align)
Definition: CallingConvLower.h:379
CreateCopyOfByValArgument
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl)
Definition: X86ISelLowering.cpp:2160
SDValue X86TargetLowering::LowerCallResult ( SDValue  Chain,
SDValue  InFlag,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  dl,
SelectionDAG &  DAG,
SmallVectorImpl< SDValue > &  InVals 
) const
private

LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate physical registers.

Definition at line 2052 of file X86ISelLowering.cpp.

2056  {
2057 
2058  // Assign locations to each value returned by this call.
2059  SmallVector<CCValAssign, 16> RVLocs;
2060  bool Is64Bit = Subtarget->is64Bit();
2061  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2062  DAG.getTarget(), RVLocs, *DAG.getContext());
2063  CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2064 
2065  // Copy all of the result registers out of their specified physreg.
2066  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2067  CCValAssign &VA = RVLocs[i];
2068  EVT CopyVT = VA.getValVT();
2069 
2070  // If this is x86-64, and we disabled SSE, we can't return FP values
2071  if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2072  ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2073  report_fatal_error("SSE register return with SSE disabled");
2074  }
2075 
2076  SDValue Val;
2077 
2078  // If this is a call to a function that returns an fp value on the floating
2079  // point stack, we must guarantee the value is popped from the stack, so
2080  // a CopyFromReg is not good enough - the copy instruction may be eliminated
2081  // if the return value is not used. We use the FpPOP_RETVAL instruction
2082  // instead.
2083  if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2084  // If we prefer to use the value in xmm registers, copy it out as f80 and
2085  // use a truncate to move it from fp stack reg to xmm reg.
2086  if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2087  SDValue Ops[] = { Chain, InFlag };
2088  Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2089  MVT::Other, MVT::Glue, Ops), 1);
2090  Val = Chain.getValue(0);
2091 
2092  // Round the f80 to the right size, which also moves it to the appropriate
2093  // xmm register.
2094  if (CopyVT != VA.getValVT())
2095  Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2096  // This truncation won't change the value.
2097  DAG.getIntPtrConstant(1));
2098  } else {
2099  Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2100  CopyVT, InFlag).getValue(1);
2101  Val = Chain.getValue(0);
2102  }
2103  InFlag = Chain.getValue(2);
2104  InVals.push_back(Val);
2105  }
2106 
2107  return Chain;
2108 }
llvm::CCState::AnalyzeCallResult
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
Definition: CallingConvLower.cpp:155
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:133
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Definition: ErrorHandling.cpp:60
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::CCValAssign::getLocReg
unsigned getLocReg() const
Definition: CallingConvLower.h:140
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:311
llvm::SelectionDAG::getMachineNode
MachineSDNode * getMachineNode(unsigned Opcode, SDLoc dl, EVT VT)
Definition: SelectionDAG.cpp:5599
llvm::X86TargetLowering::isScalarFPTypeInSSEReg
bool isScalarFPTypeInSSEReg(EVT VT) const
Definition: X86ISelLowering.h:752
std::pair< SDValue, SDValue > TargetLowering::LowerCallTo ( TargetLowering::CallLoweringInfo &  CLI) const
inherited

This function lowers an abstract call to a function into an actual call. This returns a pair of operands. The first element is the return value for the function (if RetTy is not VoidTy). The second element is the outgoing token chain. It calls LowerCall to do the actual lowering.

TargetLowering::LowerCallTo - This is the default LowerCallTo implementation, which just calls LowerCall. FIXME: When all targets are migrated to using LowerCall, this hook should be integrated into SDISel.

Definition at line 7072 of file SelectionDAGBuilder.cpp.

7072  {
7073  // Handle the incoming return values from the call.
7074  CLI.Ins.clear();
7075  Type *OrigRetTy = CLI.RetTy;
7076  SmallVector<EVT, 4> RetTys;
7077  SmallVector<uint64_t, 4> Offsets;
7078  ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7079 
7080  SmallVector<ISD::OutputArg, 4> Outs;
7081  GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7082 
7083  bool CanLowerReturn =
7084  this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7085  CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7086 
7087  SDValue DemoteStackSlot;
7088  int DemoteStackIdx = -100;
7089  if (!CanLowerReturn) {
7090  // FIXME: equivalent assert?
7091  // assert(!CS.hasInAllocaArgument() &&
7092  // "sret demotion is incompatible with inalloca");
7093  uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7094  unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7095  MachineFunction &MF = CLI.DAG.getMachineFunction();
7096  DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7097  Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7098 
7099  DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7100  ArgListEntry Entry;
7101  Entry.Node = DemoteStackSlot;
7102  Entry.Ty = StackSlotPtrType;
7103  Entry.isSExt = false;
7104  Entry.isZExt = false;
7105  Entry.isInReg = false;
7106  Entry.isSRet = true;
7107  Entry.isNest = false;
7108  Entry.isByVal = false;
7109  Entry.isReturned = false;
7110  Entry.Alignment = Align;
7111  CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7112  CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7113  } else {
7114  for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7115  EVT VT = RetTys[I];
7116  MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7117  unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7118  for (unsigned i = 0; i != NumRegs; ++i) {
7119  ISD::InputArg MyFlags;
7120  MyFlags.VT = RegisterVT;
7121  MyFlags.ArgVT = VT;
7122  MyFlags.Used = CLI.IsReturnValueUsed;
7123  if (CLI.RetSExt)
7124  MyFlags.Flags.setSExt();
7125  if (CLI.RetZExt)
7126  MyFlags.Flags.setZExt();
7127  if (CLI.IsInReg)
7128  MyFlags.Flags.setInReg();
7129  CLI.Ins.push_back(MyFlags);
7130  }
7131  }
7132  }
7133 
7134  // Handle all of the outgoing arguments.
7135  CLI.Outs.clear();
7136  CLI.OutVals.clear();
7137  ArgListTy &Args = CLI.getArgs();
7138  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7139  SmallVector<EVT, 4> ValueVTs;
7140  ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7141  Type *FinalType = Args[i].Ty;
7142  if (Args[i].isByVal)
7143  FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7144  bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7145  FinalType, CLI.CallConv, CLI.IsVarArg);
7146  for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7147  ++Value) {
7148  EVT VT = ValueVTs[Value];
7149  Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7150  SDValue Op = SDValue(Args[i].Node.getNode(),
7151  Args[i].Node.getResNo() + Value);
7152  ISD::ArgFlagsTy Flags;
7153  unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7154 
7155  if (Args[i].isZExt)
7156  Flags.setZExt();
7157  if (Args[i].isSExt)
7158  Flags.setSExt();
7159  if (Args[i].isInReg)
7160  Flags.setInReg();
7161  if (Args[i].isSRet)
7162  Flags.setSRet();
7163  if (Args[i].isByVal)
7164  Flags.setByVal();
7165  if (Args[i].isInAlloca) {
7166  Flags.setInAlloca();
7167  // Set the byval flag for CCAssignFn callbacks that don't know about
7168  // inalloca. This way we can know how many bytes we should've allocated
7169  // and how many bytes a callee cleanup function will pop. If we port
7170  // inalloca to more targets, we'll have to add custom inalloca handling
7171  // in the various CC lowering callbacks.
7172  Flags.setByVal();
7173  }
7174  if (Args[i].isByVal || Args[i].isInAlloca) {
7175  PointerType *Ty = cast<PointerType>(Args[i].Ty);
7176  Type *ElementTy = Ty->getElementType();
7177  Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7178  // For ByVal, alignment should come from FE. BE will guess if this
7179  // info is not there but there are cases it cannot get right.
7180  unsigned FrameAlign;
7181  if (Args[i].Alignment)
7182  FrameAlign = Args[i].Alignment;
7183  else
7184  FrameAlign = getByValTypeAlignment(ElementTy);
7185  Flags.setByValAlign(FrameAlign);
7186  }
7187  if (Args[i].isNest)
7188  Flags.setNest();
7189  if (NeedsRegBlock)
7190  Flags.setInConsecutiveRegs();
7191  Flags.setOrigAlign(OriginalAlignment);
7192 
7193  MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7194  unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7195  SmallVector<SDValue, 4> Parts(NumParts);
7196  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7197 
7198  if (Args[i].isSExt)
7199  ExtendKind = ISD::SIGN_EXTEND;
7200  else if (Args[i].isZExt)
7201  ExtendKind = ISD::ZERO_EXTEND;
7202 
7203  // Conservatively only handle 'returned' on non-vectors for now
7204  if (Args[i].isReturned && !Op.getValueType().isVector()) {
7205  assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7206  "unexpected use of 'returned'");
7207  // Before passing 'returned' to the target lowering code, ensure that
7208  // either the register MVT and the actual EVT are the same size or that
7209  // the return value and argument are extended in the same way; in these
7210  // cases it's safe to pass the argument register value unchanged as the
7211  // return register value (although it's at the target's option whether
7212  // to do so)
7213  // TODO: allow code generation to take advantage of partially preserved
7214  // registers rather than clobbering the entire register when the
7215  // parameter extension method is not compatible with the return
7216  // extension method
7217  if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7218  (ExtendKind != ISD::ANY_EXTEND &&
7219  CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7220  Flags.setReturned();
7221  }
7222 
7223  getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7224  CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7225 
7226  for (unsigned j = 0; j != NumParts; ++j) {
7227  // if it isn't first piece, alignment must be 1
7228  ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7229  i < CLI.NumFixedArgs,
7230  i, j*Parts[j].getValueType().getStoreSize());
7231  if (NumParts > 1 && j == 0)
7232  MyFlags.Flags.setSplit();
7233  else if (j != 0)
7234  MyFlags.Flags.setOrigAlign(1);
7235 
7236  // Only mark the end at the last register of the last value.
7237  if (NeedsRegBlock && Value == NumValues - 1 && j == NumParts - 1)
7238  MyFlags.Flags.setInConsecutiveRegsLast();
7239 
7240  CLI.Outs.push_back(MyFlags);
7241  CLI.OutVals.push_back(Parts[j]);
7242  }
7243  }
7244  }
7245 
7246  SmallVector<SDValue, 4> InVals;
7247  CLI.Chain = LowerCall(CLI, InVals);
7248 
7249  // Verify that the target's LowerCall behaved as expected.
7250  assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7251  "LowerCall didn't return a valid chain!");
7252  assert((!CLI.IsTailCall || InVals.empty()) &&
7253  "LowerCall emitted a return value for a tail call!");
7254  assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7255  "LowerCall didn't emit the correct number of values!");
7256 
7257  // For a tail call, the return value is merely live-out and there aren't
7258  // any nodes in the DAG representing it. Return a special value to
7259  // indicate that a tail call has been emitted and no more Instructions
7260  // should be processed in the current block.
7261  if (CLI.IsTailCall) {
7262  CLI.DAG.setRoot(CLI.Chain);
7263  return std::make_pair(SDValue(), SDValue());
7264  }
7265 
7266  DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7267  assert(InVals[i].getNode() &&
7268  "LowerCall emitted a null value!");
7269  assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7270  "LowerCall emitted a value with the wrong type!");
7271  });
7272 
7273  SmallVector<SDValue, 4> ReturnValues;
7274  if (!CanLowerReturn) {
7275  // The instruction result is the result of loading from the
7276  // hidden sret parameter.
7277  SmallVector<EVT, 1> PVTs;
7278  Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7279 
7280  ComputeValueVTs(*this, PtrRetTy, PVTs);
7281  assert(PVTs.size() == 1 && "Pointers should fit in one register");
7282  EVT PtrVT = PVTs[0];
7283 
7284  unsigned NumValues = RetTys.size();
7285  ReturnValues.resize(NumValues);
7286  SmallVector<SDValue, 4> Chains(NumValues);
7287 
7288  for (unsigned i = 0; i < NumValues; ++i) {
7289  SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7290  CLI.DAG.getConstant(Offsets[i], PtrVT));
7291  SDValue L = CLI.DAG.getLoad(
7292  RetTys[i], CLI.DL, CLI.Chain, Add,
7293  MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7294  false, false, 1);
7295  ReturnValues[i] = L;
7296  Chains[i] = L.getValue(1);
7297  }
7298 
7299  CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7300  } else {
7301  // Collect the legal value parts into potentially illegal values
7302  // that correspond to the original function's return values.
7303  ISD::NodeType AssertOp = ISD::DELETED_NODE;
7304  if (CLI.RetSExt)
7305  AssertOp = ISD::AssertSext;
7306  else if (CLI.RetZExt)
7307  AssertOp = ISD::AssertZext;
7308  unsigned CurReg = 0;
7309  for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7310  EVT VT = RetTys[I];
7311  MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7312  unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7313 
7314  ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7315  NumRegs, RegisterVT, VT, nullptr,
7316  AssertOp));
7317  CurReg += NumRegs;
7318  }
7319 
7320  // For a function returning void, there is no return value. We can't create
7321  // such a node, so we just return a null return value in that case. In
7322  // that case, nothing will actually look at the value.
7323  if (ReturnValues.empty())
7324  return std::make_pair(SDValue(), CLI.Chain);
7325  }
7326 
7327  SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7328  CLI.DAG.getVTList(RetTys), ReturnValues);
7329  return std::make_pair(Res, CLI.Chain);
7330 }
llvm::SmallVectorTemplateBase::push_back
void push_back(const T &Elt)
Definition: SmallVector.h:225
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::TargetLoweringBase::getNumRegisters
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Definition: TargetLowering.h:703
llvm::DataLayout::getPrefTypeAlignment
unsigned getPrefTypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:693
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm::TargetLowering::functionArgumentNeedsConsecutiveRegisters
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const
Definition: TargetLowering.h:2337
llvm::SelectionDAG::setRoot
const SDValue & setRoot(SDValue N)
Definition: SelectionDAG.h:333
llvm::TargetLoweringBase::getValueType
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
Definition: TargetLowering.h:638
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
Definition: MachineInstr.cpp:414
MyFlags
MyFlags
Definition: YAMLIOTest.cpp:502
llvm::EVT::isVector
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::TargetLowering::CallLoweringInfo::Ins
SmallVector< ISD::InputArg, 32 > Ins
Definition: TargetLowering.h:2155
Value
static int Value(bit_value_t V)
Definition: FixedLenDecoderEmitter.cpp:140
llvm::Type::getContext
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
llvm::SmallVectorBase::empty
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
Node
const DomTreeNodeT * Node
Definition: DominanceFrontierImpl.h:37
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::TargetLowering::CallLoweringInfo::Outs
SmallVector< ISD::OutputArg, 32 > Outs
Definition: TargetLowering.h:2153
llvm::TargetLowering::LowerCall
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
Definition: TargetLowering.h:2260
llvm::ISD::ArgFlagsTy::setOrigAlign
void setOrigAlign(unsigned A)
Definition: TargetCallingConv.h:109
llvm::SequentialType::getElementType
Type * getElementType() const
Definition: DerivedTypes.h:319
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::GetReturnInfo
void GetReturnInfo(Type *ReturnType, AttributeSet attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI)
Definition: TargetLoweringBase.cpp:1296
assert
assert(Globals.size() > 1)
llvm::Type::getVoidTy
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:221
llvm::TargetLoweringBase::getDataLayout
const DataLayout * getDataLayout() const
Definition: TargetLowering.h:150
llvm::TargetLoweringBase::getRegisterType
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
Definition: TargetLowering.h:669
llvm::TargetLoweringBase::getByValTypeAlignment
virtual unsigned getByValTypeAlignment(Type *Ty) const
Definition: TargetLoweringBase.cpp:1345
DEBUG
#define DEBUG(X)
Definition: include/llvm/Support/Debug.h:93
llvm::TargetLowering::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:2126
llvm::DataLayout::getABITypeAlignment
unsigned getABITypeAlignment(Type *Ty) const
Definition: DataLayout.cpp:683
llvm::PointerType::getUnqual
static PointerType * getUnqual(Type *ElementType)
Definition: DerivedTypes.h:456
Args
const char * Args[]
Definition: OptionParsingTest.cpp:55
llvm::DataLayout::getTypeAllocSize
uint64_t getTypeAllocSize(Type *Ty) const
Definition: DataLayout.h:368
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
getCopyToParts
static void getCopyToParts(SelectionDAG &DAG, SDLoc DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, ISD::NodeType ExtendKind=ISD::ANY_EXTEND)
Definition: SelectionDAGBuilder.cpp:346
Align
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
getCopyFromParts
static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, ISD::NodeType AssertOp=ISD::DELETED_NODE)
Definition: SelectionDAGBuilder.cpp:102
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
getReturnAttrs
static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI)
Definition: SelectionDAGBuilder.cpp:7054
llvm::TargetLowering::CanLowerReturn
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
Definition: TargetLowering.h:2271
llvm::TargetLowering::CallLoweringInfo::OutVals
SmallVector< SDValue, 32 > OutVals
Definition: TargetLowering.h:2154
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
Definition: CodeGen/Analysis.cpp:75
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
I
#define I(x, y, z)
Definition: MD5.cpp:54
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Definition: MachineFunction.cpp:513
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1297
llvm::Value
LLVM Value Representation.
Definition: Value.h:69
SDValue X86TargetLowering::LowerConstantPool ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 10146 of file X86ISelLowering.cpp.

10146  {
10147  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10148 
10149  // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10150  // global base reg.
10151  unsigned char OpFlag = 0;
10152  unsigned WrapperKind = X86ISD::Wrapper;
10153  CodeModel::Model M = DAG.getTarget().getCodeModel();
10154 
10155  if (Subtarget->isPICStyleRIPRel() &&
10156  (M == CodeModel::Small || M == CodeModel::Kernel))
10157  WrapperKind = X86ISD::WrapperRIP;
10158  else if (Subtarget->isPICStyleGOT())
10159  OpFlag = X86II::MO_GOTOFF;
10160  else if (Subtarget->isPICStyleStubPIC())
10161  OpFlag = X86II::MO_PIC_BASE_OFFSET;
10162 
10163  SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10164  CP->getAlignment(),
10165  CP->getOffset(), OpFlag);
10166  SDLoc DL(CP);
10167  Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10168  // With PIC, the address is actually $g + Offset.
10169  if (OpFlag) {
10170  Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10171  DAG.getNode(X86ISD::GlobalBaseReg,
10172  SDLoc(), getPointerTy()),
10173  Result);
10174  }
10175 
10176  return Result;
10177 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::X86Subtarget::isPICStyleRIPRel
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:417
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Definition: TargetMachine.cpp:84
llvm::X86Subtarget::isPICStyleStubPIC
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:419
llvm::ConstantPoolSDNode::getConstVal
const Constant * getConstVal() const
Definition: SelectionDAGNodes.h:1500
llvm::X86Subtarget::isPICStyleGOT
bool isPICStyleGOT() const
Definition: X86Subtarget.h:416
llvm::SelectionDAG::getTargetConstantPool
SDValue getTargetConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:450
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::ConstantPoolSDNode::getAlignment
unsigned getAlignment() const
Definition: SelectionDAGNodes.h:1516
const MCExpr * X86TargetLowering::LowerCustomJumpTableEntry ( const MachineJumpTableInfo *  MJTI,
const MachineBasicBlock *  MBB,
unsigned  uid,
MCContext &  Ctx 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 1768 of file X86ISelLowering.cpp.

1770  {
1771  assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1772  Subtarget->isPICStyleGOT());
1773  // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1774  // entries.
1775  return MCSymbolRefExpr::Create(MBB->getSymbol(),
1776  MCSymbolRefExpr::VK_GOTOFF, Ctx);
1777 }
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Definition: MachineBasicBlock.h:137
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Definition: TargetMachine.cpp:76
llvm::MCSymbolRefExpr::Create
static const MCSymbolRefExpr * Create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:293
assert
assert(Globals.size() > 1)
llvm::X86Subtarget::isPICStyleGOT
bool isPICStyleGOT() const
Definition: X86Subtarget.h:416
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Definition: MachineBasicBlock.cpp:52
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
SDValue X86TargetLowering::LowerDYNAMIC_STACKALLOC ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 13124 of file X86ISelLowering.cpp.

13125  {
13126  MachineFunction &MF = DAG.getMachineFunction();
13127  bool SplitStack = MF.shouldSplitStack();
13128  bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
13129  SplitStack;
13130  SDLoc dl(Op);
13131 
13132  if (!Lower) {
13133  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13134  SDNode* Node = Op.getNode();
13135 
13136  unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
13137  assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
13138  " not tell us which reg is the stack pointer!");
13139  EVT VT = Node->getValueType(0);
13140  SDValue Tmp1 = SDValue(Node, 0);
13141  SDValue Tmp2 = SDValue(Node, 1);
13142  SDValue Tmp3 = Node->getOperand(2);
13143  SDValue Chain = Tmp1.getOperand(0);
13144 
13145  // Chain the dynamic stack allocation so that it doesn't modify the stack
13146  // pointer when other instructions are using the stack.
13147  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
13148  SDLoc(Node));
13149 
13150  SDValue Size = Tmp2.getOperand(1);
13151  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
13152  Chain = SP.getValue(1);
13153  unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
13154  const TargetFrameLowering &TFI = *DAG.getTarget().getFrameLowering();
13155  unsigned StackAlign = TFI.getStackAlignment();
13156  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
13157  if (Align > StackAlign)
13158  Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
13159  DAG.getConstant(-(uint64_t)Align, VT));
13160  Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
13161 
13162  Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
13163  DAG.getIntPtrConstant(0, true), SDValue(),
13164  SDLoc(Node));
13165 
13166  SDValue Ops[2] = { Tmp1, Tmp2 };
13167  return DAG.getMergeValues(Ops, dl);
13168  }
13169 
13170  // Get the inputs.
13171  SDValue Chain = Op.getOperand(0);
13172  SDValue Size = Op.getOperand(1);
13173  unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
13174  EVT VT = Op.getNode()->getValueType(0);
13175 
13176  bool Is64Bit = Subtarget->is64Bit();
13177  EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
13178 
13179  if (SplitStack) {
13180  MachineRegisterInfo &MRI = MF.getRegInfo();
13181 
13182  if (Is64Bit) {
13183  // The 64 bit implementation of segmented stacks needs to clobber both r10
13184  // r11. This makes it impossible to use it along with nested parameters.
13185  const Function *F = MF.getFunction();
13186 
13187  for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
13188  I != E; ++I)
13189  if (I->hasNestAttr())
13190  report_fatal_error("Cannot use segmented stacks with functions that "
13191  "have nested arguments.");
13192  }
13193 
13194  const TargetRegisterClass *AddrRegClass =
13195  getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
13196  unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
13197  Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
13198  SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
13199  DAG.getRegister(Vreg, SPTy));
13200  SDValue Ops1[2] = { Value, Chain };
13201  return DAG.getMergeValues(Ops1, dl);
13202  } else {
13203  SDValue Flag;
13204  unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
13205 
13206  Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
13207  Flag = Chain.getValue(1);
13208  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13209 
13210  Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
13211 
13212  const X86RegisterInfo *RegInfo =
13213  static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
13214  unsigned SPReg = RegInfo->getStackRegister();
13215  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
13216  Chain = SP.getValue(1);
13217 
13218  if (Align) {
13219  SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
13220  DAG.getConstant(-(uint64_t)Align, VT));
13221  Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
13222  }
13223 
13224  SDValue Ops1[2] = { SP, Chain };
13225  return DAG.getMergeValues(Ops1, dl);
13226  }
13227 }
llvm::TargetFrameLowering::getStackAlignment
unsigned getStackAlignment() const
Definition: TargetFrameLowering.h:70
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
llvm::SelectionDAG::getCALLSEQ_END
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, SDLoc DL)
Definition: SelectionDAG.h:612
llvm::MachineRegisterInfo::createVirtualRegister
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
Definition: MachineRegisterInfo.cpp:97
llvm::SelectionDAG::getMergeValues
SDValue getMergeValues(ArrayRef< SDValue > Ops, SDLoc dl)
getMergeValues - Create a MERGE_VALUES node from the given operands.
Definition: SelectionDAG.cpp:4574
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::X86Subtarget::isTargetMacho
bool isTargetMacho() const
Definition: X86Subtarget.h:380
llvm::Function::arg_end
arg_iterator arg_end()
Definition: Function.h:425
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:592
F
F(f)
llvm::MachineFunction::getFunction
const Function * getFunction() const
Definition: MachineFunction.h:151
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Definition: ErrorHandling.cpp:60
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Definition: SelectionDAGNodes.h:648
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:429
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::SelectionDAG::getCALLSEQ_START
SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL)
Definition: SelectionDAG.h:603
Value
static int Value(bit_value_t V)
Definition: FixedLenDecoderEmitter.cpp:140
Node
const DomTreeNodeT * Node
Definition: DominanceFrontierImpl.h:37
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::MachineFunction::shouldSplitStack
bool shouldSplitStack()
Should we be emitting segmented stack stuff for the function.
Definition: MachineFunction.cpp:129
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
llvm::Function::arg_begin
arg_iterator arg_begin()
Definition: Function.h:417
llvm::X86Subtarget::isOSWindows
bool isOSWindows() const
Definition: X86Subtarget.h:405
llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore
unsigned getStackPointerRegisterToSaveRestore() const
Definition: TargetLowering.h:839
llvm::TargetMachine::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: Target/TargetMachine.h:119
llvm::X86RegisterInfo::getStackRegister
unsigned getStackRegister() const
Definition: X86RegisterInfo.h:125
llvm::ilist_iterator
Definition: ilist.h:50
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
Align
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Definition: TargetLowering.h:314
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
Definition: MachineFunction.h:167
I
#define I(x, y, z)
Definition: MD5.cpp:54
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::Value
LLVM Value Representation.
Definition: Value.h:69
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:1647
llvm::SelectionDAG::getTargetLoweringInfo
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
SDValue X86TargetLowering::LowerEH_RETURN ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 14648 of file X86ISelLowering.cpp.

14648  {
14649  SDValue Chain = Op.getOperand(0);
14650  SDValue Offset = Op.getOperand(1);
14651  SDValue Handler = Op.getOperand(2);
14652  SDLoc dl (Op);
14653 
14654  EVT PtrVT = getPointerTy();
14655  const X86RegisterInfo *RegInfo =
14656  static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14657  unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
14658  assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
14659  (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
14660  "Invalid Frame Register!");
14661  SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
14662  unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
14663 
14664  SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
14665  DAG.getIntPtrConstant(RegInfo->getSlotSize()));
14666  StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
14667  Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
14668  false, false, 0);
14669  Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
14670 
14671  return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
14672  DAG.getRegister(StoreAddrReg, PtrVT));
14673 }
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
assert
assert(Globals.size() > 1)
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
Definition: SelectionDAG.cpp:4815
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::X86RegisterInfo::getSlotSize
unsigned getSlotSize() const
Definition: X86RegisterInfo.h:128
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:1647
llvm::X86RegisterInfo::getFrameRegister
unsigned getFrameRegister(const MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:528
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 14683 of file X86ISelLowering.cpp.

14684  {
14685  SDLoc DL(Op);
14686  return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
14687  Op.getOperand(0), Op.getOperand(1));
14688 }
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 14675 of file X86ISelLowering.cpp.

14676  {
14677  SDLoc DL(Op);
14678  return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
14679  DAG.getVTList(MVT::i32, MVT::Other),
14680  Op.getOperand(0), Op.getOperand(1));
14681 }
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
SDValue X86TargetLowering::LowerExternalSymbol ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 10212 of file X86ISelLowering.cpp.

10212  {
10213  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10214 
10215  // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10216  // global base reg.
10217  unsigned char OpFlag = 0;
10218  unsigned WrapperKind = X86ISD::Wrapper;
10219  CodeModel::Model M = DAG.getTarget().getCodeModel();
10220 
10221  if (Subtarget->isPICStyleRIPRel() &&
10222  (M == CodeModel::Small || M == CodeModel::Kernel)) {
10223  if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10224  OpFlag = X86II::MO_GOTPCREL;
10225  WrapperKind = X86ISD::WrapperRIP;
10226  } else if (Subtarget->isPICStyleGOT()) {
10227  OpFlag = X86II::MO_GOT;
10228  } else if (Subtarget->isPICStyleStubPIC()) {
10229  OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10230  } else if (Subtarget->isPICStyleStubNoDynamic()) {
10231  OpFlag = X86II::MO_DARWIN_NONLAZY;
10232  }
10233 
10234  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10235 
10236  SDLoc DL(Op);
10237  Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10238 
10239  // With PIC, the address is actually $g + Offset.
10240  if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10241  !Subtarget->is64Bit()) {
10242  Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10243  DAG.getNode(X86ISD::GlobalBaseReg,
10244  SDLoc(), getPointerTy()),
10245  Result);
10246  }
10247 
10248  // For symbols that require a load from a stub to get the address, emit the
10249  // load.
10250  if (isGlobalStubReference(OpFlag))
10251  Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10252  MachinePointerInfo::getGOT(), false, false, false, 0);
10253 
10254  return Result;
10255 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Definition: TargetMachine.cpp:76
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::SelectionDAG::getTargetExternalSymbol
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.cpp:1441
llvm::X86Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: X86Subtarget.h:370
llvm::isGlobalStubReference
static bool isGlobalStubReference(unsigned char TargetFlag)
Definition: X86InstrInfo.h:85
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::X86Subtarget::isPICStyleRIPRel
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:417
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Definition: TargetMachine.cpp:84
llvm::X86Subtarget::isPICStyleStubPIC
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:419
llvm::X86Subtarget::isPICStyleStubNoDynamic
bool isPICStyleStubNoDynamic() const
Definition: X86Subtarget.h:423
llvm::X86Subtarget::isPICStyleGOT
bool isPICStyleGOT() const
Definition: X86Subtarget.h:416
llvm::X86Subtarget::isTargetELF
bool isTargetELF() const
Definition: X86Subtarget.h:378
getSymbol
static void getSymbol(const MachOObjectFile *Obj, DataRefImpl DRI, MachOSymbol &Symbol)
Definition: MachODumper.cpp:187
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT()
Definition: MachineInstr.cpp:422
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue X86TargetLowering::LowerEXTRACT_VECTOR_ELT ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 9804 of file X86ISelLowering.cpp.

9805  {
9806  SDLoc dl(Op);
9807  SDValue Vec = Op.getOperand(0);
9808  MVT VecVT = Vec.getSimpleValueType();
9809  SDValue Idx = Op.getOperand(1);
9810 
9811  if (Op.getSimpleValueType() == MVT::i1)
9812  return ExtractBitFromMaskVector(Op, DAG);
9813 
9814  if (!isa<ConstantSDNode>(Idx)) {
9815  if (VecVT.is512BitVector() ||
9816  (VecVT.is256BitVector() && Subtarget->hasInt256() &&
9817  VecVT.getVectorElementType().getSizeInBits() == 32)) {
9818 
9819  MVT MaskEltVT =
9820  MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
9821  MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
9822  MaskEltVT.getSizeInBits());
9823 
9824  Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
9825  SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
9826  getZeroVector(MaskVT, Subtarget, DAG, dl),
9827  Idx, DAG.getConstant(0, getPointerTy()));
9828  SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
9829  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
9830  Perm, DAG.getConstant(0, getPointerTy()));
9831  }
9832  return SDValue();
9833  }
9834 
9835  // If this is a 256-bit vector result, first extract the 128-bit vector and
9836  // then extract the element from the 128-bit vector.
9837  if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
9838 
9839  unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9840  // Get the 128-bit vector.
9841  Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
9842  MVT EltVT = VecVT.getVectorElementType();
9843 
9844  unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
9845 
9846  //if (IdxVal >= NumElems/2)
9847  // IdxVal -= NumElems/2;
9848  IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
9849  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
9850  DAG.getConstant(IdxVal, MVT::i32));
9851  }
9852 
9853  assert(VecVT.is128BitVector() && "Unexpected vector length");
9854 
9855  if (Subtarget->hasSSE41()) {
9856  SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
9857  if (Res.getNode())
9858  return Res;
9859  }
9860 
9861  MVT VT = Op.getSimpleValueType();
9862  // TODO: handle v16i8.
9863  if (VT.getSizeInBits() == 16) {
9864  SDValue Vec = Op.getOperand(0);
9865  unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9866  if (Idx == 0)
9867  return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
9868  DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9869  DAG.getNode(ISD::BITCAST, dl,
9870  MVT::v4i32, Vec),
9871  Op.getOperand(1)));
9872  // Transform it so it match pextrw which produces a 32-bit result.
9873  MVT EltVT = MVT::i32;
9874  SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
9875  Op.getOperand(0), Op.getOperand(1));
9876  SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
9877  DAG.getValueType(VT));
9878  return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9879  }
9880 
9881  if (VT.getSizeInBits() == 32) {
9882  unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9883  if (Idx == 0)
9884  return Op;
9885 
9886  // SHUFPS the element to the lowest double word, then movss.
9887  int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
9888  MVT VVT = Op.getOperand(0).getSimpleValueType();
9889  SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
9890  DAG.getUNDEF(VVT), Mask);
9891  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
9892  DAG.getIntPtrConstant(0));
9893  }
9894 
9895  if (VT.getSizeInBits() == 64) {
9896  // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
9897  // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
9898  // to match extract_elt for f64.
9899  unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9900  if (Idx == 0)
9901  return Op;
9902 
9903  // UNPCKHPD the element to the lowest double word, then movsd.
9904  // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
9905  // to a f64mem, the whole operation is folded into a single MOVHPDmr.
9906  int Mask[2] = { 1, -1 };
9907  MVT VVT = Op.getOperand(0).getSimpleValueType();
9908  SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
9909  DAG.getUNDEF(VVT), Mask);
9910  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
9911  DAG.getIntPtrConstant(0));
9912  }
9913 
9914  return SDValue();
9915 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:486
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:505
getZeroVector
static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget, SelectionDAG &DAG, SDLoc dl)
Definition: X86ISelLowering.cpp:4885
llvm::MVT::is512BitVector
bool is512BitVector() const
is512BitVector - Return true if this is a 512-bit vector type.
Definition: MachineValueType.h:224
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm::X86Subtarget::hasSSE41
bool hasSSE41() const
Definition: X86Subtarget.h:315
LowerEXTRACT_VECTOR_ELT_SSE4
static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:9708
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::X86TargetLowering::ExtractBitFromMaskVector
SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:9773
llvm::SelectionDAG::getVectorShuffle
SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, const int *MaskElts)
Definition: SelectionDAG.cpp:1479
llvm::SelectionDAG::getUNDEF
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
Extract
Extract files back to file system.
Definition: llvm-ar.cpp:110
Extract128BitVector
static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl)
Definition: X86ISelLowering.cpp:118
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::MVT::is128BitVector
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
Definition: MachineValueType.h:210
llvm::X86Subtarget::hasInt256
bool hasInt256() const
Definition: X86Subtarget.h:321
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::MVT::is256BitVector
bool is256BitVector() const
is256BitVector - Return true if this is a 256-bit vector type.
Definition: MachineValueType.h:217
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::SelectionDAG::getZExtOrTrunc
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:1009
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1419
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:264
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
Assert
#define Assert(C, M)
Definition: Lint.cpp:161
SDValue X86TargetLowering::LowerFLT_ROUNDS_ ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 14844 of file X86ISelLowering.cpp.

14845  {
14846  /*
14847  The rounding mode is in bits 11:10 of FPSR, and has the following
14848  settings:
14849  00 Round to nearest
14850  01 Round to -inf
14851  10 Round to +inf
14852  11 Round to 0
14853 
14854  FLT_ROUNDS, on the other hand, expects the following:
14855  -1 Undefined
14856  0 Round to 0
14857  1 Round to nearest
14858  2 Round to +inf
14859  3 Round to -inf
14860 
14861  To perform the conversion, we do:
14862  (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
14863  */
14864 
14865  MachineFunction &MF = DAG.getMachineFunction();
14866  const TargetMachine &TM = MF.getTarget();
14867  const TargetFrameLowering &TFI = *TM.getFrameLowering();
14868  unsigned StackAlignment = TFI.getStackAlignment();
14869  MVT VT = Op.getSimpleValueType();
14870  SDLoc DL(Op);
14871 
14872  // Save FP Control Word to stack slot
14873  int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
14874  SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14875 
14876  MachineMemOperand *MMO =
14877  MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14878  MachineMemOperand::MOStore, 2, 2);
14879 
14880  SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
14881  SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
14882  DAG.getVTList(MVT::Other),
14883  Ops, MVT::i16, MMO);
14884 
14885  // Load FP Control Word from stack slot
14886  SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
14887  MachinePointerInfo(), false, false, false, 0);
14888 
14889  // Transform as necessary
14890  SDValue CWD1 =
14891  DAG.getNode(ISD::SRL, DL, MVT::i16,
14892  DAG.getNode(ISD::AND, DL, MVT::i16,
14893  CWD, DAG.getConstant(0x800, MVT::i16)),
14894  DAG.getConstant(11, MVT::i8));
14895  SDValue CWD2 =
14896  DAG.getNode(ISD::SRL, DL, MVT::i16,
14897  DAG.getNode(ISD::AND, DL, MVT::i16,
14898  CWD, DAG.getConstant(0x400, MVT::i16)),
14899  DAG.getConstant(9, MVT::i8));
14900 
14901  SDValue RetVal =
14902  DAG.getNode(ISD::AND, DL, MVT::i16,
14903  DAG.getNode(ISD::ADD, DL, MVT::i16,
14904  DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
14905  DAG.getConstant(1, MVT::i16)),
14906  DAG.getConstant(3, MVT::i16));
14907 
14908  return DAG.getNode((VT.getSizeInBits() < 16 ?
14909  ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
14910 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::TargetFrameLowering::getStackAlignment
unsigned getStackAlignment() const
Definition: TargetFrameLowering.h:70
llvm::MachineMemOperand::MOStore
The memory access writes data.
Definition: MachineMemOperand.h:103
llvm::TargetLoweringBase::TM
const TargetMachine & TM
True if this is a little endian target.
Definition: TargetLowering.h:1452
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
Definition: MachineInstr.cpp:414
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::TargetMachine::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: Target/TargetMachine.h:119
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: MachineFunction.cpp:230
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Definition: MachineFunction.cpp:513
llvm::SelectionDAG::getMemIntrinsicNode
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true)
Definition: SelectionDAG.cpp:4586
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1297
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
SDValue X86TargetLowering::LowerFormalArguments ( SDValue  Chain,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::InputArg > &  Ins,
SDLoc  dl,
SelectionDAG &  DAG,
SmallVectorImpl< SDValue > &  InVals 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2244 of file X86ISelLowering.cpp.

2251  {
2252  MachineFunction &MF = DAG.getMachineFunction();
2253  X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2254 
2255  const Function* Fn = MF.getFunction();
2256  if (Fn->hasExternalLinkage() &&
2257  Subtarget->isTargetCygMing() &&
2258  Fn->getName() == "main")
2259  FuncInfo->setForceFramePointer(true);
2260 
2261  MachineFrameInfo *MFI = MF.getFrameInfo();
2262  bool Is64Bit = Subtarget->is64Bit();
2263  bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2264 
2265  assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2266  "Var args not supported with calling convention fastcc, ghc or hipe");
2267 
2268  // Assign locations to all of the incoming arguments.
2269  SmallVector<CCValAssign, 16> ArgLocs;
2270  CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
2271  ArgLocs, *DAG.getContext());
2272 
2273  // Allocate shadow area for Win64
2274  if (IsWin64)
2275  CCInfo.AllocateStack(32, 8);
2276 
2277  CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2278 
2279  unsigned LastVal = ~0U;
2280  SDValue ArgValue;
2281  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2282  CCValAssign &VA = ArgLocs[i];
2283  // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2284  // places.
2285  assert(VA.getValNo() != LastVal &&
2286  "Don't support value assigned to multiple locs yet");
2287  (void)LastVal;
2288  LastVal = VA.getValNo();
2289 
2290  if (VA.isRegLoc()) {
2291  EVT RegVT = VA.getLocVT();
2292  const TargetRegisterClass *RC;
2293  if (RegVT == MVT::i32)
2294  RC = &X86::GR32RegClass;
2295  else if (Is64Bit && RegVT == MVT::i64)
2296  RC = &X86::GR64RegClass;
2297  else if (RegVT == MVT::f32)
2298  RC = &X86::FR32RegClass;
2299  else if (RegVT == MVT::f64)
2300  RC = &X86::FR64RegClass;
2301  else if (RegVT.is512BitVector())
2302  RC = &X86::VR512RegClass;
2303  else if (RegVT.is256BitVector())
2304  RC = &X86::VR256RegClass;
2305  else if (RegVT.is128BitVector())
2306  RC = &X86::VR128RegClass;
2307  else if (RegVT == MVT::x86mmx)
2308  RC = &X86::VR64RegClass;
2309  else if (RegVT == MVT::i1)
2310  RC = &X86::VK1RegClass;
2311  else if (RegVT == MVT::v8i1)
2312  RC = &X86::VK8RegClass;
2313  else if (RegVT == MVT::v16i1)
2314  RC = &X86::VK16RegClass;
2315  else
2316  llvm_unreachable("Unknown argument type!");
2317 
2318  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2319  ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2320 
2321  // If this is an 8 or 16-bit value, it is really passed promoted to 32
2322  // bits. Insert an assert[sz]ext to capture this, then truncate to the
2323  // right size.
2324  if (VA.getLocInfo() == CCValAssign::SExt)
2325  ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2326  DAG.getValueType(VA.getValVT()));
2327  else if (VA.getLocInfo() == CCValAssign::ZExt)
2328  ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2329  DAG.getValueType(VA.getValVT()));
2330  else if (VA.getLocInfo() == CCValAssign::BCvt)
2331  ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2332 
2333  if (VA.isExtInLoc()) {
2334  // Handle MMX values passed in XMM regs.
2335  if (RegVT.isVector())
2336  ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2337  else
2338  ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2339  }
2340  } else {
2341  assert(VA.isMemLoc());
2342  ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2343  }
2344 
2345  // If value is passed via pointer - do a load.
2346  if (VA.getLocInfo() == CCValAssign::Indirect)
2347  ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2348  MachinePointerInfo(), false, false, false, 0);
2349 
2350  InVals.push_back(ArgValue);
2351  }
2352 
2353  if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2354  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2355  // The x86-64 ABIs require that for returning structs by value we copy
2356  // the sret argument into %rax/%eax (depending on ABI) for the return.
2357  // Win32 requires us to put the sret argument to %eax as well.
2358  // Save the argument into a virtual register so that we can access it
2359  // from the return points.
2360  if (Ins[i].Flags.isSRet()) {
2361  unsigned Reg = FuncInfo->getSRetReturnReg();
2362  if (!Reg) {
2363  MVT PtrTy = getPointerTy();
2364  Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2365  FuncInfo->setSRetReturnReg(Reg);
2366  }
2367  SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2368  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2369  break;
2370  }
2371  }
2372  }
2373 
2374  unsigned StackSize = CCInfo.getNextStackOffset();
2375  // Align stack specially for tail calls.
2376  if (FuncIsMadeTailCallSafe(CallConv,
2377  MF.getTarget().Options.GuaranteedTailCallOpt))
2378  StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2379 
2380  // If the function takes variable number of arguments, make a frame index for
2381  // the start of the first vararg value... for expansion of llvm.va_start.
2382  if (isVarArg) {
2383  if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2384  CallConv != CallingConv::X86_ThisCall)) {
2385  FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2386  }
2387  if (Is64Bit) {
2388  unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2389 
2390  // FIXME: We should really autogenerate these arrays
2391  static const MCPhysReg GPR64ArgRegsWin64[] = {
2392  X86::RCX, X86::RDX, X86::R8, X86::R9
2393  };
2394  static const MCPhysReg GPR64ArgRegs64Bit[] = {
2395  X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2396  };
2397  static const MCPhysReg XMMArgRegs64Bit[] = {
2398  X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2399  X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2400  };
2401  const MCPhysReg *GPR64ArgRegs;
2402  unsigned NumXMMRegs = 0;
2403 
2404  if (IsWin64) {
2405  // The XMM registers which might contain var arg parameters are shadowed
2406  // in their paired GPR. So we only need to save the GPR to their home
2407  // slots.
2408  TotalNumIntRegs = 4;
2409  GPR64ArgRegs = GPR64ArgRegsWin64;
2410  } else {
2411  TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2412  GPR64ArgRegs = GPR64ArgRegs64Bit;
2413 
2414  NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2415  TotalNumXMMRegs);
2416  }
2417  unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2418  TotalNumIntRegs);
2419 
2420  bool NoImplicitFloatOps = Fn->getAttributes().
2421  hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2422  assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2423  "SSE register cannot be used when SSE is disabled!");
2424  assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2425  NoImplicitFloatOps) &&
2426  "SSE register cannot be used when SSE is disabled!");
2427  if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2428  !Subtarget->hasSSE1())
2429  // Kernel mode asks for SSE to be disabled, so don't push them
2430  // on the stack.
2431  TotalNumXMMRegs = 0;
2432 
2433  if (IsWin64) {
2434  const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
2435  // Get to the caller-allocated home save location. Add 8 to account
2436  // for the return address.
2437  int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2438  FuncInfo->setRegSaveFrameIndex(
2439  MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2440  // Fixup to set vararg frame on shadow area (4 x i64).
2441  if (NumIntRegs < 4)
2442  FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2443  } else {
2444  // For X86-64, if there are vararg parameters that are passed via
2445  // registers, then we must store them to their spots on the stack so
2446  // they may be loaded by deferencing the result of va_next.
2447  FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2448  FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2449  FuncInfo->setRegSaveFrameIndex(
2450  MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2451  false));
2452  }
2453 
2454  // Store the integer parameter registers.
2455  SmallVector<SDValue, 8> MemOps;
2456  SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2457  getPointerTy());
2458  unsigned Offset = FuncInfo->getVarArgsGPOffset();
2459  for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2460  SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2461  DAG.getIntPtrConstant(Offset));
2462  unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2463  &X86::GR64RegClass);
2464  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2465  SDValue Store =
2466  DAG.getStore(Val.getValue(1), dl, Val, FIN,
2467  MachinePointerInfo::getFixedStack(
2468  FuncInfo->getRegSaveFrameIndex(), Offset),
2469  false, false, 0);
2470  MemOps.push_back(Store);
2471  Offset += 8;
2472  }
2473 
2474  if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2475  // Now store the XMM (fp + vector) parameter registers.
2476  SmallVector<SDValue, 11> SaveXMMOps;
2477  SaveXMMOps.push_back(Chain);
2478 
2479  unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2480  SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2481  SaveXMMOps.push_back(ALVal);
2482 
2483  SaveXMMOps.push_back(DAG.getIntPtrConstant(
2484  FuncInfo->getRegSaveFrameIndex()));
2485  SaveXMMOps.push_back(DAG.getIntPtrConstant(
2486  FuncInfo->getVarArgsFPOffset()));
2487 
2488  for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2489  unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2490  &X86::VR128RegClass);
2491  SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2492  SaveXMMOps.push_back(Val);
2493  }
2494  MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2495  MVT::Other, SaveXMMOps));
2496  }
2497 
2498  if (!MemOps.empty())
2499  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2500  }
2501  }
2502 
2503  // Some CCs need callee pop.
2504  if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2505  MF.getTarget().Options.GuaranteedTailCallOpt)) {
2506  FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2507  } else {
2508  FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2509  // If this is an sret function, the return should pop the hidden pointer.
2510  if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2511  !Subtarget->getTargetTriple().isOSMSVCRT() &&
2512  argsAreStructReturn(Ins) == StackStructReturn)
2513  FuncInfo->setBytesToPopOnReturn(4);
2514  }
2515 
2516  if (!Is64Bit) {
2517  // RegSaveFrameIndex is X86-64 only.
2518  FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2519  if (CallConv == CallingConv::X86_FastCall ||
2520  CallConv == CallingConv::X86_ThisCall)
2521  // fastcc functions can't have varargs.
2522  FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2523  }
2524 
2525  FuncInfo->setArgumentStackSize(StackSize);
2526 
2527  return Chain;
2528 }
FuncIsMadeTailCallSafe
static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, bool GuaranteedTailCallOpt)
Definition: X86ISelLowering.cpp:2197
llvm::X86MachineFunctionInfo::setVarArgsFPOffset
void setVarArgsFPOffset(unsigned Offset)
Definition: X86MachineFunctionInfo.h:133
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:133
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:144
llvm::X86Subtarget::isTargetCygMing
bool isTargetCygMing() const
Definition: X86Subtarget.h:403
llvm::MachineRegisterInfo::createVirtualRegister
unsigned createVirtualRegister(const TargetRegisterClass *RegClass)
Definition: MachineRegisterInfo.cpp:97
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::MachineFunction::addLiveIn
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC)
Definition: MachineFunction.cpp:435
llvm::X86Subtarget::isTargetKnownWindowsMSVC
bool isTargetKnownWindowsMSVC() const
Definition: X86Subtarget.h:391
llvm::MachineFunction::getFunction
const Function * getFunction() const
Definition: MachineFunction.h:151
llvm::CCValAssign::getValNo
unsigned getValNo() const
Definition: CallingConvLower.h:132
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:135
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
Definition: MachineInstr.cpp:414
llvm::EVT::isVector
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
argsAreStructReturn
static StructReturnType argsAreStructReturn(const SmallVectorImpl< ISD::InputArg > &Ins)
Definition: X86ISelLowering.cpp:2143
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:429
llvm::X86Subtarget::getTargetTriple
const Triple & getTargetTriple() const
Definition: X86Subtarget.h:368
llvm::MachineFrameInfo
Abstract Stack Frame Information.
Definition: MachineFrameInfo.h:80
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::X86TargetLowering::LowerMemArgument
SDValue LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl< ISD::InputArg > &ArgInfo, SDLoc dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, unsigned i) const
Definition: X86ISelLowering.cpp:2203
llvm::CCValAssign::getLocReg
unsigned getLocReg() const
Definition: CallingConvLower.h:140
llvm::SmallVectorBase::empty
bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const
Definition: SmallVector.h:57
llvm::MCPhysReg
uint16_t MCPhysReg
Definition: MCRegisterInfo.h:27
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
IsTailCallConvention
static bool IsTailCallConvention(CallingConv::ID CC)
Definition: X86ISelLowering.cpp:2172
llvm::X86MachineFunctionInfo::setVarArgsGPOffset
void setVarArgsGPOffset(unsigned Offset)
Definition: X86MachineFunctionInfo.h:130
llvm::X86MachineFunctionInfo::setBytesToPopOnReturn
void setBytesToPopOnReturn(unsigned bytes)
Definition: X86MachineFunctionInfo.h:109
assert
assert(Globals.size() > 1)
llvm::EVT::is256BitVector
bool is256BitVector() const
is256BitVector - Return true if this is a 256-bit vector type.
Definition: ValueTypes.h:141
llvm::X86Subtarget::isCallingConvWin64
bool isCallingConvWin64(CallingConv::ID CC) const
Definition: X86Subtarget.h:431
llvm::CCValAssign::isExtInLoc
bool isExtInLoc() const
Definition: CallingConvLower.h:145
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:142
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
Definition: TargetOptions.h:148
llvm::X86TargetLowering::GetAlignedArgumentStackSize
unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:3078
llvm::TargetMachine::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: Target/TargetMachine.h:119
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
Definition: SelectionDAG.cpp:4815
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
llvm::TargetLoweringBase::getRegClassFor
virtual const TargetRegisterClass * getRegClassFor(MVT VT) const
Definition: TargetLowering.h:314
llvm::CCValAssign::isMemLoc
bool isMemLoc() const
Definition: CallingConvLower.h:136
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:311
llvm::X86MachineFunctionInfo::setArgumentStackSize
void setArgumentStackSize(unsigned size)
Definition: X86MachineFunctionInfo.h:136
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
Definition: MachineFunction.h:167
llvm::Triple::isOSMSVCRT
bool isOSMSVCRT() const
Is this a "Windows" OS targeting a "MSVCRT.dll" environment.
Definition: Triple.h:398
llvm::MachineFunction::getTarget
const TargetMachine & getTarget() const
Definition: MachineFunction.h:163
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Definition: MachineFunction.cpp:513
llvm::EVT::is128BitVector
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
Definition: ValueTypes.h:136
llvm::X86::isCalleePop
bool isCalleePop(CallingConv::ID CallingConv, bool is64Bit, bool IsVarArg, bool TailCallOpt)
Definition: X86ISelLowering.cpp:3511
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1297
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1419
llvm::Attribute::NoImplicitFloat
Disable implicit floating point insts.
Definition: Attributes.h:86
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
Definition: MachineFunction.cpp:563
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
llvm::EVT::is512BitVector
bool is512BitVector() const
is512BitVector - Return true if this is a 512-bit vector type.
Definition: ValueTypes.h:146
llvm::CCState::AllocateStack
unsigned AllocateStack(unsigned Size, unsigned Align)
Definition: CallingConvLower.h:379
SDValue X86TargetLowering::LowerFP_TO_SINT ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 11328 of file X86ISelLowering.cpp.

11329  {
11330  assert(!Op.getSimpleValueType().isVector());
11331 
11332  std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11333  /*IsSigned=*/ true, /*IsReplace=*/ false);
11334  SDValue FIST = Vals.first, StackSlot = Vals.second;
11335  // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
11336  if (!FIST.getNode()) return Op;
11337 
11338  if (StackSlot.getNode())
11339  // Load the result.
11340  return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11341  FIST, StackSlot, MachinePointerInfo(),
11342  false, false, false, 0);
11343 
11344  // The node is the result.
11345  return FIST;
11346 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::MVT::isVector
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: MachineValueType.h:185
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::X86TargetLowering::FP_TO_INTHelper
std::pair< SDValue, SDValue > FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool isSigned, bool isReplace) const
Definition: X86ISelLowering.cpp:10988
SDValue X86TargetLowering::LowerFP_TO_UINT ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 11348 of file X86ISelLowering.cpp.

11349  {
11350  std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11351  /*IsSigned=*/ false, /*IsReplace=*/ false);
11352  SDValue FIST = Vals.first, StackSlot = Vals.second;
11353  assert(FIST.getNode() && "Unexpected failure");
11354 
11355  if (StackSlot.getNode())
11356  // Load the result.
11357  return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11358  FIST, StackSlot, MachinePointerInfo(),
11359  false, false, false, 0);
11360 
11361  // The node is the result.
11362  return FIST;
11363 }
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::X86TargetLowering::FP_TO_INTHelper
std::pair< SDValue, SDValue > FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool isSigned, bool isReplace) const
Definition: X86ISelLowering.cpp:10988
SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 14641 of file X86ISelLowering.cpp.

14642  {
14643  const X86RegisterInfo *RegInfo =
14644  static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14645  return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
14646 }
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::X86RegisterInfo::getSlotSize
unsigned getSlotSize() const
Definition: X86RegisterInfo.h:128
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
SDValue X86TargetLowering::LowerFRAMEADDR ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 14607 of file X86ISelLowering.cpp.

14607  {
14608  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
14609  MFI->setFrameAddressIsTaken(true);
14610 
14611  EVT VT = Op.getValueType();
14612  SDLoc dl(Op); // FIXME probably not meaningful
14613  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14614  const X86RegisterInfo *RegInfo =
14615  static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14616  unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
14617  assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
14618  (FrameReg == X86::EBP && VT == MVT::i32)) &&
14619  "Invalid Frame Register!");
14620  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
14621  while (Depth--)
14622  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
14623  MachinePointerInfo(),
14624  false, false, false, 0);
14625  return FrameAddr;
14626 }
llvm::MachineFrameInfo::setFrameAddressIsTaken
void setFrameAddressIsTaken(bool T)
Definition: MachineFrameInfo.h:281
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::MachineFrameInfo
Abstract Stack Frame Information.
Definition: MachineFrameInfo.h:80
assert
assert(Globals.size() > 1)
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::X86RegisterInfo::getFrameRegister
unsigned getFrameRegister(const MachineFunction &MF) const override
Definition: X86RegisterInfo.cpp:528
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue X86TargetLowering::LowerGlobalAddress ( const GlobalValue *  GV,
SDLoc  dl,
int64_t  Offset,
SelectionDAG &  DAG 
) const
private

Definition at line 10286 of file X86ISelLowering.cpp.

10287  {
10288  // Create the TargetGlobalAddress node, folding in the constant
10289  // offset if it is legal.
10290  unsigned char OpFlags =
10291  Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10292  CodeModel::Model M = DAG.getTarget().getCodeModel();
10293  SDValue Result;
10294  if (OpFlags == X86II::MO_NO_FLAG &&
10295  X86::isOffsetSuitableForCodeModel(Offset, M)) {
10296  // A direct static reference to a global.
10297  Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
10298  Offset = 0;
10299  } else {
10300  Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
10301  }
10302 
10303  if (Subtarget->isPICStyleRIPRel() &&
10304  (M == CodeModel::Small || M == CodeModel::Kernel))
10305  Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10306  else
10307  Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10308 
10309  // With PIC, the address is actually $g + Offset.
10310  if (isGlobalRelativeToPICBase(OpFlags)) {
10311  Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10312  DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10313  Result);
10314  }
10315 
10316  // For globals that require a load from a stub to get the address, emit the
10317  // load.
10318  if (isGlobalStubReference(OpFlags))
10319  Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
10320  MachinePointerInfo::getGOT(), false, false, false, 0);
10321 
10322  // If there was a non-zero offset that we didn't fold, create an explicit
10323  // addition for it.
10324  if (Offset != 0)
10325  Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
10326  DAG.getConstant(Offset, getPointerTy()));
10327 
10328  return Result;
10329 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::X86Subtarget::ClassifyGlobalReference
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
Definition: X86Subtarget.cpp:64
llvm::isGlobalStubReference
static bool isGlobalStubReference(unsigned char TargetFlag)
Definition: X86InstrInfo.h:85
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::isGlobalRelativeToPICBase
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
Definition: X86InstrInfo.h:102
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::X86Subtarget::isPICStyleRIPRel
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:417
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Definition: TargetMachine.cpp:84
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT()
Definition: MachineInstr.cpp:422
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::X86::isOffsetSuitableForCodeModel
bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, bool hasSymbolicDisplacement=true)
Definition: X86ISelLowering.cpp:3479
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue X86TargetLowering::LowerGlobalAddress ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 10332 of file X86ISelLowering.cpp.

10332  {
10333  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
10334  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
10335  return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
10336 }
llvm::getOffset
static std::error_code getOffset(const SymbolRef &Sym, uint64_t &Result)
Definition: RuntimeDyld.cpp:76
llvm::X86TargetLowering::LowerGlobalAddress
SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl, int64_t Offset, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10286
SDValue X86TargetLowering::LowerGlobalTLSAddress ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 10485 of file X86ISelLowering.cpp.

10485  {
10486 
10487  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
10488  const GlobalValue *GV = GA->getGlobal();
10489 
10490  if (Subtarget->isTargetELF()) {
10491  TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
10492 
10493  switch (model) {
10494  case TLSModel::GeneralDynamic:
10495  if (Subtarget->is64Bit())
10496  return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
10497  return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
10498  case TLSModel::LocalDynamic:
10499  return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
10500  Subtarget->is64Bit());
10501  case TLSModel::InitialExec:
10502  case TLSModel::LocalExec:
10503  return LowerToTLSExecModel(
10504  GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
10505  DAG.getTarget().getRelocationModel() == Reloc::PIC_);
10506  }
10507  llvm_unreachable("Unknown TLS model.");
10508  }
10509 
10510  if (Subtarget->isTargetDarwin()) {
10511  // Darwin only has one model of TLS. Lower to that.
10512  unsigned char OpFlag = 0;
10513  unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
10514  X86ISD::WrapperRIP : X86ISD::Wrapper;
10515 
10516  // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10517  // global base reg.
10518  bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
10519  !Subtarget->is64Bit();
10520  if (PIC32)
10521  OpFlag = X86II::MO_TLVP_PIC_BASE;
10522  else
10523  OpFlag = X86II::MO_TLVP;
10524  SDLoc DL(Op);
10525  SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
10526  GA->getValueType(0),
10527  GA->getOffset(), OpFlag);
10528  SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10529 
10530  // With PIC32, the address is actually $g + Offset.
10531  if (PIC32)
10532  Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10533  DAG.getNode(X86ISD::GlobalBaseReg,
10534  SDLoc(), getPointerTy()),
10535  Offset);
10536 
10537  // Lowering the machine isd will make sure everything is in the right
10538  // location.
10539  SDValue Chain = DAG.getEntryNode();
10540  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10541  SDValue Args[] = { Chain, Offset };
10542  Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
10543 
10544  // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
10545  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10546  MFI->setAdjustsStack(true);
10547 
10548  // And our return value (tls address) is in the standard call return value
10549  // location.
10550  unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10551  return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
10552  Chain.getValue(1));
10553  }
10554 
10555  if (Subtarget->isTargetKnownWindowsMSVC() ||
10556  Subtarget->isTargetWindowsGNU()) {
10557  // Just use the implicit TLS architecture
10558  // Need to generate someting similar to:
10559  // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
10560  // ; from TEB
10561  // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
10562  // mov rcx, qword [rdx+rcx*8]
10563  // mov eax, .tls$:tlsvar
10564  // [rax+rcx] contains the address
10565  // Windows 64bit: gs:0x58
10566  // Windows 32bit: fs:__tls_array
10567 
10568  SDLoc dl(GA);
10569  SDValue Chain = DAG.getEntryNode();
10570 
10571  // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
10572  // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
10573  // use its literal value of 0x2C.
10574  Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
10575  ? Type::getInt8PtrTy(*DAG.getContext(),
10576  256)
10577  : Type::getInt32PtrTy(*DAG.getContext(),
10578  257));
10579 
10580  SDValue TlsArray =
10581  Subtarget->is64Bit()
10582  ? DAG.getIntPtrConstant(0x58)
10583  : (Subtarget->isTargetWindowsGNU()
10584  ? DAG.getIntPtrConstant(0x2C)
10585  : DAG.getExternalSymbol("_tls_array", getPointerTy()));
10586 
10587  SDValue ThreadPointer =
10588  DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
10589  MachinePointerInfo(Ptr), false, false, false, 0);
10590 
10591  // Load the _tls_index variable
10592  SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
10593  if (Subtarget->is64Bit())
10594  IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
10595  IDX, MachinePointerInfo(), MVT::i32,
10596  false, false, 0);
10597  else
10598  IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
10599  false, false, false, 0);
10600 
10601  SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
10602  getPointerTy());
10603  IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
10604 
10605  SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
10606  res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
10607  false, false, false, 0);
10608 
10609  // Get the offset of start of .tls section
10610  SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10611  GA->getValueType(0),
10612  GA->getOffset(), X86II::MO_SECREL);
10613  SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
10614 
10615  // The address of the thread local variable is the add of the thread
10616  // pointer with the offset of the variable.
10617  return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
10618  }
10619 
10620  llvm_unreachable("TLS not implemented for this target.");
10621 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::TargetMachine::getRelocationModel
Reloc::Model getRelocationModel() const
Definition: TargetMachine.cpp:76
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::Type::getInt32PtrTy
static PointerType * getInt32PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:286
llvm::GlobalAddressSDNode::getGlobal
const GlobalValue * getGlobal() const
Definition: SelectionDAGNodes.h:1418
llvm::X86Subtarget::isTargetKnownWindowsMSVC
bool isTargetKnownWindowsMSVC() const
Definition: X86Subtarget.h:391
llvm::SelectionDAG::getExtLoad
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
Definition: SelectionDAG.cpp:4783
LowerToTLSGeneralDynamicModel64
static SDValue LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT)
Definition: X86ISelLowering.cpp:10384
llvm::SelectionDAG::getExternalSymbol
SDValue getExternalSymbol(const char *Sym, EVT VT)
Definition: SelectionDAG.cpp:1433
llvm::Constant::getNullValue
static Constant * getNullValue(Type *Ty)
Definition: Constants.cpp:133
LowerToTLSLocalDynamicModel
static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT, bool is64Bit)
Definition: X86ISelLowering.cpp:10390
llvm::X86Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: X86Subtarget.h:370
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Definition: SelectionDAGNodes.h:648
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::SelectionDAG::getTargetGlobalAddress
SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT, int64_t offset=0, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:433
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:429
llvm::MachineFrameInfo
Abstract Stack Frame Information.
Definition: MachineFrameInfo.h:80
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::X86Subtarget::isTargetWindowsGNU
bool isTargetWindowsGNU() const
Definition: X86Subtarget.h:399
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::X86Subtarget::isPICStyleRIPRel
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:417
LowerToTLSExecModel
static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT, TLSModel::Model model, bool is64Bit, bool isPIC)
Definition: X86ISelLowering.cpp:10430
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
llvm::Type::getInt8PtrTy
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:278
Args
const char * Args[]
Definition: OptionParsingTest.cpp:55
llvm::X86Subtarget::isTargetELF
bool isTargetELF() const
Definition: X86Subtarget.h:378
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
llvm::Log2_64_Ceil
unsigned Log2_64_Ceil(uint64_t Value)
Definition: MathExtras.h:471
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
LowerToTLSGeneralDynamicModel32
static SDValue LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT)
Definition: X86ISelLowering.cpp:10370
llvm::TargetMachine::getTLSModel
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Definition: TargetMachine.cpp:108
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::Value
LLVM Value Representation.
Definition: Value.h:69
llvm::X86TargetLowering::TD
const DataLayout * TD
Definition: X86ISelLowering.h:810
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
llvm::DataLayout::getPointerSize
unsigned getPointerSize(unsigned AS=0) const
Definition: DataLayout.cpp:602
SDValue X86TargetLowering::LowerINIT_TRAMPOLINE ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 14694 of file X86ISelLowering.cpp.

14695  {
14696  SDValue Root = Op.getOperand(0);
14697  SDValue Trmp = Op.getOperand(1); // trampoline
14698  SDValue FPtr = Op.getOperand(2); // nested function
14699  SDValue Nest = Op.getOperand(3); // 'nest' parameter value
14700  SDLoc dl (Op);
14701 
14702  const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14703  const TargetRegisterInfo* TRI = DAG.getTarget().getRegisterInfo();
14704 
14705  if (Subtarget->is64Bit()) {
14706  SDValue OutChains[6];
14707 
14708  // Large code-model.
14709  const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
14710  const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
14711 
14712  const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
14713  const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
14714 
14715  const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
14716 
14717  // Load the pointer to the nested function into R11.
14718  unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
14719  SDValue Addr = Trmp;
14720  OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14721  Addr, MachinePointerInfo(TrmpAddr),
14722  false, false, 0);
14723 
14724  Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14725  DAG.getConstant(2, MVT::i64));
14726  OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
14727  MachinePointerInfo(TrmpAddr, 2),
14728  false, false, 2);
14729 
14730  // Load the 'nest' parameter value into R10.
14731  // R10 is specified in X86CallingConv.td
14732  OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
14733  Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14734  DAG.getConstant(10, MVT::i64));
14735  OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14736  Addr, MachinePointerInfo(TrmpAddr, 10),
14737  false, false, 0);
14738 
14739  Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14740  DAG.getConstant(12, MVT::i64));
14741  OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
14742  MachinePointerInfo(TrmpAddr, 12),
14743  false, false, 2);
14744 
14745  // Jump to the nested function.
14746  OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
14747  Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14748  DAG.getConstant(20, MVT::i64));
14749  OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14750  Addr, MachinePointerInfo(TrmpAddr, 20),
14751  false, false, 0);
14752 
14753  unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
14754  Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14755  DAG.getConstant(22, MVT::i64));
14756  OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
14757  MachinePointerInfo(TrmpAddr, 22),
14758  false, false, 0);
14759 
14760  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
14761  } else {
14762  const Function *Func =
14763  cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
14764  CallingConv::ID CC = Func->getCallingConv();
14765  unsigned NestReg;
14766 
14767  switch (CC) {
14768  default:
14769  llvm_unreachable("Unsupported calling convention");
14770  case CallingConv::C:
14771  case CallingConv::X86_StdCall: {
14772  // Pass 'nest' parameter in ECX.
14773  // Must be kept in sync with X86CallingConv.td
14774  NestReg = X86::ECX;
14775 
14776  // Check that ECX wasn't needed by an 'inreg' parameter.
14777  FunctionType *FTy = Func->getFunctionType();
14778  const AttributeSet &Attrs = Func->getAttributes();
14779 
14780  if (!Attrs.isEmpty() && !Func->isVarArg()) {
14781  unsigned InRegCount = 0;
14782  unsigned Idx = 1;
14783 
14784  for (FunctionType::param_iterator I = FTy->param_begin(),
14785  E = FTy->param_end(); I != E; ++I, ++Idx)
14786  if (Attrs.hasAttribute(Idx, Attribute::InReg))
14787  // FIXME: should only count parameters that are lowered to integers.
14788  InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
14789 
14790  if (InRegCount > 2) {
14791  report_fatal_error("Nest register in use - reduce number of inreg"
14792  " parameters!");
14793  }
14794  }
14795  break;
14796  }
14797  case CallingConv::X86_FastCall:
14798  case CallingConv::X86_ThisCall:
14799  case CallingConv::Fast:
14800  // Pass 'nest' parameter in EAX.
14801  // Must be kept in sync with X86CallingConv.td
14802  NestReg = X86::EAX;
14803  break;
14804  }
14805 
14806  SDValue OutChains[4];
14807  SDValue Addr, Disp;
14808 
14809  Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14810  DAG.getConstant(10, MVT::i32));
14811  Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
14812 
14813  // This is storing the opcode for MOV32ri.
14814  const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
14815  const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
14816  OutChains[0] = DAG.getStore(Root, dl,
14817  DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
14818  Trmp, MachinePointerInfo(TrmpAddr),
14819  false, false, 0);
14820 
14821  Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14822  DAG.getConstant(1, MVT::i32));
14823  OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
14824  MachinePointerInfo(TrmpAddr, 1),
14825  false, false, 1);
14826 
14827  const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
14828  Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14829  DAG.getConstant(5, MVT::i32));
14830  OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
14831  MachinePointerInfo(TrmpAddr, 5),
14832  false, false, 1);
14833 
14834  Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14835  DAG.getConstant(6, MVT::i32));
14836  OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
14837  MachinePointerInfo(TrmpAddr, 6),
14838  false, false, 1);
14839 
14840  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
14841  }
14842 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::Attribute::InReg
Force argument to be passed in register.
Definition: Attributes.h:77
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::FunctionType::param_iterator
Type::subtype_iterator param_iterator
Definition: DerivedTypes.h:123
llvm::AttributeSet::hasAttribute
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Definition: ErrorHandling.cpp:60
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
Definition: Function.h:161
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::FunctionType::param_end
param_iterator param_end() const
Definition: DerivedTypes.h:125
llvm::CallingConv::ID
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::FunctionType::param_begin
param_iterator param_begin() const
Definition: DerivedTypes.h:124
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
Definition: SelectionDAG.cpp:4815
llvm::Function::getAttributes
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
I
#define I(x, y, z)
Definition: MD5.cpp:54
llvm::Function::getFunctionType
FunctionType * getFunctionType() const
Definition: Function.cpp:206
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::MCRegisterInfo::getEncodingValue
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
Definition: MCRegisterInfo.h:405
llvm::Value
LLVM Value Representation.
Definition: Value.h:69
llvm::DataLayout::getTypeSizeInBits
uint64_t getTypeSizeInBits(Type *Ty) const
Definition: DataLayout.h:522
llvm::X86TargetLowering::TD
const DataLayout * TD
Definition: X86ISelLowering.h:810
llvm::Function::isVarArg
bool isVarArg() const
Definition: Function.cpp:210
llvm::AttributeSet::isEmpty
bool isEmpty() const
Return true if there are no attributes.
Definition: Attributes.h:358
SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 10005 of file X86ISelLowering.cpp.

10005  {
10006  MVT VT = Op.getSimpleValueType();
10007  MVT EltVT = VT.getVectorElementType();
10008 
10009  if (EltVT == MVT::i1)
10010  return InsertBitToMaskVector(Op, DAG);
10011 
10012  SDLoc dl(Op);
10013  SDValue N0 = Op.getOperand(0);
10014  SDValue N1 = Op.getOperand(1);
10015  SDValue N2 = Op.getOperand(2);
10016 
10017  // If this is a 256-bit vector result, first extract the 128-bit vector,
10018  // insert the element into the extracted half and then place it back.
10019  if (VT.is256BitVector() || VT.is512BitVector()) {
10020  if (!isa<ConstantSDNode>(N2))
10021  return SDValue();
10022 
10023  // Get the desired 128-bit vector half.
10024  unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
10025  SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10026 
10027  // Insert the element into the desired half.
10028  unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
10029  unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
10030 
10031  V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10032  DAG.getConstant(IdxIn128, MVT::i32));
10033 
10034  // Insert the changed part back to the 256-bit vector
10035  return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10036  }
10037 
10038  if (Subtarget->hasSSE41())
10039  return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
10040 
10041  if (EltVT == MVT::i8)
10042  return SDValue();
10043 
10044  if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
10045  // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10046  // as its second argument.
10047  if (N1.getValueType() != MVT::i32)
10048  N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10049  if (N2.getValueType() != MVT::i32)
10050  N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10051  return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10052  }
10053  return SDValue();
10054 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::MVT::is512BitVector
bool is512BitVector() const
is512BitVector - Return true if this is a 512-bit vector type.
Definition: MachineValueType.h:224
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm::X86Subtarget::hasSSE41
bool hasSSE41() const
Definition: X86Subtarget.h:315
Insert128BitVector
static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl)
Definition: X86ISelLowering.cpp:162
LowerINSERT_VECTOR_ELT_SSE4
static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:9917
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
Extract128BitVector
static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl)
Definition: X86ISelLowering.cpp:118
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::X86TargetLowering::InsertBitToMaskVector
SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:9973
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
llvm::MVT::is256BitVector
bool is256BitVector() const
is256BitVector - Return true if this is a 256-bit vector type.
Definition: MachineValueType.h:217
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:264
SDValue X86TargetLowering::LowerJumpTable ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 10179 of file X86ISelLowering.cpp.

10179  {
10180  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10181 
10182  // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10183  // global base reg.
10184  unsigned char OpFlag = 0;
10185  unsigned WrapperKind = X86ISD::Wrapper;
10186  CodeModel::Model M = DAG.getTarget().getCodeModel();
10187 
10188  if (Subtarget->isPICStyleRIPRel() &&
10189  (M == CodeModel::Small || M == CodeModel::Kernel))
10190  WrapperKind = X86ISD::WrapperRIP;
10191  else if (Subtarget->isPICStyleGOT())
10192  OpFlag = X86II::MO_GOTOFF;
10193  else if (Subtarget->isPICStyleStubPIC())
10194  OpFlag = X86II::MO_PIC_BASE_OFFSET;
10195 
10196  SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10197  OpFlag);
10198  SDLoc DL(JT);
10199  Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10200 
10201  // With PIC, the address is actually $g + Offset.
10202  if (OpFlag)
10203  Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10204  DAG.getNode(X86ISD::GlobalBaseReg,
10205  SDLoc(), getPointerTy()),
10206  Result);
10207 
10208  return Result;
10209 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::X86Subtarget::isPICStyleRIPRel
bool isPICStyleRIPRel() const
Definition: X86Subtarget.h:417
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Definition: TargetMachine.cpp:84
llvm::X86Subtarget::isPICStyleStubPIC
bool isPICStyleStubPIC() const
Definition: X86Subtarget.h:419
llvm::X86Subtarget::isPICStyleGOT
bool isPICStyleGOT() const
Definition: X86Subtarget.h:416
llvm::SelectionDAG::getTargetJumpTable
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags=0)
Definition: SelectionDAG.h:444
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
SDValue X86TargetLowering::LowerMemArgument ( SDValue  Chain,
CallingConv::ID  CallConv,
const SmallVectorImpl< ISD::InputArg > &  ArgInfo,
SDLoc  dl,
SelectionDAG &  DAG,
const CCValAssign &  VA,
MachineFrameInfo *  MFI,
unsigned  i 
) const
private

Definition at line 2203 of file X86ISelLowering.cpp.

2209  {
2210  // Create the nodes corresponding to a load from this parameter slot.
2211  ISD::ArgFlagsTy Flags = Ins[i].Flags;
2212  bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2213  CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2214  bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2215  EVT ValVT;
2216 
2217  // If value is passed by pointer we have address passed instead of the value
2218  // itself.
2219  if (VA.getLocInfo() == CCValAssign::Indirect)
2220  ValVT = VA.getLocVT();
2221  else
2222  ValVT = VA.getValVT();
2223 
2224  // FIXME: For now, all byval parameter objects are marked mutable. This can be
2225  // changed with more analysis.
2226  // In case of tail call optimization mark all arguments mutable. Since they
2227  // could be overwritten by lowering of arguments in case of a tail call.
2228  if (Flags.isByVal()) {
2229  unsigned Bytes = Flags.getByValSize();
2230  if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2231  int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2232  return DAG.getFrameIndex(FI, getPointerTy());
2233  } else {
2234  int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2235  VA.getLocMemOffset(), isImmutable);
2236  SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2237  return DAG.getLoad(ValVT, dl, Chain, FIN,
2238  MachinePointerInfo::getFixedStack(FI),
2239  false, false, false, 0);
2240  }
2241 }
FuncIsMadeTailCallSafe
static bool FuncIsMadeTailCallSafe(CallingConv::ID CC, bool GuaranteedTailCallOpt)
Definition: X86ISelLowering.cpp:2197
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:133
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:144
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::ISD::ArgFlagsTy::getByValSize
unsigned getByValSize() const
Definition: TargetCallingConv.h:114
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
Definition: MachineInstr.cpp:414
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:142
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
Definition: TargetOptions.h:148
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1297
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:141
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool Immutable)
Definition: MachineFunction.cpp:563
SDValue X86TargetLowering::LowerMemOpCallTo ( SDValue  Chain,
SDValue  StackPtr,
SDValue  Arg,
SDLoc  dl,
SelectionDAG &  DAG,
const CCValAssign &  VA,
ISD::ArgFlagsTy  Flags 
) const
private

Definition at line 2531 of file X86ISelLowering.cpp.

2535  {
2536  unsigned LocMemOffset = VA.getLocMemOffset();
2537  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2538  PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2539  if (Flags.isByVal())
2540  return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2541 
2542  return DAG.getStore(Chain, dl, Arg, PtrOff,
2543  MachinePointerInfo::getStack(LocMemOffset),
2544  false, false, 0);
2545 }
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
Definition: SelectionDAG.cpp:4815
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(int64_t Offset)
getStack - stack pointer relative access.
Definition: MachineInstr.cpp:426
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:141
CreateCopyOfByValArgument
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, SDLoc dl)
Definition: X86ISelLowering.cpp:2160
SDValue llvm::X86TargetLowering::LowerMEMSET ( SDValue  Op,
SelectionDAG &  DAG 
) const
private
SDValue X86TargetLowering::LowerOperation ( SDValue  Op,
SelectionDAG &  DAG 
) const
overridevirtual

LowerOperation - Provide custom lowering hooks for some operations.

Reimplemented from llvm::TargetLowering.

Definition at line 16208 of file X86ISelLowering.cpp.

16208  {
16209  switch (Op.getOpcode()) {
16210  default: llvm_unreachable("Should not custom lower this!");
16211  case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
16212  case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
16213  case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
16214  return LowerCMP_SWAP(Op, Subtarget, DAG);
16215  case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
16216  case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
16217  case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16218  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
16219  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
16220  case ISD::VSELECT: return LowerVSELECT(Op, DAG);
16221  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
16222  case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
16223  case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
16224  case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
16225  case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
16226  case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
16227  case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
16228  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
16229  case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
16230  case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
16231  case ISD::SHL_PARTS:
16232  case ISD::SRA_PARTS:
16233  case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
16234  case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
16235  case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
16236  case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
16237  case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
16238  case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
16239  case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
16240  case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
16241  case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
16242  case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
16243  case ISD::FABS: return LowerFABS(Op, DAG);
16244  case ISD::FNEG: return LowerFNEG(Op, DAG);
16245  case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
16246  case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
16247  case ISD::SETCC: return LowerSETCC(Op, DAG);
16248  case ISD::SELECT: return LowerSELECT(Op, DAG);
16249  case ISD::BRCOND: return LowerBRCOND(Op, DAG);
16250  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
16251  case ISD::VASTART: return LowerVASTART(Op, DAG);
16252  case ISD::VAARG: return LowerVAARG(Op, DAG);
16253  case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
16254  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
16255  case ISD::INTRINSIC_VOID:
16256  case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
16257  case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
16258  case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
16259  case ISD::FRAME_TO_ARGS_OFFSET:
16260  return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
16261  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
16262  case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
16263  case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
16264  case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
16265  case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
16266  case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
16267  case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
16268  case ISD::CTLZ: return LowerCTLZ(Op, DAG);
16269  case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
16270  case ISD::CTTZ: return LowerCTTZ(Op, DAG);
16271  case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
16272  case ISD::UMUL_LOHI:
16273  case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
16274  case ISD::SRA:
16275  case ISD::SRL:
16276  case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
16277  case ISD::SADDO:
16278  case ISD::UADDO:
16279  case ISD::SSUBO:
16280  case ISD::USUBO:
16281  case ISD::SMULO:
16282  case ISD::UMULO: return LowerXALUO(Op, DAG);
16283  case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
16284  case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
16285  case ISD::ADDC:
16286  case ISD::ADDE:
16287  case ISD::SUBC:
16288  case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
16289  case ISD::ADD: return LowerADD(Op, DAG);
16290  case ISD::SUB: return LowerSUB(Op, DAG);
16291  case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
16292  }
16293 }
LowerINSERT_SUBVECTOR
static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:10113
LowerFNEG
static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:11413
LowerADJUST_TRAMPOLINE
static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:14690
llvm::X86TargetLowering::LowerGlobalTLSAddress
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10485
llvm::X86TargetLowering::LowerRETURNADDR
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:14578
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86TargetLowering::lowerEH_SJLJ_LONGJMP
SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:14683
llvm::X86TargetLowering::LowerVECTOR_SHUFFLE
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:9257
LowerADD
static SDValue LowerADD(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:15020
llvm::X86TargetLowering::LowerINIT_TRAMPOLINE
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:14694
llvm::X86TargetLowering::LowerINSERT_VECTOR_ELT
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10005
llvm::X86TargetLowering::LowerExternalSymbol
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10212
LowerSUB
static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:15027
LowerMUL_LOHI
static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:15158
llvm::X86TargetLowering::LowerJumpTable
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10179
llvm::X86TargetLowering::LowerVASTART
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:13229
llvm::ISD::SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:221
LowerZERO_EXTEND
static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:11165
llvm::X86TargetLowering::LowerSETCC
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:12407
LowerADDC_ADDE_SUBC_SUBE
static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:16128
llvm::X86TargetLowering::LowerVAARG
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:13289
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::X86TargetLowering::lowerEH_SJLJ_SETJMP
SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:14675
LowerREADCYCLECOUNTER
static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:14376
llvm::X86TargetLowering::LowerFRAMEADDR
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:14607
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
LowerATOMIC_FENCE
static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:15959
LowerCTLZ
static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:14912
LowerEXTRACT_SUBVECTOR
static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:10087
LowerFP_EXTEND
static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:11365
LowerINTRINSIC_WO_CHAIN
static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:13486
LowerCTLZ_ZERO_UNDEF
static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:14946
LowerCONCAT_VECTORS
static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:6866
LowerBITCAST
static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:16036
llvm::X86TargetLowering::LowerEH_RETURN
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:14648
llvm::X86TargetLowering::LowerUINT_TO_FP
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10898
llvm::X86TargetLowering::LowerSIGN_EXTEND_INREG
SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:15883
llvm::X86TargetLowering::LowerFP_TO_UINT
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:11348
llvm::X86TargetLowering::LowerSELECT
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:12516
llvm::X86TargetLowering::LowerBlockAddress
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10258
llvm::X86TargetLowering::LowerTRUNCATE
SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:11186
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::X86TargetLowering::LowerDYNAMIC_STACKALLOC
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:13124
LowerCTTZ
static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:14971
llvm::ISD::FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
llvm::X86TargetLowering::LowerBRCOND
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:12840
LowerATOMIC_STORE
static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:16103
LowerCMP_SWAP
static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:15995
LowerSIGN_EXTEND
static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:12763
llvm::X86TargetLowering::LowerFLT_ROUNDS_
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:14844
LowerSCALAR_TO_VECTOR
static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:10056
LowerANY_EXTEND
static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:11154
LowerLOAD_SUB
static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:16088
LowerShiftParts
static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:10625
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
LowerFGETSIGN
static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:11529
LowerShift
static SDValue LowerShift(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:15561
llvm::ISD::SMULO
Same for multiplication.
Definition: ISDOpcodes.h:224
llvm::X86TargetLowering::LowerSINT_TO_FP
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10677
llvm::ISD::FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:490
LowerXALUO
static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:15808
llvm::X86TargetLowering::LowerFP_TO_SINT
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:11328
LowerVACOPY
static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:13356
LowerINTRINSIC_W_CHAIN
static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:14485
llvm::X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET
SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:14641
LowerFCOPYSIGN
static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:11449
llvm::X86TargetLowering::LowerConstantPool
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10146
llvm::X86TargetLowering::LowerBUILD_VECTOR
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:6493
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
llvm::X86TargetLowering::LowerEXTRACT_VECTOR_ELT
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:9804
llvm::X86TargetLowering::LowerGlobalAddress
SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl, int64_t Offset, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10286
LowerFABS
static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:11378
LowerMUL
static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:15034
LowerFSINCOS
static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:16154
llvm::X86TargetLowering::LowerVSELECT
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:9685
void TargetLowering::LowerOperationWrapper ( SDNode *  N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG &  DAG 
) const
virtualinherited

This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but legal result types. It replaces the LowerOperation callback in the type Legalizer. The reason we can not do away with LowerOperation entirely is that LegalizeDAG isn't yet ready to use this callback.

TODO: Consider merging with ReplaceNodeResults.

The target places new result values for the node in Results (their number and types must exactly match those of the original return values of the node), or leaves Results empty, which indicates that the node is not to be custom lowered after all. The default implementation calls LowerOperation.

Reimplemented in llvm::MipsTargetLowering.

Definition at line 7332 of file SelectionDAGBuilder.cpp.

7334  {
7335  SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7336  if (Res.getNode())
7337  Results.push_back(Res);
7338 }
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::TargetLowering::LowerOperation
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
Definition: SelectionDAGBuilder.cpp:7340
SDValue X86TargetLowering::LowerReturn ( SDValue  Chain,
CallingConv::ID  CallConv,
bool  isVarArg,
const SmallVectorImpl< ISD::OutputArg > &  Outs,
const SmallVectorImpl< SDValue > &  OutVals,
SDLoc  dl,
SelectionDAG &  DAG 
) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 1881 of file X86ISelLowering.cpp.

1885  {
1886  MachineFunction &MF = DAG.getMachineFunction();
1887  X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1888 
1889  SmallVector<CCValAssign, 16> RVLocs;
1890  CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
1891  RVLocs, *DAG.getContext());
1892  CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1893 
1894  SDValue Flag;
1895  SmallVector<SDValue, 6> RetOps;
1896  RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1897  // Operand #1 = Bytes To Pop
1898  RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1899  MVT::i16));
1900 
1901  // Copy the result values into the output registers.
1902  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1903  CCValAssign &VA = RVLocs[i];
1904  assert(VA.isRegLoc() && "Can only return in registers!");
1905  SDValue ValToCopy = OutVals[i];
1906  EVT ValVT = ValToCopy.getValueType();
1907 
1908  // Promote values to the appropriate types
1909  if (VA.getLocInfo() == CCValAssign::SExt)
1910  ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1911  else if (VA.getLocInfo() == CCValAssign::ZExt)
1912  ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1913  else if (VA.getLocInfo() == CCValAssign::AExt)
1914  ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1915  else if (VA.getLocInfo() == CCValAssign::BCvt)
1916  ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1917 
1918  assert(VA.getLocInfo() != CCValAssign::FPExt &&
1919  "Unexpected FP-extend for return value.");
1920 
1921  // If this is x86-64, and we disabled SSE, we can't return FP values,
1922  // or SSE or MMX vectors.
1923  if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1924  VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1925  (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1926  report_fatal_error("SSE register return with SSE disabled");
1927  }
1928  // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1929  // llvm-gcc has never done it right and no one has noticed, so this
1930  // should be OK for now.
1931  if (ValVT == MVT::f64 &&
1932  (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1933  report_fatal_error("SSE2 register return with SSE2 disabled");
1934 
1935  // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1936  // the RET instruction and handled by the FP Stackifier.
1937  if (VA.getLocReg() == X86::ST0 ||
1938  VA.getLocReg() == X86::ST1) {
1939  // If this is a copy from an xmm register to ST(0), use an FPExtend to
1940  // change the value to the FP stack register class.
1941  if (isScalarFPTypeInSSEReg(VA.getValVT()))
1942  ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1943  RetOps.push_back(ValToCopy);
1944  // Don't emit a copytoreg.
1945  continue;
1946  }
1947 
1948  // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1949  // which is returned in RAX / RDX.
1950  if (Subtarget->is64Bit()) {
1951  if (ValVT == MVT::x86mmx) {
1952  if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1953  ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1954  ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1955  ValToCopy);
1956  // If we don't have SSE2 available, convert to v4f32 so the generated
1957  // register is legal.
1958  if (!Subtarget->hasSSE2())
1959  ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1960  }
1961  }
1962  }
1963 
1964  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1965  Flag = Chain.getValue(1);
1966  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1967  }
1968 
1969  // The x86-64 ABIs require that for returning structs by value we copy
1970  // the sret argument into %rax/%eax (depending on ABI) for the return.
1971  // Win32 requires us to put the sret argument to %eax as well.
1972  // We saved the argument into a virtual register in the entry block,
1973  // so now we copy the value out and into %rax/%eax.
1974  if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1975  (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
1976  MachineFunction &MF = DAG.getMachineFunction();
1977  X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1978  unsigned Reg = FuncInfo->getSRetReturnReg();
1979  assert(Reg &&
1980  "SRetReturnReg should have been set in LowerFormalArguments().");
1981  SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1982 
1983  unsigned RetValReg
1984  = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1985  X86::RAX : X86::EAX;
1986  Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1987  Flag = Chain.getValue(1);
1988 
1989  // RAX/EAX now acts like a return value.
1990  RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1991  }
1992 
1993  RetOps[0] = Chain; // Update chain.
1994 
1995  // Add the flag if we have it.
1996  if (Flag.getNode())
1997  RetOps.push_back(Flag);
1998 
1999  return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2000 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:133
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:144
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::X86Subtarget::isTargetKnownWindowsMSVC
bool isTargetKnownWindowsMSVC() const
Definition: X86Subtarget.h:391
llvm::MachineFunction::getFunction
const Function * getFunction() const
Definition: MachineFunction.h:151
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:135
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Definition: ErrorHandling.cpp:60
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:429
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::CCValAssign::getLocReg
unsigned getLocReg() const
Definition: CallingConvLower.h:140
llvm::Function::hasStructRetAttr
bool hasStructRetAttr() const
Determine if the function returns a structure through first pointer argument.
Definition: Function.h:305
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::X86Subtarget::hasSSE2
bool hasSSE2() const
Definition: X86Subtarget.h:312
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:142
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
llvm::ISD::FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
llvm::X86Subtarget::isTarget64BitILP32
bool isTarget64BitILP32() const
Is this x86_64 with the ILP32 programming model (x32 ABI)?
Definition: X86Subtarget.h:296
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:31
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:406
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:311
llvm::CCState::AnalyzeReturn
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
Definition: CallingConvLower.cpp:100
llvm::SelectionDAG::getRegister
SDValue getRegister(unsigned Reg, EVT VT)
Definition: SelectionDAG.cpp:1647
llvm::X86TargetLowering::isScalarFPTypeInSSEReg
bool isScalarFPTypeInSSEReg(EVT VT) const
Definition: X86ISelLowering.h:752
SDValue X86TargetLowering::LowerRETURNADDR ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 14578 of file X86ISelLowering.cpp.

14579  {
14580  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
14581  MFI->setReturnAddressIsTaken(true);
14582 
14583  if (verifyReturnAddressArgumentIsConstant(Op, DAG))
14584  return SDValue();
14585 
14586  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14587  SDLoc dl(Op);
14588  EVT PtrVT = getPointerTy();
14589 
14590  if (Depth > 0) {
14591  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
14592  const X86RegisterInfo *RegInfo =
14593  static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14594  SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
14595  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
14596  DAG.getNode(ISD::ADD, dl, PtrVT,
14597  FrameAddr, Offset),
14598  MachinePointerInfo(), false, false, false, 0);
14599  }
14600 
14601  // Just load the return address.
14602  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
14603  return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
14604  RetAddrFI, MachinePointerInfo(), false, false, false, 0);
14605 }
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::TargetLowering::verifyReturnAddressArgumentIsConstant
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
Definition: TargetLowering.cpp:2772
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::MachineFrameInfo
Abstract Stack Frame Information.
Definition: MachineFrameInfo.h:80
llvm::X86TargetLowering::LowerFRAMEADDR
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:14607
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::X86TargetLowering::getReturnAddressFrameIndex
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:3460
llvm::X86RegisterInfo::getSlotSize
unsigned getSlotSize() const
Definition: X86RegisterInfo.h:128
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::MachineFrameInfo::setReturnAddressIsTaken
void setReturnAddressIsTaken(bool s)
Definition: MachineFrameInfo.h:287
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
SDValue X86TargetLowering::LowerSELECT ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 12516 of file X86ISelLowering.cpp.

12516  {
12517  bool addTest = true;
12518  SDValue Cond = Op.getOperand(0);
12519  SDValue Op1 = Op.getOperand(1);
12520  SDValue Op2 = Op.getOperand(2);
12521  SDLoc DL(Op);
12522  EVT VT = Op1.getValueType();
12523  SDValue CC;
12524 
12525  // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
12526  // are available. Otherwise fp cmovs get lowered into a less efficient branch
12527  // sequence later on.
12528  if (Cond.getOpcode() == ISD::SETCC &&
12529  ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
12530  (Subtarget->hasSSE1() && VT == MVT::f32)) &&
12531  VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
12532  SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
12533  int SSECC = translateX86FSETCC(
12534  cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
12535 
12536  if (SSECC != 8) {
12537  if (Subtarget->hasAVX512()) {
12538  SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
12539  DAG.getConstant(SSECC, MVT::i8));
12540  return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
12541  }
12542  SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
12543  DAG.getConstant(SSECC, MVT::i8));
12544  SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
12545  SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
12546  return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
12547  }
12548  }
12549 
12550  if (Cond.getOpcode() == ISD::SETCC) {
12551  SDValue NewCond = LowerSETCC(Cond, DAG);
12552  if (NewCond.getNode())
12553  Cond = NewCond;
12554  }
12555 
12556  // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
12557  // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
12558  // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
12559  // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
12560  if (Cond.getOpcode() == X86ISD::SETCC &&
12561  Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
12562  isZero(Cond.getOperand(1).getOperand(1))) {
12563  SDValue Cmp = Cond.getOperand(1);
12564 
12565  unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
12566 
12567  if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
12568  (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
12569  SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
12570 
12571  SDValue CmpOp0 = Cmp.getOperand(0);
12572  // Apply further optimizations for special cases
12573  // (select (x != 0), -1, 0) -> neg & sbb
12574  // (select (x == 0), 0, -1) -> neg & sbb
12575  if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
12576  if (YC->isNullValue() &&
12577  (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
12578  SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
12579  SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
12580  DAG.getConstant(0, CmpOp0.getValueType()),
12581  CmpOp0);
12582  SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12583  DAG.getConstant(X86::COND_B, MVT::i8),
12584  SDValue(Neg.getNode(), 1));
12585  return Res;
12586  }
12587 
12588  Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
12589  CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
12590  Cmp = ConvertCmpIfNecessary(Cmp, DAG);
12591 
12592  SDValue Res = // Res = 0 or -1.
12593  DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12594  DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
12595 
12596  if (isAllOnes(Op1) != (CondCode == X86::COND_E))
12597  Res = DAG.getNOT(DL, Res, Res.getValueType());
12598 
12599  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
12600  if (!N2C || !N2C->isNullValue())
12601  Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
12602  return Res;
12603  }
12604  }
12605 
12606  // Look past (and (setcc_carry (cmp ...)), 1).
12607  if (Cond.getOpcode() == ISD::AND &&
12608  Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12609  ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12610  if (C && C->getAPIntValue() == 1)
12611  Cond = Cond.getOperand(0);
12612  }
12613 
12614  // If condition flag is set by a X86ISD::CMP, then use it as the condition
12615  // setting operand in place of the X86ISD::SETCC.
12616  unsigned CondOpcode = Cond.getOpcode();
12617  if (CondOpcode == X86ISD::SETCC ||
12618  CondOpcode == X86ISD::SETCC_CARRY) {
12619  CC = Cond.getOperand(0);
12620 
12621  SDValue Cmp = Cond.getOperand(1);
12622  unsigned Opc = Cmp.getOpcode();
12623  MVT VT = Op.getSimpleValueType();
12624 
12625  bool IllegalFPCMov = false;
12626  if (VT.isFloatingPoint() && !VT.isVector() &&
12627  !isScalarFPTypeInSSEReg(VT)) // FPStack?
12628  IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
12629 
12630  if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
12631  Opc == X86ISD::BT) { // FIXME
12632  Cond = Cmp;
12633  addTest = false;
12634  }
12635  } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12636  CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12637  ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12638  Cond.getOperand(0).getValueType() != MVT::i8)) {
12639  SDValue LHS = Cond.getOperand(0);
12640  SDValue RHS = Cond.getOperand(1);
12641  unsigned X86Opcode;
12642  unsigned X86Cond;
12643  SDVTList VTs;
12644  switch (CondOpcode) {
12645  case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12646  case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12647  case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12648  case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12649  case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12650  case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12651  default: llvm_unreachable("unexpected overflowing operator");
12652  }
12653  if (CondOpcode == ISD::UMULO)
12654  VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12655  MVT::i32);
12656  else
12657  VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12658 
12659  SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
12660 
12661  if (CondOpcode == ISD::UMULO)
12662  Cond = X86Op.getValue(2);
12663  else
12664  Cond = X86Op.getValue(1);
12665 
12666  CC = DAG.getConstant(X86Cond, MVT::i8);
12667  addTest = false;
12668  }
12669 
12670  if (addTest) {
12671  // Look pass the truncate if the high bits are known zero.
12672  if (isTruncWithZeroHighBitsInput(Cond, DAG))
12673  Cond = Cond.getOperand(0);
12674 
12675  // We know the result of AND is compared against zero. Try to match
12676  // it to BT.
12677  if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
12678  SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
12679  if (NewSetCC.getNode()) {
12680  CC = NewSetCC.getOperand(0);
12681  Cond = NewSetCC.getOperand(1);
12682  addTest = false;
12683  }
12684  }
12685  }
12686 
12687  if (addTest) {
12688  CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12689  Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
12690  }
12691 
12692  // a < b ? -1 : 0 -> RES = ~setcc_carry
12693  // a < b ? 0 : -1 -> RES = setcc_carry
12694  // a >= b ? -1 : 0 -> RES = setcc_carry
12695  // a >= b ? 0 : -1 -> RES = ~setcc_carry
12696  if (Cond.getOpcode() == X86ISD::SUB) {
12697  Cond = ConvertCmpIfNecessary(Cond, DAG);
12698  unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
12699 
12700  if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
12701  (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
12702  SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12703  DAG.getConstant(X86::COND_B, MVT::i8), Cond);
12704  if (isAllOnes(Op1) != (CondCode == X86::COND_B))
12705  return DAG.getNOT(DL, Res, Res.getValueType());
12706  return Res;
12707  }
12708  }
12709 
12710  // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
12711  // widen the cmov and push the truncate through. This avoids introducing a new
12712  // branch during isel and doesn't add any extensions.
12713  if (Op.getValueType() == MVT::i8 &&
12714  Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
12715  SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
12716  if (T1.getValueType() == T2.getValueType() &&
12717  // Blacklist CopyFromReg to avoid partial register stalls.
12718  T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
12719  SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
12720  SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
12721  return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
12722  }
12723  }
12724 
12725  // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
12726  // condition is true.
12727  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
12728  SDValue Ops[] = { Op2, Op1, CC, Cond };
12729  return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
12730 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::X86TargetLowering::ConvertCmpIfNecessary
SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const
Convert a comparison if required by the subtarget.
Definition: X86ISelLowering.cpp:11926
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::SDNode::hasOneUse
bool hasOneUse() const
Definition: SelectionDAGNodes.h:438
translateX86FSETCC
static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0, SDValue &Op1)
Turns an ISD::CondCode into a value suitable for SSE floating point mask CMPs.
Definition: X86ISelLowering.cpp:12027
llvm::SDValue::hasOneUse
bool hasOneUse() const
Definition: SelectionDAGNodes.h:910
isZero
static bool isZero(SDValue V)
isZero - Returns true if Elt is a constant integer zero
Definition: X86ISelLowering.cpp:4755
isAllOnes
static bool isAllOnes(SDValue V)
Definition: X86ISelLowering.cpp:11949
llvm::X86TargetLowering::LowerToBT
SDValue LowerToBT(SDValue And, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:11956
llvm::X86TargetLowering::EmitTest
SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:11654
llvm::ISD::SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:221
llvm::X86TargetLowering::LowerSETCC
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:12407
llvm::X86ISD::BT
X86 bit-test instructions.
Definition: X86ISelLowering.h:96
isX86LogicalCmp
static bool isX86LogicalCmp(SDValue Op)
Definition: X86ISelLowering.cpp:12481
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::X86ISD::CMP
X86 compare and logical compare instructions.
Definition: X86ISelLowering.h:93
llvm::ConstantSDNode::getAPIntValue
const APInt & getAPIntValue() const
Definition: SelectionDAGNodes.h:1349
isTruncWithZeroHighBitsInput
static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:12506
llvm::X86Subtarget::hasSSE2
bool hasSSE2() const
Definition: X86Subtarget.h:312
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::MVT::isVector
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: MachineValueType.h:185
llvm::MVT::isFloatingPoint
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: MachineValueType.h:169
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::SelectionDAG::getNOT
SDValue getNOT(SDLoc DL, SDValue Val, EVT VT)
getNOT - Create a bitwise NOT operation as (XOR Val, -1).
Definition: SelectionDAG.cpp:1068
llvm::dyn_cast
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::APIntOps::And
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1865
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:311
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
llvm::X86Subtarget::hasAVX512
bool hasAVX512() const
Definition: X86Subtarget.h:319
llvm::ISD::SMULO
Same for multiplication.
Definition: ISDOpcodes.h:224
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
hasFPCMov
static bool hasFPCMov(unsigned X86CC)
Definition: X86ISelLowering.cpp:3643
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml","ocaml 3.10-compatible collector")
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
llvm::X86TargetLowering::isScalarFPTypeInSSEReg
bool isScalarFPTypeInSSEReg(EVT VT) const
Definition: X86ISelLowering.h:752
T1
#define T1
Definition: Mips16ISelLowering.cpp:348
SDValue X86TargetLowering::LowerSETCC ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 12407 of file X86ISelLowering.cpp.

12407  {
12408 
12409  MVT VT = Op.getSimpleValueType();
12410 
12411  if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
12412 
12413  assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
12414  && "SetCC type must be 8-bit or 1-bit integer");
12415  SDValue Op0 = Op.getOperand(0);
12416  SDValue Op1 = Op.getOperand(1);
12417  SDLoc dl(Op);
12418  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
12419 
12420  // Optimize to BT if possible.
12421  // Lower (X & (1 << N)) == 0 to BT(X, N).
12422  // Lower ((X >>u N) & 1) != 0 to BT(X, N).
12423  // Lower ((X >>s N) & 1) != 0 to BT(X, N).
12424  if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
12425  Op1.getOpcode() == ISD::Constant &&
12426  cast<ConstantSDNode>(Op1)->isNullValue() &&
12427  (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12428  SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
12429  if (NewSetCC.getNode())
12430  return NewSetCC;
12431  }
12432 
12433  // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
12434  // these.
12435  if (Op1.getOpcode() == ISD::Constant &&
12436  (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
12437  cast<ConstantSDNode>(Op1)->isNullValue()) &&
12438  (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12439 
12440  // If the input is a setcc, then reuse the input setcc or use a new one with
12441  // the inverted condition.
12442  if (Op0.getOpcode() == X86ISD::SETCC) {
12443  X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
12444  bool Invert = (CC == ISD::SETNE) ^
12445  cast<ConstantSDNode>(Op1)->isNullValue();
12446  if (!Invert)
12447  return Op0;
12448 
12449  CCode = X86::GetOppositeBranchCondition(CCode);
12450  SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12451  DAG.getConstant(CCode, MVT::i8),
12452  Op0.getOperand(1));
12453  if (VT == MVT::i1)
12454  return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12455  return SetCC;
12456  }
12457  }
12458  if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
12459  (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
12460  (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12461 
12462  ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
12463  return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
12464  }
12465 
12466  bool isFP = Op1.getSimpleValueType().isFloatingPoint();
12467  unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
12468  if (X86CC == X86::COND_INVALID)
12469  return SDValue();
12470 
12471  SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
12472  EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
12473  SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12474  DAG.getConstant(X86CC, MVT::i8), EFLAGS);
12475  if (VT == MVT::i1)
12476  return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12477  return SetCC;
12478 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::X86TargetLowering::ConvertCmpIfNecessary
SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const
Convert a comparison if required by the subtarget.
Definition: X86ISelLowering.cpp:11926
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SDValue::hasOneUse
bool hasOneUse() const
Definition: SelectionDAGNodes.h:910
llvm::X86TargetLowering::LowerToBT
SDValue LowerToBT(SDValue And, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:11956
TranslateX86CC
static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:3555
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::MVT::isVector
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: MachineValueType.h:185
llvm::MVT::isFloatingPoint
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: MachineValueType.h:169
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::X86::GetOppositeBranchCondition
CondCode GetOppositeBranchCondition(CondCode CC)
Definition: X86InstrInfo.cpp:2630
llvm::X86TargetLowering::EmitCmp
SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:11891
llvm::ISD::getSetCCInverse
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
Definition: SelectionDAG.cpp:265
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::SDValue::getConstantOperandVal
uint64_t getConstantOperandVal(unsigned i) const
Definition: SelectionDAGNodes.h:892
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
llvm::X86Subtarget::hasAVX512
bool hasAVX512() const
Definition: X86Subtarget.h:319
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::SelectionDAG::getSetCC
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Definition: SelectionDAG.h:690
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
LowerVSETCC
static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:12170
SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 15883 of file X86ISelLowering.cpp.

15884  {
15885  SDLoc dl(Op);
15886  EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
15887  MVT VT = Op.getSimpleValueType();
15888 
15889  if (!Subtarget->hasSSE2() || !VT.isVector())
15890  return SDValue();
15891 
15892  unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
15893  ExtraVT.getScalarType().getSizeInBits();
15894 
15895  switch (VT.SimpleTy) {
15896  default: return SDValue();
15897  case MVT::v8i32:
15898  case MVT::v16i16:
15899  if (!Subtarget->hasFp256())
15900  return SDValue();
15901  if (!Subtarget->hasInt256()) {
15902  // needs to be split
15903  unsigned NumElems = VT.getVectorNumElements();
15904 
15905  // Extract the LHS vectors
15906  SDValue LHS = Op.getOperand(0);
15907  SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15908  SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15909 
15910  MVT EltVT = VT.getVectorElementType();
15911  EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15912 
15913  EVT ExtraEltVT = ExtraVT.getVectorElementType();
15914  unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
15915  ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
15916  ExtraNumElems/2);
15917  SDValue Extra = DAG.getValueType(ExtraVT);
15918 
15919  LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
15920  LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
15921 
15922  return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
15923  }
15924  // fall through
15925  case MVT::v4i32:
15926  case MVT::v8i16: {
15927  SDValue Op0 = Op.getOperand(0);
15928  SDValue Op00 = Op0.getOperand(0);
15929  SDValue Tmp1;
15930  // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
15931  if (Op0.getOpcode() == ISD::BITCAST &&
15932  Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
15933  // (sext (vzext x)) -> (vsext x)
15934  Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
15935  if (Tmp1.getNode()) {
15936  EVT ExtraEltVT = ExtraVT.getVectorElementType();
15937  // This folding is only valid when the in-reg type is a vector of i8,
15938  // i16, or i32.
15939  if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
15940  ExtraEltVT == MVT::i32) {
15941  SDValue Tmp1Op0 = Tmp1.getOperand(0);
15942  assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
15943  "This optimization is invalid without a VZEXT.");
15944  return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
15945  }
15946  Op0 = Tmp1;
15947  }
15948  }
15949 
15950  // If the above didn't work, then just use Shift-Left + Shift-Right.
15951  Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
15952  DAG);
15953  return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
15954  DAG);
15955  }
15956  }
15957 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:505
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:156
llvm::MVT::getScalarType
MVT getScalarType() const
Definition: MachineValueType.h:260
llvm::EVT::getScalarType
EVT getScalarType() const
Definition: ValueTypes.h:211
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Definition: ValueTypes.h:217
llvm::X86Subtarget::hasSSE2
bool hasSSE2() const
Definition: X86Subtarget.h:312
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:312
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::MVT::isVector
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: MachineValueType.h:185
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::X86Subtarget::hasFp256
bool hasFp256() const
Definition: X86Subtarget.h:320
llvm::EVT::getVectorVT
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
Extract128BitVector
static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl)
Definition: X86ISelLowering.cpp:118
LowerVectorIntExtend
static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:9114
llvm::X86Subtarget::hasInt256
bool hasInt256() const
Definition: X86Subtarget.h:321
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1419
getTargetVShiftByConstNode
static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT, SDValue SrcOp, uint64_t ShiftAmt, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:13375
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:264
llvm::EVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
SDValue X86TargetLowering::LowerSINT_TO_FP ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 10677 of file X86ISelLowering.cpp.

10678  {
10679  MVT SrcVT = Op.getOperand(0).getSimpleValueType();
10680 
10681  if (SrcVT.isVector())
10682  return SDValue();
10683 
10684  assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
10685  "Unknown SINT_TO_FP to lower!");
10686 
10687  // These are really Legal; return the operand so the caller accepts it as
10688  // Legal.
10689  if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
10690  return Op;
10691  if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
10692  Subtarget->is64Bit()) {
10693  return Op;
10694  }
10695 
10696  SDLoc dl(Op);
10697  unsigned Size = SrcVT.getSizeInBits()/8;
10698  MachineFunction &MF = DAG.getMachineFunction();
10699  int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
10700  SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10701  SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10702  StackSlot,
10703  MachinePointerInfo::getFixedStack(SSFI),
10704  false, false, 0);
10705  return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
10706 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
Definition: MachineInstr.cpp:414
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
assert
assert(Globals.size() > 1)
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::MVT::isVector
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: MachineValueType.h:185
llvm::X86TargetLowering::BuildFILD
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10708
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
Definition: SelectionDAG.cpp:4815
llvm::MachineFunction::getFrameInfo
MachineFrameInfo * getFrameInfo()
Definition: MachineFunction.h:174
llvm::MachineFrameInfo::CreateStackObject
int CreateStackObject(uint64_t Size, unsigned Alignment, bool isSS, const AllocaInst *Alloca=nullptr)
Definition: MachineFunction.cpp:513
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1297
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
llvm::X86TargetLowering::isScalarFPTypeInSSEReg
bool isScalarFPTypeInSSEReg(EVT VT) const
Definition: X86ISelLowering.h:752
SDValue X86TargetLowering::LowerToBT ( SDValue  And,
ISD::CondCode  CC,
SDLoc  dl,
SelectionDAG &  DAG 
) const
private

LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node if it's possible.

Definition at line 11956 of file X86ISelLowering.cpp.

11957  {
11958  SDValue Op0 = And.getOperand(0);
11959  SDValue Op1 = And.getOperand(1);
11960  if (Op0.getOpcode() == ISD::TRUNCATE)
11961  Op0 = Op0.getOperand(0);
11962  if (Op1.getOpcode() == ISD::TRUNCATE)
11963  Op1 = Op1.getOperand(0);
11964 
11965  SDValue LHS, RHS;
11966  if (Op1.getOpcode() == ISD::SHL)
11967  std::swap(Op0, Op1);
11968  if (Op0.getOpcode() == ISD::SHL) {
11969  if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
11970  if (And00C->getZExtValue() == 1) {
11971  // If we looked past a truncate, check that it's only truncating away
11972  // known zeros.
11973  unsigned BitWidth = Op0.getValueSizeInBits();
11974  unsigned AndBitWidth = And.getValueSizeInBits();
11975  if (BitWidth > AndBitWidth) {
11976  APInt Zeros, Ones;
11977  DAG.computeKnownBits(Op0, Zeros, Ones);
11978  if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
11979  return SDValue();
11980  }
11981  LHS = Op1;
11982  RHS = Op0.getOperand(1);
11983  }
11984  } else if (Op1.getOpcode() == ISD::Constant) {
11985  ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
11986  uint64_t AndRHSVal = AndRHS->getZExtValue();
11987  SDValue AndLHS = Op0;
11988 
11989  if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
11990  LHS = AndLHS.getOperand(0);
11991  RHS = AndLHS.getOperand(1);
11992  }
11993 
11994  // Use BT if the immediate can't be encoded in a TEST instruction.
11995  if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
11996  LHS = AndLHS;
11997  RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
11998  }
11999  }
12000 
12001  if (LHS.getNode()) {
12002  // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12003  // instruction. Since the shift amount is in-range-or-undefined, we know
12004  // that doing a bittest on the i32 value is ok. We extend to i32 because
12005  // the encoding for the i16 version is larger than the i32 version.
12006  // Also promote i16 to i32 for performance / code size reason.
12007  if (LHS.getValueType() == MVT::i8 ||
12008  LHS.getValueType() == MVT::i16)
12009  LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12010 
12011  // If the operand types disagree, extend the shift amount to match. Since
12012  // BT ignores high bits (like shifts) we can use anyextend.
12013  if (LHS.getValueType() != RHS.getValueType())
12014  RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12015 
12016  SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12017  X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12018  return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12019  DAG.getConstant(Cond, MVT::i8), BT);
12020  }
12021 
12022  return SDValue();
12023 }
llvm::SelectionDAG::computeKnownBits
void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, unsigned Depth=0) const
Definition: SelectionDAG.cpp:1943
llvm::SDValue::getValueSizeInBits
unsigned getValueSizeInBits() const
Definition: SelectionDAGNodes.h:168
llvm::X86ISD::BT
X86 bit-test instructions.
Definition: X86ISelLowering.h:96
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::Log2_64_Ceil
unsigned Log2_64_Ceil(uint64_t Value)
Definition: MathExtras.h:471
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::isUInt< 32 >
bool isUInt< 32 >(uint64_t x)
Definition: MathExtras.h:311
llvm::isPowerOf2_64
bool isPowerOf2_64(uint64_t Value)
Definition: MathExtras.h:369
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
llvm::APInt::countLeadingOnes
unsigned countLeadingOnes() const
Count the number of leading one bits.
Definition: APInt.cpp:710
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
llvm::ConstantSDNode::getZExtValue
uint64_t getZExtValue() const
Definition: SelectionDAGNodes.h:1350
SDValue X86TargetLowering::LowerTRUNCATE ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 11186 of file X86ISelLowering.cpp.

11186  {
11187  SDLoc DL(Op);
11188  MVT VT = Op.getSimpleValueType();
11189  SDValue In = Op.getOperand(0);
11190  MVT InVT = In.getSimpleValueType();
11191 
11192  if (VT == MVT::i1) {
11193  assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11194  "Invalid scalar TRUNCATE operation");
11195  if (InVT == MVT::i32)
11196  return SDValue();
11197  if (InVT.getSizeInBits() == 64)
11198  In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
11199  else if (InVT.getSizeInBits() < 32)
11200  In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11201  return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11202  }
11203  assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11204  "Invalid TRUNCATE operation");
11205 
11206  if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11207  if (VT.getVectorElementType().getSizeInBits() >=8)
11208  return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11209 
11210  assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11211  unsigned NumElts = InVT.getVectorNumElements();
11212  assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11213  if (InVT.getSizeInBits() < 512) {
11214  MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11215  In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11216  InVT = ExtVT;
11217  }
11218 
11219  SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11220  const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11221  SDValue CP = DAG.getConstantPool(C, getPointerTy());
11222  unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11223  SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11224  MachinePointerInfo::getConstantPool(),
11225  false, false, false, Alignment);
11226  SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11227  SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11228  return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11229  }
11230 
11231  if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11232  // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11233  if (Subtarget->hasInt256()) {
11234  static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11235  In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11236  In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11237  ShufMask);
11238  return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11239  DAG.getIntPtrConstant(0));
11240  }
11241 
11242  SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11243  DAG.getIntPtrConstant(0));
11244  SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11245  DAG.getIntPtrConstant(2));
11246  OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11247  OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11248  static const int ShufMask[] = {0, 2, 4, 6};
11249  return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11250  }
11251 
11252  if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11253  // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11254  if (Subtarget->hasInt256()) {
11255  In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11256 
11257  SmallVector<SDValue,32> pshufbMask;
11258  for (unsigned i = 0; i < 2; ++i) {
11259  pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11260  pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11261  pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11262  pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11263  pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11264  pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11265  pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11266  pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11267  for (unsigned j = 0; j < 8; ++j)
11268  pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11269  }
11270  SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11271  In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11272  In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11273 
11274  static const int ShufMask[] = {0, 2, -1, -1};
11275  In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11276  &ShufMask[0]);
11277  In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11278  DAG.getIntPtrConstant(0));
11279  return DAG.getNode(ISD::BITCAST, DL, VT, In);
11280  }
11281 
11282  SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11283  DAG.getIntPtrConstant(0));
11284 
11285  SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11286  DAG.getIntPtrConstant(4));
11287 
11288  OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11289  OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11290 
11291  // The PSHUFB mask:
11292  static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11293  -1, -1, -1, -1, -1, -1, -1, -1};
11294 
11295  SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11296  OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11297  OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
11298 
11299  OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11300  OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11301 
11302  // The MOVLHPS Mask:
11303  static const int ShufMask2[] = {0, 1, 4, 5};
11304  SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
11305  return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
11306  }
11307 
11308  // Handle truncation of V256 to V128 using shuffles.
11309  if (!VT.is128BitVector() || !InVT.is256BitVector())
11310  return SDValue();
11311 
11312  assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
11313 
11314  unsigned NumElems = VT.getVectorNumElements();
11315  MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
11316 
11317  SmallVector<int, 16> MaskVec(NumElems * 2, -1);
11318  // Prepare truncation shuffle mask
11319  for (unsigned i = 0; i != NumElems; ++i)
11320  MaskVec[i] = i * 2;
11321  SDValue V = DAG.getVectorShuffle(NVT, DL,
11322  DAG.getNode(ISD::BITCAST, DL, NVT, In),
11323  DAG.getUNDEF(NVT), &MaskVec[0]);
11324  return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
11325  DAG.getIntPtrConstant(0));
11326 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86ISD::PSHUFB
PSHUFB - Shuffle 16 8-bit values within a vector.
Definition: X86ISelLowering.h:182
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:505
llvm::MVT::is512BitVector
bool is512BitVector() const
is512BitVector - Return true if this is a 512-bit vector type.
Definition: MachineValueType.h:224
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm::MachinePointerInfo::getConstantPool
static MachinePointerInfo getConstantPool()
Definition: MachineInstr.cpp:408
llvm::SelectionDAG::getConstantPool
SDValue getConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offs=0, bool isT=false, unsigned char TargetFlags=0)
Definition: SelectionDAG.cpp:1332
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::SelectionDAG::getVectorShuffle
SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2, const int *MaskElts)
Definition: SelectionDAG.cpp:1479
llvm::SelectionDAG::getUNDEF
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
assert
assert(Globals.size() > 1)
llvm::MVT::isInteger
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: MachineValueType.h:177
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:312
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::Constant
LLVM Constant Representation.
Definition: Constant.h:41
llvm::X86Subtarget::hasFp256
bool hasFp256() const
Definition: X86Subtarget.h:320
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::SelectionDAG::getTargetConstant
SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque=false)
Definition: SelectionDAG.h:406
llvm::MVT::is128BitVector
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
Definition: MachineValueType.h:210
llvm::X86Subtarget::hasInt256
bool hasInt256() const
Definition: X86Subtarget.h:321
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::dyn_cast
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
llvm::APIntOps::And
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1865
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
llvm::MVT::is256BitVector
bool is256BitVector() const
is256BitVector - Return true if this is a 256-bit vector type.
Definition: MachineValueType.h:217
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:264
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
SDValue X86TargetLowering::LowerUINT_TO_FP ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 10898 of file X86ISelLowering.cpp.

10899  {
10900  SDValue N0 = Op.getOperand(0);
10901  SDLoc dl(Op);
10902 
10903  if (Op.getValueType().isVector())
10904  return lowerUINT_TO_FP_vec(Op, DAG);
10905 
10906  // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
10907  // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
10908  // the optimization here.
10909  if (DAG.SignBitIsZero(N0))
10910  return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
10911 
10912  MVT SrcVT = N0.getSimpleValueType();
10913  MVT DstVT = Op.getSimpleValueType();
10914  if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
10915  return LowerUINT_TO_FP_i64(Op, DAG);
10916  if (SrcVT == MVT::i32 && X86ScalarSSEf64)
10917  return LowerUINT_TO_FP_i32(Op, DAG);
10918  if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
10919  return SDValue();
10920 
10921  // Make a 64-bit buffer, and use it to build an FILD.
10922  SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
10923  if (SrcVT == MVT::i32) {
10924  SDValue WordOff = DAG.getConstant(4, getPointerTy());
10925  SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
10926  getPointerTy(), StackSlot, WordOff);
10927  SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10928  StackSlot, MachinePointerInfo(),
10929  false, false, 0);
10930  SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
10931  OffsetSlot, MachinePointerInfo(),
10932  false, false, 0);
10933  SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
10934  return Fild;
10935  }
10936 
10937  assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
10938  SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10939  StackSlot, MachinePointerInfo(),
10940  false, false, 0);
10941  // For i64 source, we need to add the appropriate power of 2 if the input
10942  // was negative. This is the same as the optimization in
10943  // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
10944  // we must be careful to do the computation in x87 extended precision, not
10945  // in SSE. (The generic code can't know it's OK to do this, or how to.)
10946  int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
10947  MachineMemOperand *MMO =
10948  DAG.getMachineFunction()
10949  .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10950  MachineMemOperand::MOLoad, 8, 8);
10951 
10952  SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
10953  SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
10954  SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
10955  MVT::i64, MMO);
10956 
10957  APInt FF(32, 0x5F800000ULL);
10958 
10959  // Check whether the sign bit is set.
10960  SDValue SignSet = DAG.getSetCC(dl,
10961  getSetCCResultType(*DAG.getContext(), MVT::i64),
10962  Op.getOperand(0), DAG.getConstant(0, MVT::i64),
10963  ISD::SETLT);
10964 
10965  // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
10966  SDValue FudgePtr = DAG.getConstantPool(
10967  ConstantInt::get(*DAG.getContext(), FF.zext(64)),
10968  getPointerTy());
10969 
10970  // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
10971  SDValue Zero = DAG.getIntPtrConstant(0);
10972  SDValue Four = DAG.getIntPtrConstant(4);
10973  SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
10974  Zero, Four);
10975  FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
10976 
10977  // Load the value out, extending it from f32 to f80.
10978  // FIXME: Avoid the extend by constructing the right constant pool?
10979  SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
10980  FudgePtr, MachinePointerInfo::getConstantPool(),
10981  MVT::f32, false, false, 4);
10982  // Extend everything to 80 bits to force it to be done on x87.
10983  SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
10984  return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
10985 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::MachineMemOperand::MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:101
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::X86TargetLowering::LowerUINT_TO_FP_i64
SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10770
llvm::SelectionDAG::getExtLoad
SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
Definition: SelectionDAG.cpp:4783
llvm::MachinePointerInfo::getConstantPool
static MachinePointerInfo getConstantPool()
Definition: MachineInstr.cpp:408
llvm::SelectionDAG::getConstantPool
SDValue getConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offs=0, bool isT=false, unsigned char TargetFlags=0)
Definition: SelectionDAG.cpp:1332
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(int FI, int64_t offset=0)
Definition: MachineInstr.cpp:414
llvm::EVT::isVector
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::X86TargetLowering::lowerUINT_TO_FP_vec
SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10883
assert
assert(Globals.size() > 1)
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::ISD::FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:227
llvm::X86TargetLowering::LowerUINT_TO_FP_i32
SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10837
llvm::X86TargetLowering::BuildFILD
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:10708
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
Definition: SelectionDAG.cpp:4815
llvm::SelectionDAG::CreateStackTemporary
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Definition: SelectionDAG.cpp:1782
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool isSigned=false)
Definition: Constants.cpp:528
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, unsigned f, uint64_t s, unsigned base_alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: MachineFunction.cpp:230
llvm::X86TargetLowering::getSetCCResultType
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the value type to use for ISD::SETCC.
Definition: X86ISelLowering.cpp:1631
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getMemIntrinsicNode
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true)
Definition: SelectionDAG.cpp:4586
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1419
llvm::SelectionDAG::getSetCC
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Definition: SelectionDAG.h:690
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
llvm::SelectionDAG::SignBitIsZero
bool SignBitIsZero(SDValue Op, unsigned Depth=0) const
Definition: SelectionDAG.cpp:1922
SDValue X86TargetLowering::LowerUINT_TO_FP_i32 ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 10837 of file X86ISelLowering.cpp.

10838  {
10839  SDLoc dl(Op);
10840  // FP constant to bias correct the final result.
10841  SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
10842  MVT::f64);
10843 
10844  // Load the 32-bit value into an XMM register.
10845  SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
10846  Op.getOperand(0));
10847 
10848  // Zero out the upper parts of the register.
10849  Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
10850 
10851  Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
10852  DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
10853  DAG.getIntPtrConstant(0));
10854 
10855  // Or the load with the bias.
10856  SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
10857  DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
10858  DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10859  MVT::v2f64, Load)),
10860  DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
10861  DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10862  MVT::v2f64, Bias)));
10863  Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
10864  DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
10865  DAG.getIntPtrConstant(0));
10866 
10867  // Subtract the bias.
10868  SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
10869 
10870  // Handle final rounding.
10871  EVT DestVT = Op.getValueType();
10872 
10873  if (DestVT.bitsLT(MVT::f64))
10874  return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
10875  DAG.getIntPtrConstant(0));
10876  if (DestVT.bitsGT(MVT::f64))
10877  return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
10878 
10879  // Handle final rounding.
10880  return Sub;
10881 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::EVT::bitsLT
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
Definition: ValueTypes.h:190
llvm::SelectionDAG::getConstantFP
SDValue getConstantFP(double Val, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1243
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::APIntOps::Or
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1870
llvm::ISD::FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
llvm::EVT::bitsGT
bool bitsGT(EVT VT) const
bitsGT - Return true if this has more bits than VT.
Definition: ValueTypes.h:178
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::BitsToDouble
double BitsToDouble(uint64_t Bits)
Definition: MathExtras.h:488
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
getShuffleVectorZeroOrUndef
static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, bool IsZero, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:5090
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
SDValue X86TargetLowering::LowerUINT_TO_FP_i64 ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 10770 of file X86ISelLowering.cpp.

10771  {
10772  // This algorithm is not obvious. Here it is what we're trying to output:
10773  /*
10774  movq %rax, %xmm0
10775  punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
10776  subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
10777  #ifdef __SSE3__
10778  haddpd %xmm0, %xmm0
10779  #else
10780  pshufd $0x4e, %xmm0, %xmm1
10781  addpd %xmm1, %xmm0
10782  #endif
10783  */
10784 
10785  SDLoc dl(Op);
10786  LLVMContext *Context = DAG.getContext();
10787 
10788  // Build some magic constants.
10789  static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
10790  Constant *C0 = ConstantDataVector::get(*Context, CV0);
10791  SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
10792 
10793  SmallVector<Constant*,2> CV1;
10794  CV1.push_back(
10795  ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
10796  APInt(64, 0x4330000000000000ULL))));
10797  CV1.push_back(
10798  ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
10799  APInt(64, 0x4530000000000000ULL))));
10800  Constant *C1 = ConstantVector::get(CV1);
10801  SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
10802 
10803  // Load the 64-bit value into an XMM register.
10804  SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
10805  Op.getOperand(0));
10806  SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
10807  MachinePointerInfo::getConstantPool(),
10808  false, false, false, 16);
10809  SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
10810  DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
10811  CLod0);
10812 
10813  SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
10814  MachinePointerInfo::getConstantPool(),
10815  false, false, false, 16);
10816  SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
10817  SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
10818  SDValue Result;
10819 
10820  if (Subtarget->hasSSE3()) {
10821  // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
10822  Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
10823  } else {
10824  SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
10825  SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
10826  S2F, 0x4E, DAG);
10827  Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
10828  DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
10829  Sub);
10830  }
10831 
10832  return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
10833  DAG.getIntPtrConstant(0));
10834 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::X86Subtarget::hasSSE3
bool hasSSE3() const
Definition: X86Subtarget.h:313
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::APFloat::IEEEdouble
static const fltSemantics IEEEdouble
Definition: APFloat.h:133
llvm::MachinePointerInfo::getConstantPool
static MachinePointerInfo getConstantPool()
Definition: MachineInstr.cpp:408
llvm::SelectionDAG::getConstantPool
SDValue getConstantPool(const Constant *C, EVT VT, unsigned Align=0, int Offs=0, bool isT=false, unsigned char TargetFlags=0)
Definition: SelectionDAG.cpp:1332
getTargetShuffleNode
static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, SDValue V1, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:3405
llvm::ConstantVector::get
static Constant * get(ArrayRef< Constant * > V)
Definition: Constants.cpp:961
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::ISD::FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:227
llvm::Constant
LLVM Constant Representation.
Definition: Constant.h:41
getUnpackl
static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1, SDValue V2)
getUnpackl - Returns a vector_shuffle node for an unpackl operation.
Definition: X86ISelLowering.cpp:4977
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::ConstantFP::get
static Constant * get(Type *Ty, double V)
Definition: Constants.cpp:593
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
testing::internal::Shuffle
void Shuffle(internal::Random *random, std::vector< E > *v)
Definition: gtest-internal-inl.h:322
llvm::X86ISD::FHADD
FHADD - Floating point horizontal add.
Definition: X86ISelLowering.h:206
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
llvm::ConstantDataVector::get
static Constant * get(LLVMContext &Context, ArrayRef< uint8_t > Elts)
Definition: Constants.cpp:2447
SDValue X86TargetLowering::lowerUINT_TO_FP_vec ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 10883 of file X86ISelLowering.cpp.

10884  {
10885  SDValue N0 = Op.getOperand(0);
10886  MVT SVT = N0.getSimpleValueType();
10887  SDLoc dl(Op);
10888 
10889  assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
10890  SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
10891  "Custom UINT_TO_FP is not supported!");
10892 
10893  MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
10894  return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
10895  DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
10896 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:505
assert
assert(Globals.size() > 1)
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:312
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
SDValue X86TargetLowering::LowerVAARG ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 13289 of file X86ISelLowering.cpp.

13289  {
13290  assert(Subtarget->is64Bit() &&
13291  "LowerVAARG only handles 64-bit va_arg!");
13292  assert((Subtarget->isTargetLinux() ||
13293  Subtarget->isTargetDarwin()) &&
13294  "Unhandled target in LowerVAARG");
13295  assert(Op.getNode()->getNumOperands() == 4);
13296  SDValue Chain = Op.getOperand(0);
13297  SDValue SrcPtr = Op.getOperand(1);
13298  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13299  unsigned Align = Op.getConstantOperandVal(3);
13300  SDLoc dl(Op);
13301 
13302  EVT ArgVT = Op.getNode()->getValueType(0);
13303  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13304  uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
13305  uint8_t ArgMode;
13306 
13307  // Decide which area this value should be read from.
13308  // TODO: Implement the AMD64 ABI in its entirety. This simple
13309  // selection mechanism works only for the basic types.
13310  if (ArgVT == MVT::f80) {
13311  llvm_unreachable("va_arg for f80 not yet implemented");
13312  } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
13313  ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
13314  } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
13315  ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
13316  } else {
13317  llvm_unreachable("Unhandled argument type in LowerVAARG");
13318  }
13319 
13320  if (ArgMode == 2) {
13321  // Sanity Check: Make sure using fp_offset makes sense.
13322  assert(!DAG.getTarget().Options.UseSoftFloat &&
13323  !(DAG.getMachineFunction()
13324  .getFunction()->getAttributes()
13325  .hasAttribute(AttributeSet::FunctionIndex,
13326  Attribute::NoImplicitFloat)) &&
13327  Subtarget->hasSSE1());
13328  }
13329 
13330  // Insert VAARG_64 node into the DAG
13331  // VAARG_64 returns two values: Variable Argument Address, Chain
13332  SmallVector<SDValue, 11> InstOps;
13333  InstOps.push_back(Chain);
13334  InstOps.push_back(SrcPtr);
13335  InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
13336  InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
13337  InstOps.push_back(DAG.getConstant(Align, MVT::i32));
13338  SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
13339  SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
13340  VTs, InstOps, MVT::i64,
13341  MachinePointerInfo(SV),
13342  /*Align=*/0,
13343  /*Volatile=*/false,
13344  /*ReadMem=*/true,
13345  /*WriteMem=*/true);
13346  Chain = VAARG.getValue(1);
13347 
13348  // Load the next argument and return it
13349  return DAG.getLoad(ArgVT, dl,
13350  Chain,
13351  VAARG,
13352  MachinePointerInfo(),
13353  false, false, false, 0);
13354 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::SelectionDAG::getTarget
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:277
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
llvm::SDNode::getNumOperands
unsigned getNumOperands() const
Definition: SelectionDAGNodes.h:586
llvm::MachineFunction::getFunction
const Function * getFunction() const
Definition: MachineFunction.h:151
llvm::AttributeSet::hasAttribute
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Definition: Attributes.cpp:872
llvm::X86Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: X86Subtarget.h:370
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Definition: SelectionDAGNodes.h:648
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::EVT::isInteger
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::TargetLoweringBase::getDataLayout
const DataLayout * getDataLayout() const
Definition: TargetLowering.h:150
llvm::DataLayout::getTypeAllocSize
uint64_t getTypeAllocSize(Type *Ty) const
Definition: DataLayout.h:368
llvm::X86Subtarget::isTargetLinux
bool isTargetLinux() const
Definition: X86Subtarget.h:382
Align
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
llvm::Function::getAttributes
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:311
llvm::SDValue::getConstantOperandVal
uint64_t getConstantOperandVal(unsigned i) const
Definition: SelectionDAGNodes.h:892
llvm::EVT::isFloatingPoint
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
llvm::SelectionDAG::getMemIntrinsicNode
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true)
Definition: SelectionDAG.cpp:4586
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::Value
LLVM Value Representation.
Definition: Value.h:69
llvm::Attribute::NoImplicitFloat
Disable implicit floating point insts.
Definition: Attributes.h:86
SDValue X86TargetLowering::LowerVASTART ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 13229 of file X86ISelLowering.cpp.

13229  {
13230  MachineFunction &MF = DAG.getMachineFunction();
13231  X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
13232 
13233  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13234  SDLoc DL(Op);
13235 
13236  if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
13237  // vastart just stores the address of the VarArgsFrameIndex slot into the
13238  // memory location argument.
13239  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13240  getPointerTy());
13241  return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
13242  MachinePointerInfo(SV), false, false, 0);
13243  }
13244 
13245  // __va_list_tag:
13246  // gp_offset (0 - 6 * 8)
13247  // fp_offset (48 - 48 + 8 * 16)
13248  // overflow_arg_area (point to parameters coming in memory).
13249  // reg_save_area
13250  SmallVector<SDValue, 8> MemOps;
13251  SDValue FIN = Op.getOperand(1);
13252  // Store gp_offset
13253  SDValue Store = DAG.getStore(Op.getOperand(0), DL,
13254  DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
13255  MVT::i32),
13256  FIN, MachinePointerInfo(SV), false, false, 0);
13257  MemOps.push_back(Store);
13258 
13259  // Store fp_offset
13260  FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13261  FIN, DAG.getIntPtrConstant(4));
13262  Store = DAG.getStore(Op.getOperand(0), DL,
13263  DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
13264  MVT::i32),
13265  FIN, MachinePointerInfo(SV, 4), false, false, 0);
13266  MemOps.push_back(Store);
13267 
13268  // Store ptr to overflow_arg_area
13269  FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13270  FIN, DAG.getIntPtrConstant(4));
13271  SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13272  getPointerTy());
13273  Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
13274  MachinePointerInfo(SV, 8),
13275  false, false, 0);
13276  MemOps.push_back(Store);
13277 
13278  // Store ptr to reg_save_area.
13279  FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13280  FIN, DAG.getIntPtrConstant(8));
13281  SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
13282  getPointerTy());
13283  Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
13284  MachinePointerInfo(SV, 16), false, false, 0);
13285  MemOps.push_back(Store);
13286  return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
13287 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
llvm::TargetLoweringBase::DL
const DataLayout * DL
True if this is a little endian target.
Definition: TargetLowering.h:1453
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
Definition: SelectionDAG.cpp:4815
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::SelectionDAG::getFrameIndex
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1297
llvm::X86Subtarget::isTargetWin64
bool isTargetWin64() const
Definition: X86Subtarget.h:407
llvm::Value
LLVM Value Representation.
Definition: Value.h:69
SDValue X86TargetLowering::LowerVECTOR_SHUFFLE ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 9257 of file X86ISelLowering.cpp.

9257  {
9258  ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9259  SDValue V1 = Op.getOperand(0);
9260  SDValue V2 = Op.getOperand(1);
9261  MVT VT = Op.getSimpleValueType();
9262  SDLoc dl(Op);
9263  unsigned NumElems = VT.getVectorNumElements();
9264  bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9265  bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9266  bool V1IsSplat = false;
9267  bool V2IsSplat = false;
9268  bool HasSSE2 = Subtarget->hasSSE2();
9269  bool HasFp256 = Subtarget->hasFp256();
9270  bool HasInt256 = Subtarget->hasInt256();
9271  MachineFunction &MF = DAG.getMachineFunction();
9272  bool OptForSize = MF.getFunction()->getAttributes().
9273  hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
9274 
9275  // Check if we should use the experimental vector shuffle lowering. If so,
9276  // delegate completely to that code path.
9277  if (ExperimentalVectorShuffleLowering)
9278  return lowerVectorShuffle(Op, Subtarget, DAG);
9279 
9280  assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9281 
9282  if (V1IsUndef && V2IsUndef)
9283  return DAG.getUNDEF(VT);
9284 
9285  // When we create a shuffle node we put the UNDEF node to second operand,
9286  // but in some cases the first operand may be transformed to UNDEF.
9287  // In this case we should just commute the node.
9288  if (V1IsUndef)
9289  return DAG.getCommutedVectorShuffle(*SVOp);
9290 
9291  // Vector shuffle lowering takes 3 steps:
9292  //
9293  // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
9294  // narrowing and commutation of operands should be handled.
9295  // 2) Matching of shuffles with known shuffle masks to x86 target specific
9296  // shuffle nodes.
9297  // 3) Rewriting of unmatched masks into new generic shuffle operations,
9298  // so the shuffle can be broken into other shuffles and the legalizer can
9299  // try the lowering again.
9300  //
9301  // The general idea is that no vector_shuffle operation should be left to
9302  // be matched during isel, all of them must be converted to a target specific
9303  // node here.
9304 
9305  // Normalize the input vectors. Here splats, zeroed vectors, profitable
9306  // narrowing and commutation of operands should be handled. The actual code
9307  // doesn't include all of those, work in progress...
9308  SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
9309  if (NewOp.getNode())
9310  return NewOp;
9311 
9312  SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
9313 
9314  // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
9315  // unpckh_undef). Only use pshufd if speed is more important than size.
9316  if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9317  return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9318  if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9319  return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9320 
9321  if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
9322  V2IsUndef && MayFoldVectorLoad(V1))
9323  return getMOVDDup(Op, dl, V1, DAG);
9324 
9325  if (isMOVHLPS_v_undef_Mask(M, VT))
9326  return getMOVHighToLow(Op, dl, DAG);
9327 
9328  // Use to match splats
9329  if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
9330  (VT == MVT::v2f64 || VT == MVT::v2i64))
9331  return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9332 
9333  if (isPSHUFDMask(M, VT)) {
9334  // The actual implementation will match the mask in the if above and then
9335  // during isel it can match several different instructions, not only pshufd
9336  // as its name says, sad but true, emulate the behavior for now...
9337  if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
9338  return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
9339 
9340  unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
9341 
9342  if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
9343  return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
9344 
9345  if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
9346  return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
9347  DAG);
9348 
9349  return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
9350  TargetMask, DAG);
9351  }
9352 
9353  if (isPALIGNRMask(M, VT, Subtarget))
9354  return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
9355  getShufflePALIGNRImmediate(SVOp),
9356  DAG);
9357 
9358  // Check if this can be converted into a logical shift.
9359  bool isLeft = false;
9360  unsigned ShAmt = 0;
9361  SDValue ShVal;
9362  bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
9363  if (isShift && ShVal.hasOneUse()) {
9364  // If the shifted value has multiple uses, it may be cheaper to use
9365  // v_set0 + movlhps or movhlps, etc.
9366  MVT EltVT = VT.getVectorElementType();
9367  ShAmt *= EltVT.getSizeInBits();
9368  return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9369  }
9370 
9371  if (isMOVLMask(M, VT)) {
9372  if (ISD::isBuildVectorAllZeros(V1.getNode()))
9373  return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
9374  if (!isMOVLPMask(M, VT)) {
9375  if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
9376  return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9377 
9378  if (VT == MVT::v4i32 || VT == MVT::v4f32)
9379  return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9380  }
9381  }
9382 
9383  // FIXME: fold these into legal mask.
9384  if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
9385  return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
9386 
9387  if (isMOVHLPSMask(M, VT))
9388  return getMOVHighToLow(Op, dl, DAG);
9389 
9390  if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
9391  return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
9392 
9393  if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
9394  return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
9395 
9396  if (isMOVLPMask(M, VT))
9397  return getMOVLP(Op, dl, DAG, HasSSE2);
9398 
9399  if (ShouldXformToMOVHLPS(M, VT) ||
9400  ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
9401  return DAG.getCommutedVectorShuffle(*SVOp);
9402 
9403  if (isShift) {
9404  // No better options. Use a vshldq / vsrldq.
9405  MVT EltVT = VT.getVectorElementType();
9406  ShAmt *= EltVT.getSizeInBits();
9407  return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9408  }
9409 
9410  bool Commuted = false;
9411  // FIXME: This should also accept a bitcast of a splat? Be careful, not
9412  // 1,1,1,1 -> v8i16 though.
9413  BitVector UndefElements;
9414  if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
9415  if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9416  V1IsSplat = true;
9417  if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
9418  if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9419  V2IsSplat = true;
9420 
9421  // Canonicalize the splat or undef, if present, to be on the RHS.
9422  if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
9423  CommuteVectorShuffleMask(M, NumElems);
9424  std::swap(V1, V2);
9425  std::swap(V1IsSplat, V2IsSplat);
9426  Commuted = true;
9427  }
9428 
9429  if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
9430  // Shuffling low element of v1 into undef, just return v1.
9431  if (V2IsUndef)
9432  return V1;
9433  // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
9434  // the instruction selector will not match, so get a canonical MOVL with
9435  // swapped operands to undo the commute.
9436  return getMOVL(DAG, dl, VT, V2, V1);
9437  }
9438 
9439  if (isUNPCKLMask(M, VT, HasInt256))
9440  return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9441 
9442  if (isUNPCKHMask(M, VT, HasInt256))
9443  return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9444 
9445  if (V2IsSplat) {
9446  // Normalize mask so all entries that point to V2 points to its first
9447  // element then try to match unpck{h|l} again. If match, return a
9448  // new vector_shuffle with the corrected mask.p
9449  SmallVector<int, 8> NewMask(M.begin(), M.end());
9450  NormalizeMask(NewMask, NumElems);
9451  if (isUNPCKLMask(NewMask, VT, HasInt256, true))
9452  return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9453  if (isUNPCKHMask(NewMask, VT, HasInt256, true))
9454  return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9455  }
9456 
9457  if (Commuted) {
9458  // Commute is back and try unpck* again.
9459  // FIXME: this seems wrong.
9460  CommuteVectorShuffleMask(M, NumElems);
9461  std::swap(V1, V2);
9462  std::swap(V1IsSplat, V2IsSplat);
9463 
9464  if (isUNPCKLMask(M, VT, HasInt256))
9465  return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9466 
9467  if (isUNPCKHMask(M, VT, HasInt256))
9468  return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9469  }
9470 
9471  // Normalize the node to match x86 shuffle ops if needed
9472  if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
9473  return DAG.getCommutedVectorShuffle(*SVOp);
9474 
9475  // The checks below are all present in isShuffleMaskLegal, but they are
9476  // inlined here right now to enable us to directly emit target specific
9477  // nodes, and remove one by one until they don't return Op anymore.
9478 
9479  if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
9480  SVOp->getSplatIndex() == 0 && V2IsUndef) {
9481  if (VT == MVT::v2f64 || VT == MVT::v2i64)
9482  return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9483  }
9484 
9485  if (isPSHUFHWMask(M, VT, HasInt256))
9486  return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
9487  getShufflePSHUFHWImmediate(SVOp),
9488  DAG);
9489 
9490  if (isPSHUFLWMask(M, VT, HasInt256))
9491  return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
9492  getShufflePSHUFLWImmediate(SVOp),
9493  DAG);
9494 
9495  unsigned MaskValue;
9496  if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
9497  &MaskValue))
9498  return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
9499 
9500  if (isSHUFPMask(M, VT))
9501  return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
9502  getShuffleSHUFImmediate(SVOp), DAG);
9503 
9504  if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9505  return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9506  if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9507  return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9508 
9509  //===--------------------------------------------------------------------===//
9510  // Generate target specific nodes for 128 or 256-bit shuffles only
9511  // supported in the AVX instruction set.
9512  //
9513 
9514  // Handle VMOVDDUPY permutations
9515  if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
9516  return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
9517 
9518  // Handle VPERMILPS/D* permutations
9519  if (isVPERMILPMask(M, VT)) {
9520  if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
9521  return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
9522  getShuffleSHUFImmediate(SVOp), DAG);
9523  return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
9524  getShuffleSHUFImmediate(SVOp), DAG);
9525  }
9526 
9527  unsigned Idx;
9528  if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
9529  return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
9530  Idx*(NumElems/2), DAG, dl);
9531 
9532  // Handle VPERM2F128/VPERM2I128 permutations
9533  if (isVPERM2X128Mask(M, VT, HasFp256))
9534  return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
9535  V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
9536 
9537  if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
9538  return getINSERTPS(SVOp, dl, DAG);
9539 
9540  unsigned Imm8;
9541  if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
9542  return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
9543 
9544  if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
9545  VT.is512BitVector()) {
9546  MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
9547  MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
9548  SmallVector<SDValue, 16> permclMask;
9549  for (unsigned i = 0; i != NumElems; ++i) {
9550  permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
9551  }
9552 
9553  SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
9554  if (V2IsUndef)
9555  // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
9556  return DAG.getNode(X86ISD::VPERMV, dl, VT,
9557  DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
9558  return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
9559  DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
9560  }
9561 
9562  //===--------------------------------------------------------------------===//
9563  // Since no target specific shuffle was selected for this generic one,
9564  // lower it into other known shuffles. FIXME: this isn't true yet, but
9565  // this is the plan.
9566  //
9567 
9568  // Handle v8i16 specifically since SSE can do byte extraction and insertion.
9569  if (VT == MVT::v8i16) {
9570  SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
9571  if (NewOp.getNode())
9572  return NewOp;
9573  }
9574 
9575  if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
9576  SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
9577  if (NewOp.getNode())
9578  return NewOp;
9579  }
9580 
9581  if (VT == MVT::v16i8) {
9582  SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
9583  if (NewOp.getNode())
9584  return NewOp;
9585  }
9586 
9587  if (VT == MVT::v32i8) {
9588  SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
9589  if (NewOp.getNode())
9590  return NewOp;
9591  }
9592 
9593  // Handle all 128-bit wide vectors with 4 elements, and match them with
9594  // several different shuffle types.
9595  if (NumElems == 4 && VT.is128BitVector())
9596  return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
9597 
9598  // Handle general 256-bit shuffles
9599  if (VT.is256BitVector())
9600  return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
9601 
9602  return SDValue();
9603 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
isPSHUFDMask
static bool isPSHUFDMask(ArrayRef< int > Mask, MVT VT)
Definition: X86ISelLowering.cpp:3708
getShuffleVPERM2X128Immediate
static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp)
Definition: X86ISelLowering.cpp:4334
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:486
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86Subtarget::hasSSE3
bool hasSSE3() const
Definition: X86Subtarget.h:313
LowerVECTOR_SHUFFLE_128v4
static SDValue LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:8753
getMOVLowToHigh
static SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2)
Definition: X86ISelLowering.cpp:8918
isPSHUFHWMask
static bool isPSHUFHWMask(ArrayRef< int > Mask, MVT VT, bool HasInt256)
Definition: X86ISelLowering.cpp:3718
CommuteVectorShuffleMask
static void CommuteVectorShuffleMask(SmallVectorImpl< int > &Mask, unsigned NumElems)
Definition: X86ISelLowering.cpp:3849
llvm::BitVector::none
bool none() const
none - Returns true if none of the bits are set.
Definition: BitVector.h:152
llvm::MVT::getVectorVT
static MVT getVectorVT(MVT VT, unsigned NumElements)
Definition: MachineValueType.h:505
llvm::SDValue::hasOneUse
bool hasOneUse() const
Definition: SelectionDAGNodes.h:910
isMOVHLPSMask
static bool isMOVHLPSMask(ArrayRef< int > Mask, MVT VT)
Definition: X86ISelLowering.cpp:3925
LowerVECTOR_SHUFFLEtoBlend
static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp, unsigned MaskValue, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:8054
getVShift
static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits, SelectionDAG &DAG, const TargetLowering &TLI, SDLoc dl)
Definition: X86ISelLowering.cpp:5547
isINSERT64x4Mask
static bool isINSERT64x4Mask(ArrayRef< int > Mask, MVT VT, unsigned int *Imm)
Definition: X86ISelLowering.cpp:4255
getMOVL
static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1, SDValue V2)
Definition: X86ISelLowering.cpp:4966
ExperimentalVectorShuffleLowering
static cl::opt< bool > ExperimentalVectorShuffleLowering("x86-experimental-vector-shuffle-lowering", cl::init(false), cl::desc("Enable an experimental vector shuffle lowering code path."), cl::Hidden)
isMOVDDUPYMask
static bool isMOVDDUPYMask(ArrayRef< int > Mask, MVT VT, bool HasFp256)
Definition: X86ISelLowering.cpp:4505
LowerVECTOR_SHUFFLEv16i16
static SDValue LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG)
v16i16 shuffles
Definition: X86ISelLowering.cpp:8382
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm::X86Subtarget::hasSSE41
bool hasSSE41() const
Definition: X86Subtarget.h:315
llvm::MachineFunction::getFunction
const Function * getFunction() const
Definition: MachineFunction.h:151
ShouldXformToMOVHLPS
static bool ShouldXformToMOVHLPS(ArrayRef< int > Mask, MVT VT)
Definition: X86ISelLowering.cpp:4774
isMOVHLPS_v_undef_Mask
static bool isMOVHLPS_v_undef_Mask(ArrayRef< int > Mask, MVT VT)
Definition: X86ISelLowering.cpp:3944
MayFoldVectorLoad
static bool MayFoldVectorLoad(SDValue V)
Definition: X86ISelLowering.cpp:8892
Extract256BitVector
static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl)
Generate a DAG to grab 256-bits from a 512-bit vector.
Definition: X86ISelLowering.cpp:126
getMOVDDup
static SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:8907
getShuffleSHUFImmediate
static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N)
Definition: X86ISelLowering.cpp:4595
getTargetShuffleNode
static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT, SDValue V1, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:3405
isPermImmMask
static bool isPermImmMask(ArrayRef< int > Mask, MVT VT, unsigned &Imm8)
Definition: X86ISelLowering.cpp:4357
isVPERMILPMask
static bool isVPERMILPMask(ArrayRef< int > Mask, MVT VT)
Definition: X86ISelLowering.cpp:4401
isUNPCKL_v_undef_Mask
static bool isUNPCKL_v_undef_Mask(ArrayRef< int > Mask, MVT VT, bool HasInt256)
Definition: X86ISelLowering.cpp:4179
llvm::ISD::isBuildVectorAllZeros
bool isBuildVectorAllZeros(const SDNode *N)
Definition: SelectionDAG.cpp:144
isBlendMask
static bool isBlendMask(ArrayRef< int > MaskVals, MVT VT, bool hasSSE41, bool hasInt256, unsigned *MaskOut=nullptr)
Definition: X86ISelLowering.cpp:8009
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:276
getShufflePSHUFHWImmediate
static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N)
Definition: X86ISelLowering.cpp:4625
getINSERTPS
static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:9028
isShift
static bool isShift(MachineInstr *MI, int Opcode, int64_t Imm)
Definition: SystemZInstrInfo.cpp:426
NormalizeMask
static void NormalizeMask(SmallVectorImpl< int > &Mask, unsigned NumElems)
Definition: X86ISelLowering.cpp:4956
llvm::SelectionDAG::getUNDEF
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
isMOVLMask
static bool isMOVLMask(ArrayRef< int > Mask, EVT VT)
Definition: X86ISelLowering.cpp:4279
getShufflePSHUFLWImmediate
static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N)
Definition: X86ISelLowering.cpp:4649
llvm::ISD::UNDEF
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
llvm::X86Subtarget::hasSSE2
bool hasSSE2() const
Definition: X86Subtarget.h:312
Insert256BitVector
static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, SDLoc dl)
Definition: X86ISelLowering.cpp:169
isSHUFPMask
static bool isSHUFPMask(ArrayRef< int > Mask, MVT VT, bool Commuted=false)
Definition: X86ISelLowering.cpp:3866
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
assert
assert(Globals.size() > 1)
llvm::SelectionDAG::getCommutedVectorShuffle
SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV)
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swa...
Definition: SelectionDAG.cpp:1601
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:312
getMOVLP
static SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2)
Definition: X86ISelLowering.cpp:8953
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
getVZextMovL
static SDValue getVZextMovL(MVT VT, MVT OpVT, SDValue SrcOp, SelectionDAG &DAG, const X86Subtarget *Subtarget, SDLoc dl)
Definition: X86ISelLowering.cpp:8604
isINSERTPSMask
static bool isINSERTPSMask(ArrayRef< int > Mask, MVT VT)
Definition: X86ISelLowering.cpp:4006
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::X86Subtarget::hasFp256
bool hasFp256() const
Definition: X86Subtarget.h:320
isMOVSLDUPMask
static bool isMOVSLDUPMask(ArrayRef< int > Mask, MVT VT, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:4481
getMOVHighToLow
static SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:8937
NormalizeVectorShuffle
static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:9201
LowerVECTOR_SHUFFLEv32i8
static SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:8528
llvm::ShuffleVectorSDNode::getMask
ArrayRef< int > getMask() const
Definition: SelectionDAGNodes.h:1312
LowerVECTOR_SHUFFLEv16i8
static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:8399
lowerVectorShuffle
static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Top-level lowering for x86 vector shuffles.
Definition: X86ISelLowering.cpp:7912
ShouldXformToMOVLP
static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, ArrayRef< int > Mask, MVT VT)
Definition: X86ISelLowering.cpp:4830
isUNPCKLMask
static bool isUNPCKLMask(ArrayRef< int > Mask, MVT VT, bool HasInt256, bool V2IsSplat=false)
Definition: X86ISelLowering.cpp:4083
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:590
llvm::Function::getAttributes
AttributeSet getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:170
getShufflePALIGNRImmediate
static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp)
Definition: X86ISelLowering.cpp:4673
llvm::X86Subtarget::hasInt256
bool hasInt256() const
Definition: X86Subtarget.h:321
isUNPCKH_v_undef_Mask
static bool isUNPCKH_v_undef_Mask(ArrayRef< int > Mask, MVT VT, bool HasInt256)
Definition: X86ISelLowering.cpp:4222
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
isVPERM2X128Mask
static bool isVPERM2X128Mask(ArrayRef< int > Mask, MVT VT, bool HasFp256)
Definition: X86ISelLowering.cpp:4303
isMOVDDUPMask
static bool isMOVDDUPMask(ArrayRef< int > Mask, MVT VT)
Definition: X86ISelLowering.cpp:4525
isMOVLHPSMask
static bool isMOVLHPSMask(ArrayRef< int > Mask, MVT VT)
Definition: X86ISelLowering.cpp:3983
isVectorShift
static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt)
Definition: X86ISelLowering.cpp:5378
LowerVECTOR_SHUFFLEv8i16
static SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:8142
LowerVECTOR_SHUFFLE_256
static SDValue LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:8640
isMOVLPMask
static bool isMOVLPMask(ArrayRef< int > Mask, MVT VT)
Definition: X86ISelLowering.cpp:3961
isUNPCKHMask
static bool isUNPCKHMask(ArrayRef< int > Mask, MVT VT, bool HasInt256, bool V2IsSplat=false)
Definition: X86ISelLowering.cpp:4131
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:264
isPALIGNRMask
static bool isPALIGNRMask(ArrayRef< int > Mask, MVT VT, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:3776
isPSHUFLWMask
static bool isPSHUFLWMask(ArrayRef< int > Mask, MVT VT, bool HasInt256)
Definition: X86ISelLowering.cpp:3747
llvm::ShuffleVectorSDNode::isSplatMask
static bool isSplatMask(const int *Mask, EVT VT)
Definition: SelectionDAG.cpp:6780
isCommutedMOVLMask
static bool isCommutedMOVLMask(ArrayRef< int > Mask, MVT VT, bool V2IsSplat=false, bool V2IsUndef=false)
Definition: X86ISelLowering.cpp:4433
isMOVSHDUPMask
static bool isMOVSHDUPMask(ArrayRef< int > Mask, MVT VT, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:4457
SDValue X86TargetLowering::LowerVSELECT ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 9685 of file X86ISelLowering.cpp.

9685  {
9686  SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
9687  if (BlendOp.getNode())
9688  return BlendOp;
9689 
9690  // Some types for vselect were previously set to Expand, not Legal or
9691  // Custom. Return an empty SDValue so we fall-through to Expand, after
9692  // the Custom lowering phase.
9693  MVT VT = Op.getSimpleValueType();
9694  switch (VT.SimpleTy) {
9695  default:
9696  break;
9697  case MVT::v8i16:
9698  case MVT::v16i16:
9699  return SDValue();
9700  }
9701 
9702  // We couldn't create a "Blend with immediate" node.
9703  // This node should still be legal, but we'll have to emit a blendv*
9704  // instruction.
9705  return Op;
9706 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::MVT::SimpleTy
SimpleValueType SimpleTy
Definition: MachineValueType.h:156
LowerVSELECTtoBlend
static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:9643
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
SDValue X86TargetLowering::LowerWin64_i128OP ( SDValue  Op,
SelectionDAG &  DAG 
) const
private

Definition at line 15106 of file X86ISelLowering.cpp.

15106  {
15107  assert(Subtarget->isTargetWin64() && "Unexpected target");
15108  EVT VT = Op.getValueType();
15109  assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15110  "Unexpected return type for lowering");
15111 
15112  RTLIB::Libcall LC;
15113  bool isSigned;
15114  switch (Op->getOpcode()) {
15115  default: llvm_unreachable("Unexpected request for libcall!");
15116  case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15117  case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15118  case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15119  case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15120  case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15121  case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15122  }
15123 
15124  SDLoc dl(Op);
15125  SDValue InChain = DAG.getEntryNode();
15126 
15127  TargetLowering::ArgListTy Args;
15128  TargetLowering::ArgListEntry Entry;
15129  for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15130  EVT ArgVT = Op->getOperand(i).getValueType();
15131  assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15132  "Unexpected argument type for lowering");
15133  SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15134  Entry.Node = StackPtr;
15135  InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15136  false, false, 16);
15137  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15138  Entry.Ty = PointerType::get(ArgTy,0);
15139  Entry.isSExt = false;
15140  Entry.isZExt = false;
15141  Args.push_back(Entry);
15142  }
15143 
15144  SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15145  getPointerTy());
15146 
15147  TargetLowering::CallLoweringInfo CLI(DAG);
15148  CLI.setDebugLoc(dl).setChain(InChain)
15149  .setCallee(getLibcallCallingConv(LC),
15150  static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15151  Callee, std::move(Args), 0)
15152  .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15153 
15154  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15155  return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15156 }
llvm::TargetLoweringBase::getLibcallCallingConv
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:1447
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::PointerType::get
static PointerType * get(Type *ElementType, unsigned AddressSpace)
Definition: Type.cpp:727
llvm::SDNode::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:401
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
llvm::SDNode::getNumOperands
unsigned getNumOperands() const
Definition: SelectionDAGNodes.h:586
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:592
llvm::SelectionDAG::getExternalSymbol
SDValue getExternalSymbol(const char *Sym, EVT VT)
Definition: SelectionDAG.cpp:1433
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::EVT::isInteger
bool isInteger() const
isInteger - Return true if this is an integer, or a vector integer type.
Definition: ValueTypes.h:111
llvm::TargetLowering::LowerCallTo
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
Definition: SelectionDAGBuilder.cpp:7072
assert
assert(Globals.size() > 1)
llvm::TargetLowering::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:2126
llvm::SelectionDAG::getStore
SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, unsigned Alignment, const MDNode *TBAAInfo=nullptr)
Definition: SelectionDAG.cpp:4815
llvm::SelectionDAG::CreateStackTemporary
SDValue CreateStackTemporary(EVT VT, unsigned minAlign=1)
Definition: SelectionDAG.cpp:1782
Args
const char * Args[]
Definition: OptionParsingTest.cpp:55
llvm::TargetLoweringBase::getLibcallName
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
Definition: TargetLowering.h:1425
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::X86Subtarget::isTargetWin64
bool isTargetWin64() const
Definition: X86Subtarget.h:407
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
const char * X86TargetLowering::LowerXConstraint ( EVT  ConstraintVT) const
overridevirtual

LowerXConstraint - try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand.

Reimplemented from llvm::TargetLowering.

Definition at line 22497 of file X86ISelLowering.cpp.

22497  {
22498  // FP X constraints get lowered to SSE1/2 registers if available, otherwise
22499  // 'f' like normal targets.
22500  if (ConstraintVT.isFloatingPoint()) {
22501  if (Subtarget->hasSSE2())
22502  return "Y";
22503  if (Subtarget->hasSSE1())
22504  return "x";
22505  }
22506 
22507  return TargetLowering::LowerXConstraint(ConstraintVT);
22508 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::TargetLowering::LowerXConstraint
virtual const char * LowerXConstraint(EVT ConstraintVT) const
Definition: TargetLowering.cpp:2091
llvm::X86Subtarget::hasSSE2
bool hasSSE2() const
Definition: X86Subtarget.h:312
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:311
llvm::EVT::isFloatingPoint
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
std::pair< SDValue, SDValue > TargetLowering::makeLibCall ( SelectionDAG &  DAG,
RTLIB::Libcall  LC,
EVT  RetVT,
const SDValue *  Ops,
unsigned  NumOps,
bool  isSigned,
SDLoc  dl,
bool  doesNotReturn = false,
bool  isReturnValueUsed = true 
) const
inherited

Returns a pair of (return value, chain).

Generate a libcall taking the given operands as arguments and returning a result of type RetVT.

Definition at line 86 of file TargetLowering.cpp.

91  {
92  TargetLowering::ArgListTy Args;
93  Args.reserve(NumOps);
94 
95  TargetLowering::ArgListEntry Entry;
96  for (unsigned i = 0; i != NumOps; ++i) {
97  Entry.Node = Ops[i];
98  Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99  Entry.isSExt = isSigned;
100  Entry.isZExt = !isSigned;
101  Args.push_back(Entry);
102  }
103  SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
104 
105  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
106  TargetLowering::CallLoweringInfo CLI(DAG);
107  CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
108  .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
109  .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
110  .setSExtResult(isSigned).setZExtResult(!isSigned);
111  return LowerCallTo(CLI);
112 }
llvm::TargetLoweringBase::getLibcallCallingConv
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:1447
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
Definition: ValueTypes.cpp:180
llvm::SelectionDAG::getExternalSymbol
SDValue getExternalSymbol(const char *Sym, EVT VT)
Definition: SelectionDAG.cpp:1433
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::TargetLowering::LowerCallTo
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
Definition: SelectionDAGBuilder.cpp:7072
llvm::TargetLowering::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:2126
Args
const char * Args[]
Definition: OptionParsingTest.cpp:55
llvm::TargetLoweringBase::getLibcallName
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
Definition: TargetLowering.h:1425
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getEntryNode
SDValue getEntryNode() const
Definition: SelectionDAG.h:327
bool X86TargetLowering::mayBeEmittedAsTailCall ( CallInst *  CI) const
overrideprivatevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 2183 of file X86ISelLowering.cpp.

2183  {
2184  if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2185  return false;
2186 
2187  CallSite CS(CI);
2188  CallingConv::ID CalleeCC = CS.getCallingConv();
2189  if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2190  return false;
2191 
2192  return true;
2193 }
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:149
llvm::CallingConv::ID
ID
LLVM Calling Convention Representation.
Definition: CallingConv.h:26
IsTailCallConvention
static bool IsTailCallConvention(CallingConv::ID CC)
Definition: X86ISelLowering.cpp:2172
llvm::CallInst::isTailCall
bool isTailCall() const
Definition: Instructions.h:1297
IsCCallConvention
static bool IsCCallConvention(CallingConv::ID CC)
Return true if the calling convention is a C calling convention.
Definition: X86ISelLowering.cpp:2178
TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints ( ImmutableCallSite  CS) const
virtualinherited

Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.

ParseConstraints - Split up the constraint string from the inline assembly value into the specific constraints and their prefixes, and also tie in the associated operand values. If this returns an empty vector, and if the constraint string itself isn't empty, there was an error parsing.

ConstraintOperands - Information about all of the constraints.

Definition at line 2233 of file TargetLowering.cpp.

2234  {
2235  /// ConstraintOperands - Information about all of the constraints.
2236  AsmOperandInfoVector ConstraintOperands;
2237  const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2238  unsigned maCount = 0; // Largest number of multiple alternative constraints.
2239 
2240  // Do a prepass over the constraints, canonicalizing them, and building up the
2241  // ConstraintOperands list.
2242  InlineAsm::ConstraintInfoVector
2243  ConstraintInfos = IA->ParseConstraints();
2244 
2245  unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2246  unsigned ResNo = 0; // ResNo - The result number of the next output.
2247 
2248  for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2249  ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2250  AsmOperandInfo &OpInfo = ConstraintOperands.back();
2251 
2252  // Update multiple alternative constraint count.
2253  if (OpInfo.multipleAlternatives.size() > maCount)
2254  maCount = OpInfo.multipleAlternatives.size();
2255 
2256  OpInfo.ConstraintVT = MVT::Other;
2257 
2258  // Compute the value type for each operand.
2259  switch (OpInfo.Type) {
2260  case InlineAsm::isOutput:
2261  // Indirect outputs just consume an argument.
2262  if (OpInfo.isIndirect) {
2263  OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2264  break;
2265  }
2266 
2267  // The return value of the call is this value. As such, there is no
2268  // corresponding argument.
2269  assert(!CS.getType()->isVoidTy() &&
2270  "Bad inline asm!");
2271  if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2272  OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2273  } else {
2274  assert(ResNo == 0 && "Asm only has one result!");
2275  OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2276  }
2277  ++ResNo;
2278  break;
2279  case InlineAsm::isInput:
2280  OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2281  break;
2282  case InlineAsm::isClobber:
2283  // Nothing to do.
2284  break;
2285  }
2286 
2287  if (OpInfo.CallOperandVal) {
2288  llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2289  if (OpInfo.isIndirect) {
2290  llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2291  if (!PtrTy)
2292  report_fatal_error("Indirect operand for inline asm not a pointer!");
2293  OpTy = PtrTy->getElementType();
2294  }
2295 
2296  // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2297  if (StructType *STy = dyn_cast<StructType>(OpTy))
2298  if (STy->getNumElements() == 1)
2299  OpTy = STy->getElementType(0);
2300 
2301  // If OpTy is not a single value, it may be a struct/union that we
2302  // can tile with integers.
2303  if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2304  unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2305  switch (BitSize) {
2306  default: break;
2307  case 1:
2308  case 8:
2309  case 16:
2310  case 32:
2311  case 64:
2312  case 128:
2313  OpInfo.ConstraintVT =
2314  MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2315  break;
2316  }
2317  } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2318  unsigned PtrSize
2319  = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
2320  OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2321  } else {
2322  OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2323  }
2324  }
2325  }
2326 
2327  // If we have multiple alternative constraints, select the best alternative.
2328  if (ConstraintInfos.size()) {
2329  if (maCount) {
2330  unsigned bestMAIndex = 0;
2331  int bestWeight = -1;
2332  // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2333  int weight = -1;
2334  unsigned maIndex;
2335  // Compute the sums of the weights for each alternative, keeping track
2336  // of the best (highest weight) one so far.
2337  for (maIndex = 0; maIndex < maCount; ++maIndex) {
2338  int weightSum = 0;
2339  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2340  cIndex != eIndex; ++cIndex) {
2341  AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2342  if (OpInfo.Type == InlineAsm::isClobber)
2343  continue;
2344 
2345  // If this is an output operand with a matching input operand,
2346  // look up the matching input. If their types mismatch, e.g. one
2347  // is an integer, the other is floating point, or their sizes are
2348  // different, flag it as an maCantMatch.
2349  if (OpInfo.hasMatchingInput()) {
2350  AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2351  if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2352  if ((OpInfo.ConstraintVT.isInteger() !=
2353  Input.ConstraintVT.isInteger()) ||
2354  (OpInfo.ConstraintVT.getSizeInBits() !=
2355  Input.ConstraintVT.getSizeInBits())) {
2356  weightSum = -1; // Can't match.
2357  break;
2358  }
2359  }
2360  }
2361  weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2362  if (weight == -1) {
2363  weightSum = -1;
2364  break;
2365  }
2366  weightSum += weight;
2367  }
2368  // Update best.
2369  if (weightSum > bestWeight) {
2370  bestWeight = weightSum;
2371  bestMAIndex = maIndex;
2372  }
2373  }
2374 
2375  // Now select chosen alternative in each constraint.
2376  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2377  cIndex != eIndex; ++cIndex) {
2378  AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2379  if (cInfo.Type == InlineAsm::isClobber)
2380  continue;
2381  cInfo.selectAlternative(bestMAIndex);
2382  }
2383  }
2384  }
2385 
2386  // Check and hook up tied operands, choose constraint code to use.
2387  for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2388  cIndex != eIndex; ++cIndex) {
2389  AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2390 
2391  // If this is an output operand with a matching input operand, look up the
2392  // matching input. If their types mismatch, e.g. one is an integer, the
2393  // other is floating point, or their sizes are different, flag it as an
2394  // error.
2395  if (OpInfo.hasMatchingInput()) {
2396  AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2397 
2398  if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2399  std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2400  getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
2401  OpInfo.ConstraintVT);
2402  std::pair<unsigned, const TargetRegisterClass*> InputRC =
2403  getRegForInlineAsmConstraint(Input.ConstraintCode,
2404  Input.ConstraintVT);
2405  if ((OpInfo.ConstraintVT.isInteger() !=
2406  Input.ConstraintVT.isInteger()) ||
2407  (MatchRC.second != InputRC.second)) {
2408  report_fatal_error("Unsupported asm: input constraint"
2409  " with a matching output constraint of"
2410  " incompatible type!");
2411  }
2412  }
2413 
2414  }
2415  }
2416 
2417  return ConstraintOperands;
2418 }
llvm::MVT::getIntegerVT
static MVT getIntegerVT(unsigned BitWidth)
Definition: MachineValueType.h:486
llvm::CallSiteBase::getType
Type * getType() const
Definition: CallSite.h:157
llvm::CallSiteBase::getArgument
ValTy * getArgument(unsigned ArgNo) const
Definition: CallSite.h:113
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(const char *reason, bool gen_crash_diag=true)
Definition: ErrorHandling.cpp:60
llvm::Type::isSingleValueType
bool isSingleValueType() const
Definition: Type.h:250
llvm::TargetLoweringBase::getSimpleValueType
MVT getSimpleValueType(Type *Ty, bool AllowUnknown=false) const
Return the MVT corresponding to this LLVM type. See getValueType.
Definition: TargetLowering.h:659
llvm::Type::getContext
LLVMContext & getContext() const
getContext - Return the LLVMContext in which this type was uniqued.
Definition: Type.h:125
llvm::TargetLowering::getRegForInlineAsmConstraint
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
Definition: TargetLowering.cpp:2167
llvm::CallSiteBase::getCalledValue
ValTy * getCalledValue() const
Definition: CallSite.h:85
llvm::SequentialType::getElementType
Type * getElementType() const
Definition: DerivedTypes.h:319
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::getDataLayout
const DataLayout * getDataLayout() const
Definition: TargetLowering.h:150
llvm::MVT::getVT
static MVT getVT(Type *Ty, bool HandleUnknown=false)
Definition: ValueTypes.cpp:247
llvm::TargetLowering::AsmOperandInfoVector
std::vector< AsmOperandInfo > AsmOperandInfoVector
Definition: TargetLowering.h:2484
llvm::IntegerType::get
static IntegerType * get(LLVMContext &C, unsigned NumBits)
Get or create an IntegerType instance.
Definition: Type.cpp:299
Input
static cl::opt< std::string > Input(cl::Positional, cl::desc("<input>"), cl::init("-"))
llvm::Type::isSized
bool isSized(SmallPtrSet< const Type *, 4 > *Visited=nullptr) const
Definition: Type.h:268
llvm::dyn_cast
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
llvm::DataLayout::getPointerSizeInBits
unsigned getPointerSizeInBits(unsigned AS=0) const
Definition: DataLayout.h:313
llvm::Value
LLVM Value Representation.
Definition: Value.h:69
llvm::TargetLowering::getMultipleConstraintMatchWeight
virtual ConstraintWeight getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const
Definition: TargetLowering.cpp:2442
llvm::DataLayout::getTypeSizeInBits
uint64_t getTypeSizeInBits(Type *Ty) const
Definition: DataLayout.h:522
llvm::InlineAsm::ConstraintInfoVector
std::vector< ConstraintInfo > ConstraintInfoVector
Definition: InlineAsm.h:118
llvm::InlineAsm::ParseConstraints
static ConstraintInfoVector ParseConstraints(StringRef ConstraintString)
Definition: InlineAsm.cpp:203
llvm::Type::isVoidTy
bool isVoidTy() const
isVoidTy - Return true if this is 'void'.
Definition: Type.h:137
SDValue X86TargetLowering::PerformDAGCombine ( SDNode *  N,
DAGCombinerInfo &  DCI 
) const
overridevirtual

Reimplemented from llvm::TargetLowering.

Definition at line 22061 of file X86ISelLowering.cpp.

22062  {
22063  SelectionDAG &DAG = DCI.DAG;
22064  switch (N->getOpcode()) {
22065  default: break;
22066  case ISD::EXTRACT_VECTOR_ELT:
22067  return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
22068  case ISD::VSELECT:
22069  case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
22070  case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
22071  case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
22072  case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
22073  case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
22074  case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
22075  case ISD::SHL:
22076  case ISD::SRA:
22077  case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
22078  case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
22079  case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
22080  case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
22081  case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
22082  case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
22083  case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
22084  case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
22085  case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
22086  case X86ISD::FXOR:
22087  case X86ISD::FOR: return PerformFORCombine(N, DAG);
22088  case X86ISD::FMIN:
22089  case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
22090  case X86ISD::FAND: return PerformFANDCombine(N, DAG);
22091  case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
22092  case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
22093  case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
22094  case ISD::ANY_EXTEND:
22095  case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
22096  case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
22097  case ISD::SIGN_EXTEND_INREG:
22098  return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
22099  case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
22100  case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
22101  case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
22102  case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
22103  case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
22104  case X86ISD::SHUFP: // Handle all target specific shuffles
22105  case X86ISD::PALIGNR:
22106  case X86ISD::UNPCKH:
22107  case X86ISD::UNPCKL:
22108  case X86ISD::MOVHLPS:
22109  case X86ISD::MOVLHPS:
22110  case X86ISD::PSHUFD:
22111  case X86ISD::PSHUFHW:
22112  case X86ISD::PSHUFLW:
22113  case X86ISD::MOVSS:
22114  case X86ISD::MOVSD:
22115  case X86ISD::VPERMILP:
22116  case X86ISD::VPERM2X128:
22117  case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
22118  case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
22119  case ISD::INTRINSIC_WO_CHAIN:
22120  return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
22121  case X86ISD::INSERTPS:
22122  return PerformINSERTPSCombine(N, DAG, Subtarget);
22123  case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
22124  }
22125 
22126  return SDValue();
22127 }
PerformBUILD_VECTORCombine
static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:6346
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
PerformEXTRACT_VECTOR_ELTCombine
static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
Definition: X86ISelLowering.cpp:19036
llvm::SDNode::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:401
PerformINSERTPSCombine
static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:21738
PerformFORCombine
static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:21448
PerformSIGN_EXTEND_INREGCombine
static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:21541
PerformFANDNCombine
static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG)
PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes.
Definition: X86ISelLowering.cpp:21497
PerformSINT_TO_FPCombine
static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, const X86TargetLowering *XTLI)
Definition: X86ISelLowering.cpp:21893
PerformFANDCombine
static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG)
PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
Definition: X86ISelLowering.cpp:21484
llvm::X86ISD::BT
X86 bit-test instructions.
Definition: X86ISelLowering.h:96
PerformSELECTCombine
static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:19252
PerformSETCCCombine
static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:21782
PerformShuffleCombine
static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
PerformShuffleCombine - Performs several different shuffle combines.
Definition: X86ISelLowering.cpp:18792
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
PerformMulCombine
static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
Definition: X86ISelLowering.cpp:20226
PerformADCCombine
static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, X86TargetLowering::DAGCombinerInfo &DCI)
Definition: X86ISelLowering.cpp:21932
PerformSubCombine
static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:22012
llvm::ISD::FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:227
PerformShiftCombine
static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
PerformShiftCombine - Combine shifts.
Definition: X86ISelLowering.cpp:20359
PerformXorCombine
static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:20850
PerformZExtCombine
static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:21635
PerformTruncateCombine
static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:18932
PerformFMACombine
static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:21595
performVZEXTCombine
static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
performVZEXTCombine - Performs build vector combines
Definition: X86ISelLowering.cpp:22046
PerformISDSETCCCombine
static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:21683
PerformAddCombine
static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget)
PerformADDCombine - Do target-specific dag combines on integer adds.
Definition: X86ISelLowering.cpp:21997
PerformCMOVCombine
static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL].
Definition: X86ISelLowering.cpp:19950
PerformBrCondCombine
static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:21826
PerformSExtCombine
static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:21576
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
PerformFADDCombine
static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget)
PerformFADDCombine - Do target-specific dag combines on floating point adds.
Definition: X86ISelLowering.cpp:21417
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
PerformFMinFMaxCombine
static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:21463
PerformFSUBCombine
static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget)
PerformFSUBCombine - Do target-specific dag combines on floating point subs.
Definition: X86ISelLowering.cpp:21432
PerformINTRINSIC_WO_CHAINCombine
static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:20121
PerformLOADCombine
static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
Definition: X86ISelLowering.cpp:20866
PerformBTCombine
static SDValue PerformBTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI)
Definition: X86ISelLowering.cpp:21509
PerformSTORECombine
static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget)
PerformSTORECombine - Do target-specific dag combines on STORE nodes.
Definition: X86ISelLowering.cpp:21061
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
PerformOrCombine
static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:20654
PerformVZEXT_MOVLCombine
static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:21528
PerformAndCombine
static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget)
Definition: X86ISelLowering.cpp:20590
virtual SDValue llvm::TargetLowering::prepareVolatileOrAtomicLoad ( SDValue  Chain,
SDLoc  DL,
SelectionDAG &  DAG 
) const
inlinevirtualinherited

This callback is used to prepare for a volatile or atomic load. It takes a chain node as input and returns the chain for the load itself.

Having a callback like this is necessary for targets like SystemZ, which allows a CPU to reuse the result of a previous load indefinitely, even if a cache-coherent store is performed by another CPU. The default implementation does nothing.

Reimplemented in llvm::SystemZTargetLowering.

Definition at line 2355 of file TargetLowering.h.

2356  {
2357  return Chain;
2358  }
void X86TargetLowering::ReplaceNodeResults ( SDNode *  N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG &  DAG 
) const
overridevirtual

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code.

ReplaceNodeResults - Replace a node with an illegal result type with a new node built out of custom code.

Reimplemented from llvm::TargetLowering.

Definition at line 16320 of file X86ISelLowering.cpp.

16322  {
16323  SDLoc dl(N);
16324  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16325  switch (N->getOpcode()) {
16326  default:
16327  llvm_unreachable("Do not know how to custom type legalize this operation!");
16328  case ISD::SIGN_EXTEND_INREG:
16329  case ISD::ADDC:
16330  case ISD::ADDE:
16331  case ISD::SUBC:
16332  case ISD::SUBE:
16333  // We don't want to expand or promote these.
16334  return;
16335  case ISD::SDIV:
16336  case ISD::UDIV:
16337  case ISD::SREM:
16338  case ISD::UREM:
16339  case ISD::SDIVREM:
16340  case ISD::UDIVREM: {
16341  SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
16342  Results.push_back(V);
16343  return;
16344  }
16345  case ISD::FP_TO_SINT:
16346  case ISD::FP_TO_UINT: {
16347  bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
16348 
16349  if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
16350  return;
16351 
16352  std::pair<SDValue,SDValue> Vals =
16353  FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
16354  SDValue FIST = Vals.first, StackSlot = Vals.second;
16355  if (FIST.getNode()) {
16356  EVT VT = N->getValueType(0);
16357  // Return a load from the stack slot.
16358  if (StackSlot.getNode())
16359  Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
16360  MachinePointerInfo(),
16361  false, false, false, 0));
16362  else
16363  Results.push_back(FIST);
16364  }
16365  return;
16366  }
16367  case ISD::UINT_TO_FP: {
16368  assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16369  if (N->getOperand(0).getValueType() != MVT::v2i32 ||
16370  N->getValueType(0) != MVT::v2f32)
16371  return;
16372  SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
16373  N->getOperand(0));
16374  SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
16375  MVT::f64);
16376  SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
16377  SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
16378  DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
16379  Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
16380  SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
16381  Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
16382  return;
16383  }
16384  case ISD::FP_ROUND: {
16385  if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
16386  return;
16387  SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
16388  Results.push_back(V);
16389  return;
16390  }
16391  case ISD::INTRINSIC_W_CHAIN: {
16392  unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
16393  switch (IntNo) {
16394  default : llvm_unreachable("Do not know how to custom type "
16395  "legalize this intrinsic operation!");
16396  case Intrinsic::x86_rdtsc:
16397  return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16398  Results);
16399  case Intrinsic::x86_rdtscp:
16400  return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
16401  Results);
16402  case Intrinsic::x86_rdpmc:
16403  return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
16404  }
16405  }
16406  case ISD::READCYCLECOUNTER: {
16407  return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16408  Results);
16409  }
16410  case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
16411  EVT T = N->getValueType(0);
16412  assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
16413  bool Regs64bit = T == MVT::i128;
16414  EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
16415  SDValue cpInL, cpInH;
16416  cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16417  DAG.getConstant(0, HalfT));
16418  cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16419  DAG.getConstant(1, HalfT));
16420  cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
16421  Regs64bit ? X86::RAX : X86::EAX,
16422  cpInL, SDValue());
16423  cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
16424  Regs64bit ? X86::RDX : X86::EDX,
16425  cpInH, cpInL.getValue(1));
16426  SDValue swapInL, swapInH;
16427  swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16428  DAG.getConstant(0, HalfT));
16429  swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16430  DAG.getConstant(1, HalfT));
16431  swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
16432  Regs64bit ? X86::RBX : X86::EBX,
16433  swapInL, cpInH.getValue(1));
16434  swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
16435  Regs64bit ? X86::RCX : X86::ECX,
16436  swapInH, swapInL.getValue(1));
16437  SDValue Ops[] = { swapInH.getValue(0),
16438  N->getOperand(1),
16439  swapInH.getValue(1) };
16440  SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16441  MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
16442  unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
16443  X86ISD::LCMPXCHG8_DAG;
16444  SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
16445  SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
16446  Regs64bit ? X86::RAX : X86::EAX,
16447  HalfT, Result.getValue(1));
16448  SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
16449  Regs64bit ? X86::RDX : X86::EDX,
16450  HalfT, cpOutL.getValue(2));
16451  SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
16452 
16453  SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
16454  MVT::i32, cpOutH.getValue(2));
16455  SDValue Success =
16456  DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16457  DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16458  Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
16459 
16460  Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
16461  Results.push_back(Success);
16462  Results.push_back(EFLAGS.getValue(1));
16463  return;
16464  }
16465  case ISD::ATOMIC_SWAP:
16466  case ISD::ATOMIC_LOAD_ADD:
16467  case ISD::ATOMIC_LOAD_SUB:
16468  case ISD::ATOMIC_LOAD_AND:
16469  case ISD::ATOMIC_LOAD_OR:
16470  case ISD::ATOMIC_LOAD_XOR:
16471  case ISD::ATOMIC_LOAD_NAND:
16472  case ISD::ATOMIC_LOAD_MIN:
16473  case ISD::ATOMIC_LOAD_MAX:
16474  case ISD::ATOMIC_LOAD_UMIN:
16475  case ISD::ATOMIC_LOAD_UMAX:
16476  // Delegate to generic TypeLegalization. Situations we can really handle
16477  // should have already been dealt with by X86AtomicExpand.cpp.
16478  break;
16479  case ISD::ATOMIC_LOAD: {
16480  ReplaceATOMIC_LOAD(N, Results, DAG);
16481  return;
16482  }
16483  case ISD::BITCAST: {
16484  assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16485  EVT DstVT = N->getValueType(0);
16486  EVT SrcVT = N->getOperand(0)->getValueType(0);
16487 
16488  if (SrcVT != MVT::f64 ||
16489  (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
16490  return;
16491 
16492  unsigned NumElts = DstVT.getVectorNumElements();
16493  EVT SVT = DstVT.getVectorElementType();
16494  EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16495  SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
16496  MVT::v2f64, N->getOperand(0));
16497  SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
16498 
16499  if (ExperimentalVectorWideningLegalization) {
16500  // If we are legalizing vectors by widening, we already have the desired
16501  // legal vector type, just return it.
16502  Results.push_back(ToVecInt);
16503  return;
16504  }
16505 
16506  SmallVector<SDValue, 8> Elts;
16507  for (unsigned i = 0, e = NumElts; i != e; ++i)
16508  Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
16509  ToVecInt, DAG.getIntPtrConstant(i)));
16510 
16511  Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
16512  }
16513  }
16514 }
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:150
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:486
llvm::SDNode::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:401
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:592
llvm::TargetLoweringBase::getValueType
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
Definition: TargetLowering.h:638
llvm::X86TargetLowering::LowerWin64_i128OP
SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const
Definition: X86ISelLowering.cpp:15106
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Definition: SelectionDAGNodes.h:648
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Definition: SelectionDAG.cpp:5166
llvm::SelectionDAG::getConstantFP
SDValue getConstantFP(double Val, EVT VT, bool isTarget=false)
Definition: SelectionDAG.cpp:1243
llvm::EVT::getVectorElementType
EVT getVectorElementType() const
Definition: ValueTypes.h:217
getReadTimeStampCounter
static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode, SelectionDAG &DAG, const X86Subtarget *Subtarget, SmallVectorImpl< SDValue > &Results)
Definition: X86ISelLowering.cpp:14325
T
#define T
Definition: Mips16ISelLowering.cpp:349
llvm::X86TargetLowering::isIntegerTypeFTOL
bool isIntegerTypeFTOL(EVT VT) const
Definition: X86ISelLowering.h:763
llvm::X86Subtarget::hasSSE2
bool hasSSE2() const
Definition: X86Subtarget.h:312
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
assert
assert(Globals.size() > 1)
llvm::APIntOps::Or
APInt Or(const APInt &LHS, const APInt &RHS)
Bitwise OR function for APInt.
Definition: APInt.h:1870
llvm::SelectionDAG::getCopyFromReg
SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT)
Definition: SelectionDAG.h:511
llvm::EVT::getVectorVT
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements)
Definition: ValueTypes.h:71
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, bool isTarget=false)
Definition: SelectionDAG.cpp:1200
llvm::X86ISD::RDTSCP_DAG
X86 Read Time-Stamp Counter and Processor ID.
Definition: X86ISelLowering.h:87
llvm::BitsToDouble
double BitsToDouble(uint64_t Bits)
Definition: MathExtras.h:488
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
getReadPerformanceCounter
static void getReadPerformanceCounter(SDNode *N, SDLoc DL, SelectionDAG &DAG, const X86Subtarget *Subtarget, SmallVectorImpl< SDValue > &Results)
Definition: X86ISelLowering.cpp:14279
Success
#define Success
Definition: AArch64Disassembler.cpp:192
N
#define N
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getMemIntrinsicNode
SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align=0, bool Vol=false, bool ReadMem=true, bool WriteMem=true)
Definition: SelectionDAG.cpp:4586
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::X86TargetLowering::FP_TO_INTHelper
std::pair< SDValue, SDValue > FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool isSigned, bool isReplace) const
Definition: X86ISelLowering.cpp:10988
llvm::SelectionDAG::getZExtOrTrunc
SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:1009
llvm::SelectionDAG::getTargetLoweringInfo
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:278
ExperimentalVectorWideningLegalization
static cl::opt< bool > ExperimentalVectorWideningLegalization("x86-experimental-vector-widening-legalization", cl::init(false), cl::desc("Enable an experimental vector type legalization through widening ""rather than promotion."), cl::Hidden)
ReplaceATOMIC_LOAD
static void ReplaceATOMIC_LOAD(SDNode *Node, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
Definition: X86ISelLowering.cpp:16295
llvm::EVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: ValueTypes.h:226
void X86TargetLowering::resetOperationActions ( )
overridevirtual

Reset the operation actions based on target options.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 224 of file X86ISelLowering.cpp.

224  {
225  const TargetMachine &TM = getTargetMachine();
226  static bool FirstTimeThrough = true;
227 
228  // If none of the target options have changed, then we don't need to reset the
229  // operation actions.
230  if (!FirstTimeThrough && TO == TM.Options) return;
231 
232  if (!FirstTimeThrough) {
233  // Reinitialize the actions.
234  initActions();
235  FirstTimeThrough = false;
236  }
237 
238  TO = TM.Options;
239 
240  // Set up the TargetLowering object.
241  static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
242 
243  // X86 is weird, it always uses i8 for shift amounts and setcc results.
244  setBooleanContents(ZeroOrOneBooleanContent);
245  // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
246  setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
247 
248  // For 64-bit since we have so many registers use the ILP scheduler, for
249  // 32-bit code use the register pressure specific scheduling.
250  // For Atom, always use ILP scheduling.
251  if (Subtarget->isAtom())
252  setSchedulingPreference(Sched::ILP);
253  else if (Subtarget->is64Bit())
254  setSchedulingPreference(Sched::ILP);
255  else
256  setSchedulingPreference(Sched::RegPressure);
257  const X86RegisterInfo *RegInfo =
258  static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
259  setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
260 
261  // Bypass expensive divides on Atom when compiling with O2
262  if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
263  addBypassSlowDiv(32, 8);
264  if (Subtarget->is64Bit())
265  addBypassSlowDiv(64, 16);
266  }
267 
268  if (Subtarget->isTargetKnownWindowsMSVC()) {
269  // Setup Windows compiler runtime calls.
270  setLibcallName(RTLIB::SDIV_I64, "_alldiv");
271  setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
272  setLibcallName(RTLIB::SREM_I64, "_allrem");
273  setLibcallName(RTLIB::UREM_I64, "_aullrem");
274  setLibcallName(RTLIB::MUL_I64, "_allmul");
275  setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
276  setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
277  setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
278  setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
279  setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
280 
281  // The _ftol2 runtime function has an unusual calling conv, which
282  // is modeled by a special pseudo-instruction.
283  setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
284  setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
285  setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
286  setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
287  }
288 
289  if (Subtarget->isTargetDarwin()) {
290  // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
291  setUseUnderscoreSetJmp(false);
292  setUseUnderscoreLongJmp(false);
293  } else if (Subtarget->isTargetWindowsGNU()) {
294  // MS runtime is weird: it exports _setjmp, but longjmp!
295  setUseUnderscoreSetJmp(true);
296  setUseUnderscoreLongJmp(false);
297  } else {
298  setUseUnderscoreSetJmp(true);
299  setUseUnderscoreLongJmp(true);
300  }
301 
302  // Set up the register classes.
303  addRegisterClass(MVT::i8, &X86::GR8RegClass);
304  addRegisterClass(MVT::i16, &X86::GR16RegClass);
305  addRegisterClass(MVT::i32, &X86::GR32RegClass);
306  if (Subtarget->is64Bit())
307  addRegisterClass(MVT::i64, &X86::GR64RegClass);
308 
309  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
310 
311  // We don't accept any truncstore of integer registers.
312  setTruncStoreAction(MVT::i64, MVT::i32, Expand);
313  setTruncStoreAction(MVT::i64, MVT::i16, Expand);
314  setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
315  setTruncStoreAction(MVT::i32, MVT::i16, Expand);
316  setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
317  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
318 
319  // SETOEQ and SETUNE require checking two conditions.
320  setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321  setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322  setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
323  setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
324  setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
325  setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
326 
327  // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
328  // operation.
329  setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
330  setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331  setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
332 
333  if (Subtarget->is64Bit()) {
334  setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
335  setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336  } else if (!TM.Options.UseSoftFloat) {
337  // We have an algorithm for SSE2->double, and we turn this into a
338  // 64-bit FILD followed by conditional FADD for other targets.
339  setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340  // We have an algorithm for SSE2, and we turn this into a 64-bit
341  // FILD for other targets.
342  setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
343  }
344 
345  // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
346  // this operation.
347  setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348  setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
349 
350  if (!TM.Options.UseSoftFloat) {
351  // SSE has no i16 to fp conversion, only i32
352  if (X86ScalarSSEf32) {
353  setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354  // f32 and f64 cases are Legal, f80 case is not
355  setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
356  } else {
357  setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358  setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
359  }
360  } else {
361  setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362  setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
363  }
364 
365  // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
366  // are Legal, f80 is custom lowered.
367  setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
368  setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
369 
370  // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
371  // this operation.
372  setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373  setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
374 
375  if (X86ScalarSSEf32) {
376  setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
377  // f32 and f64 cases are Legal, f80 case is not
378  setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
379  } else {
380  setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381  setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
382  }
383 
384  // Handle FP_TO_UINT by promoting the destination to a larger signed
385  // conversion.
386  setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387  setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388  setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
389 
390  if (Subtarget->is64Bit()) {
391  setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392  setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
393  } else if (!TM.Options.UseSoftFloat) {
394  // Since AVX is a superset of SSE3, only check for SSE here.
395  if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
396  // Expand FP_TO_UINT into a select.
397  // FIXME: We would like to use a Custom expander here eventually to do
398  // the optimal thing for SSE vs. the default expansion in the legalizer.
399  setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
400  else
401  // With SSE3 we can use fisttpll to convert to a signed i64; without
402  // SSE, we're stuck with a fistpll.
403  setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
404  }
405 
406  if (isTargetFTOL()) {
407  // Use the _ftol2 runtime function, which has a pseudo-instruction
408  // to handle its weird calling convention.
409  setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
410  }
411 
412  // TODO: when we have SSE, these could be more efficient, by using movd/movq.
413  if (!X86ScalarSSEf64) {
414  setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
415  setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
416  if (Subtarget->is64Bit()) {
417  setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
418  // Without SSE, i64->f64 goes through memory.
419  setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
420  }
421  }
422 
423  // Scalar integer divide and remainder are lowered to use operations that
424  // produce two results, to match the available instructions. This exposes
425  // the two-result form to trivial CSE, which is able to combine x/y and x%y
426  // into a single instruction.
427  //
428  // Scalar integer multiply-high is also lowered to use two-result
429  // operations, to match the available instructions. However, plain multiply
430  // (low) operations are left as Legal, as there are single-result
431  // instructions for this in x86. Using the two-result multiply instructions
432  // when both high and low results are needed must be arranged by dagcombine.
433  for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
434  MVT VT = IntVTs[i];
435  setOperationAction(ISD::MULHS, VT, Expand);
436  setOperationAction(ISD::MULHU, VT, Expand);
437  setOperationAction(ISD::SDIV, VT, Expand);
438  setOperationAction(ISD::UDIV, VT, Expand);
439  setOperationAction(ISD::SREM, VT, Expand);
440  setOperationAction(ISD::UREM, VT, Expand);
441 
442  // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
443  setOperationAction(ISD::ADDC, VT, Custom);
444  setOperationAction(ISD::ADDE, VT, Custom);
445  setOperationAction(ISD::SUBC, VT, Custom);
446  setOperationAction(ISD::SUBE, VT, Custom);
447  }
448 
449  setOperationAction(ISD::BR_JT , MVT::Other, Expand);
450  setOperationAction(ISD::BRCOND , MVT::Other, Custom);
451  setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452  setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453  setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454  setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455  setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456  setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457  setOperationAction(ISD::BR_CC , MVT::i64, Expand);
458  setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
459  setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
460  setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
461  setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
462  setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
463  setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
464  setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
465  if (Subtarget->is64Bit())
466  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
470  setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
471  setOperationAction(ISD::FREM , MVT::f32 , Expand);
472  setOperationAction(ISD::FREM , MVT::f64 , Expand);
473  setOperationAction(ISD::FREM , MVT::f80 , Expand);
474  setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
475 
476  // Promote the i8 variants and force them on up to i32 which has a shorter
477  // encoding.
478  setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
479  AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
480  setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
481  AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
482  if (Subtarget->hasBMI()) {
483  setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
484  setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
485  if (Subtarget->is64Bit())
486  setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
487  } else {
488  setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
489  setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
490  if (Subtarget->is64Bit())
491  setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
492  }
493 
494  if (Subtarget->hasLZCNT()) {
495  // When promoting the i8 variants, force them to i32 for a shorter
496  // encoding.
497  setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498  AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
499  setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
500  AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
501  setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
502  setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
503  if (Subtarget->is64Bit())
504  setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
505  } else {
506  setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507  setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508  setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
509  setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
510  setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
511  setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
512  if (Subtarget->is64Bit()) {
513  setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
514  setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
515  }
516  }
517 
518  // Special handling for half-precision floating point conversions.
519  // If we don't have F16C support, then lower half float conversions
520  // into library calls.
521  if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
522  setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
523  setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
524  }
525 
526  // There's never any support for operations beyond MVT::f32.
527  setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
528  setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
529  setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
530  setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
531 
532  setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
533  setTruncStoreAction(MVT::f32, MVT::f16, Expand);
534  setTruncStoreAction(MVT::f64, MVT::f16, Expand);
535  setTruncStoreAction(MVT::f80, MVT::f16, Expand);
536 
537  if (Subtarget->hasPOPCNT()) {
538  setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
539  } else {
540  setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
541  setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
542  setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
543  if (Subtarget->is64Bit())
544  setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
545  }
546 
547  setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
548 
549  if (!Subtarget->hasMOVBE())
550  setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
551 
552  // These should be promoted to a larger select which is supported.
553  setOperationAction(ISD::SELECT , MVT::i1 , Promote);
554  // X86 wants to expand cmov itself.
555  setOperationAction(ISD::SELECT , MVT::i8 , Custom);
556  setOperationAction(ISD::SELECT , MVT::i16 , Custom);
557  setOperationAction(ISD::SELECT , MVT::i32 , Custom);
558  setOperationAction(ISD::SELECT , MVT::f32 , Custom);
559  setOperationAction(ISD::SELECT , MVT::f64 , Custom);
560  setOperationAction(ISD::SELECT , MVT::f80 , Custom);
561  setOperationAction(ISD::SETCC , MVT::i8 , Custom);
562  setOperationAction(ISD::SETCC , MVT::i16 , Custom);
563  setOperationAction(ISD::SETCC , MVT::i32 , Custom);
564  setOperationAction(ISD::SETCC , MVT::f32 , Custom);
565  setOperationAction(ISD::SETCC , MVT::f64 , Custom);
566  setOperationAction(ISD::SETCC , MVT::f80 , Custom);
567  if (Subtarget->is64Bit()) {
568  setOperationAction(ISD::SELECT , MVT::i64 , Custom);
569  setOperationAction(ISD::SETCC , MVT::i64 , Custom);
570  }
571  setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
572  // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
573  // SjLj exception handling but a light-weight setjmp/longjmp replacement to
574  // support continuation, user-level threading, and etc.. As a result, no
575  // other SjLj exception interfaces are implemented and please don't build
576  // your own exception handling based on them.
577  // LLVM/Clang supports zero-cost DWARF exception handling.
578  setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
579  setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
580 
581  // Darwin ABI issue.
582  setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
583  setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
584  setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
585  setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
586  if (Subtarget->is64Bit())
587  setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
588  setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
589  setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
590  if (Subtarget->is64Bit()) {
591  setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
592  setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
593  setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
594  setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
595  setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
596  }
597  // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
598  setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
599  setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
600  setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
601  if (Subtarget->is64Bit()) {
602  setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
603  setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
604  setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
605  }
606 
607  if (Subtarget->hasSSE1())
608  setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
609 
610  setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
611 
612  // Expand certain atomics
613  for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
614  MVT VT = IntVTs[i];
615  setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
616  setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
617  setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
618  }
619 
620  if (Subtarget->hasCmpxchg16b()) {
621  setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
622  }
623 
624  // FIXME - use subtarget debug flags
625  if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
626  !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
627  setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
628  }
629 
630  if (Subtarget->is64Bit()) {
631  setExceptionPointerRegister(X86::RAX);
632  setExceptionSelectorRegister(X86::RDX);
633  } else {
634  setExceptionPointerRegister(X86::EAX);
635  setExceptionSelectorRegister(X86::EDX);
636  }
637  setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
638  setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
639 
640  setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
641  setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
642 
643  setOperationAction(ISD::TRAP, MVT::Other, Legal);
644  setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
645 
646  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
647  setOperationAction(ISD::VASTART , MVT::Other, Custom);
648  setOperationAction(ISD::VAEND , MVT::Other, Expand);
649  if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
650  // TargetInfo::X86_64ABIBuiltinVaList
651  setOperationAction(ISD::VAARG , MVT::Other, Custom);
652  setOperationAction(ISD::VACOPY , MVT::Other, Custom);
653  } else {
654  // TargetInfo::CharPtrBuiltinVaList
655  setOperationAction(ISD::VAARG , MVT::Other, Expand);
656  setOperationAction(ISD::VACOPY , MVT::Other, Expand);
657  }
658 
659  setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
660  setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
661 
662  setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
663  MVT::i64 : MVT::i32, Custom);
664 
665  if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
666  // f32 and f64 use SSE.
667  // Set up the FP register classes.
668  addRegisterClass(MVT::f32, &X86::FR32RegClass);
669  addRegisterClass(MVT::f64, &X86::FR64RegClass);
670 
671  // Use ANDPD to simulate FABS.
672  setOperationAction(ISD::FABS , MVT::f64, Custom);
673  setOperationAction(ISD::FABS , MVT::f32, Custom);
674 
675  // Use XORP to simulate FNEG.
676  setOperationAction(ISD::FNEG , MVT::f64, Custom);
677  setOperationAction(ISD::FNEG , MVT::f32, Custom);
678 
679  // Use ANDPD and ORPD to simulate FCOPYSIGN.
680  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
681  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
682 
683  // Lower this to FGETSIGNx86 plus an AND.
684  setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
685  setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
686 
687  // We don't support sin/cos/fmod
688  setOperationAction(ISD::FSIN , MVT::f64, Expand);
689  setOperationAction(ISD::FCOS , MVT::f64, Expand);
690  setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
691  setOperationAction(ISD::FSIN , MVT::f32, Expand);
692  setOperationAction(ISD::FCOS , MVT::f32, Expand);
693  setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
694 
695  // Expand FP immediates into loads from the stack, except for the special
696  // cases we handle.
697  addLegalFPImmediate(APFloat(+0.0)); // xorpd
698  addLegalFPImmediate(APFloat(+0.0f)); // xorps
699  } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
700  // Use SSE for f32, x87 for f64.
701  // Set up the FP register classes.
702  addRegisterClass(MVT::f32, &X86::FR32RegClass);
703  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
704 
705  // Use ANDPS to simulate FABS.
706  setOperationAction(ISD::FABS , MVT::f32, Custom);
707 
708  // Use XORP to simulate FNEG.
709  setOperationAction(ISD::FNEG , MVT::f32, Custom);
710 
711  setOperationAction(ISD::UNDEF, MVT::f64, Expand);
712 
713  // Use ANDPS and ORPS to simulate FCOPYSIGN.
714  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
715  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
716 
717  // We don't support sin/cos/fmod
718  setOperationAction(ISD::FSIN , MVT::f32, Expand);
719  setOperationAction(ISD::FCOS , MVT::f32, Expand);
720  setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
721 
722  // Special cases we handle for FP constants.
723  addLegalFPImmediate(APFloat(+0.0f)); // xorps
724  addLegalFPImmediate(APFloat(+0.0)); // FLD0
725  addLegalFPImmediate(APFloat(+1.0)); // FLD1
726  addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
727  addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
728 
729  if (!TM.Options.UnsafeFPMath) {
730  setOperationAction(ISD::FSIN , MVT::f64, Expand);
731  setOperationAction(ISD::FCOS , MVT::f64, Expand);
732  setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
733  }
734  } else if (!TM.Options.UseSoftFloat) {
735  // f32 and f64 in x87.
736  // Set up the FP register classes.
737  addRegisterClass(MVT::f64, &X86::RFP64RegClass);
738  addRegisterClass(MVT::f32, &X86::RFP32RegClass);
739 
740  setOperationAction(ISD::UNDEF, MVT::f64, Expand);
741  setOperationAction(ISD::UNDEF, MVT::f32, Expand);
742  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
743  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
744 
745  if (!TM.Options.UnsafeFPMath) {
746  setOperationAction(ISD::FSIN , MVT::f64, Expand);
747  setOperationAction(ISD::FSIN , MVT::f32, Expand);
748  setOperationAction(ISD::FCOS , MVT::f64, Expand);
749  setOperationAction(ISD::FCOS , MVT::f32, Expand);
750  setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
751  setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
752  }
753  addLegalFPImmediate(APFloat(+0.0)); // FLD0
754  addLegalFPImmediate(APFloat(+1.0)); // FLD1
755  addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
756  addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
757  addLegalFPImmediate(APFloat(+0.0f)); // FLD0
758  addLegalFPImmediate(APFloat(+1.0f)); // FLD1
759  addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
760  addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
761  }
762 
763  // We don't support FMA.
764  setOperationAction(ISD::FMA, MVT::f64, Expand);
765  setOperationAction(ISD::FMA, MVT::f32, Expand);
766 
767  // Long double always uses X87.
768  if (!TM.Options.UseSoftFloat) {
769  addRegisterClass(MVT::f80, &X86::RFP80RegClass);
770  setOperationAction(ISD::UNDEF, MVT::f80, Expand);
771  setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
772  {
773  APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
774  addLegalFPImmediate(TmpFlt); // FLD0
775  TmpFlt.changeSign();
776  addLegalFPImmediate(TmpFlt); // FLD0/FCHS
777 
778  bool ignored;
779  APFloat TmpFlt2(+1.0);
780  TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
781  &ignored);
782  addLegalFPImmediate(TmpFlt2); // FLD1
783  TmpFlt2.changeSign();
784  addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
785  }
786 
787  if (!TM.Options.UnsafeFPMath) {
788  setOperationAction(ISD::FSIN , MVT::f80, Expand);
789  setOperationAction(ISD::FCOS , MVT::f80, Expand);
790  setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
791  }
792 
793  setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
794  setOperationAction(ISD::FCEIL, MVT::f80, Expand);
795  setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
796  setOperationAction(ISD::FRINT, MVT::f80, Expand);
797  setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
798  setOperationAction(ISD::FMA, MVT::f80, Expand);
799  }
800 
801  // Always use a library call for pow.
802  setOperationAction(ISD::FPOW , MVT::f32 , Expand);
803  setOperationAction(ISD::FPOW , MVT::f64 , Expand);
804  setOperationAction(ISD::FPOW , MVT::f80 , Expand);
805 
806  setOperationAction(ISD::FLOG, MVT::f80, Expand);
807  setOperationAction(ISD::FLOG2, MVT::f80, Expand);
808  setOperationAction(ISD::FLOG10, MVT::f80, Expand);
809  setOperationAction(ISD::FEXP, MVT::f80, Expand);
810  setOperationAction(ISD::FEXP2, MVT::f80, Expand);
811 
812  // First set operation action for all vector types to either promote
813  // (for widening) or expand (for scalarization). Then we will selectively
814  // turn on ones that can be effectively codegen'd.
815  for (int i = MVT::FIRST_VECTOR_VALUETYPE;
816  i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
817  MVT VT = (MVT::SimpleValueType)i;
818  setOperationAction(ISD::ADD , VT, Expand);
819  setOperationAction(ISD::SUB , VT, Expand);
820  setOperationAction(ISD::FADD, VT, Expand);
821  setOperationAction(ISD::FNEG, VT, Expand);
822  setOperationAction(ISD::FSUB, VT, Expand);
823  setOperationAction(ISD::MUL , VT, Expand);
824  setOperationAction(ISD::FMUL, VT, Expand);
825  setOperationAction(ISD::SDIV, VT, Expand);
826  setOperationAction(ISD::UDIV, VT, Expand);
827  setOperationAction(ISD::FDIV, VT, Expand);
828  setOperationAction(ISD::SREM, VT, Expand);
829  setOperationAction(ISD::UREM, VT, Expand);
830  setOperationAction(ISD::LOAD, VT, Expand);
831  setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
832  setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
833  setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
834  setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
835  setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
836  setOperationAction(ISD::FABS, VT, Expand);
837  setOperationAction(ISD::FSIN, VT, Expand);
838  setOperationAction(ISD::FSINCOS, VT, Expand);
839  setOperationAction(ISD::FCOS, VT, Expand);
840  setOperationAction(ISD::FSINCOS, VT, Expand);
841  setOperationAction(ISD::FREM, VT, Expand);
842  setOperationAction(ISD::FMA, VT, Expand);
843  setOperationAction(ISD::FPOWI, VT, Expand);
844  setOperationAction(ISD::FSQRT, VT, Expand);
845  setOperationAction(ISD::FCOPYSIGN, VT, Expand);
846  setOperationAction(ISD::FFLOOR, VT, Expand);
847  setOperationAction(ISD::FCEIL, VT, Expand);
848  setOperationAction(ISD::FTRUNC, VT, Expand);
849  setOperationAction(ISD::FRINT, VT, Expand);
850  setOperationAction(ISD::FNEARBYINT, VT, Expand);
851  setOperationAction(ISD::SMUL_LOHI, VT, Expand);
852  setOperationAction(ISD::MULHS, VT, Expand);
853  setOperationAction(ISD::UMUL_LOHI, VT, Expand);
854  setOperationAction(ISD::MULHU, VT, Expand);
855  setOperationAction(ISD::SDIVREM, VT, Expand);
856  setOperationAction(ISD::UDIVREM, VT, Expand);
857  setOperationAction(ISD::FPOW, VT, Expand);
858  setOperationAction(ISD::CTPOP, VT, Expand);
859  setOperationAction(ISD::CTTZ, VT, Expand);
860  setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
861  setOperationAction(ISD::CTLZ, VT, Expand);
862  setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
863  setOperationAction(ISD::SHL, VT, Expand);
864  setOperationAction(ISD::SRA, VT, Expand);
865  setOperationAction(ISD::SRL, VT, Expand);
866  setOperationAction(ISD::ROTL, VT, Expand);
867  setOperationAction(ISD::ROTR, VT, Expand);
868  setOperationAction(ISD::BSWAP, VT, Expand);
869  setOperationAction(ISD::SETCC, VT, Expand);
870  setOperationAction(ISD::FLOG, VT, Expand);
871  setOperationAction(ISD::FLOG2, VT, Expand);
872  setOperationAction(ISD::FLOG10, VT, Expand);
873  setOperationAction(ISD::FEXP, VT, Expand);
874  setOperationAction(ISD::FEXP2, VT, Expand);
875  setOperationAction(ISD::FP_TO_UINT, VT, Expand);
876  setOperationAction(ISD::FP_TO_SINT, VT, Expand);
877  setOperationAction(ISD::UINT_TO_FP, VT, Expand);
878  setOperationAction(ISD::SINT_TO_FP, VT, Expand);
879  setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
880  setOperationAction(ISD::TRUNCATE, VT, Expand);
881  setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
882  setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
883  setOperationAction(ISD::ANY_EXTEND, VT, Expand);
884  setOperationAction(ISD::VSELECT, VT, Expand);
885  setOperationAction(ISD::SELECT_CC, VT, Expand);
886  for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
887  InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
888  setTruncStoreAction(VT,
889  (MVT::SimpleValueType)InnerVT, Expand);
890  setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
891  setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
892 
893  // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
894  // we have to deal with them whether we ask for Expansion or not. Setting
895  // Expand causes its own optimisation problems though, so leave them legal.
896  if (VT.getVectorElementType() == MVT::i1)
897  setLoadExtAction(ISD::EXTLOAD, VT, Expand);
898  }
899 
900  // FIXME: In order to prevent SSE instructions being expanded to MMX ones
901  // with -msoft-float, disable use of MMX as well.
902  if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
903  addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
904  // No operations on x86mmx supported, everything uses intrinsics.
905  }
906 
907  // MMX-sized vectors (other than x86mmx) are expected to be expanded
908  // into smaller operations.
909  setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
910  setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
911  setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
912  setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
913  setOperationAction(ISD::AND, MVT::v8i8, Expand);
914  setOperationAction(ISD::AND, MVT::v4i16, Expand);
915  setOperationAction(ISD::AND, MVT::v2i32, Expand);
916  setOperationAction(ISD::AND, MVT::v1i64, Expand);
917  setOperationAction(ISD::OR, MVT::v8i8, Expand);
918  setOperationAction(ISD::OR, MVT::v4i16, Expand);
919  setOperationAction(ISD::OR, MVT::v2i32, Expand);
920  setOperationAction(ISD::OR, MVT::v1i64, Expand);
921  setOperationAction(ISD::XOR, MVT::v8i8, Expand);
922  setOperationAction(ISD::XOR, MVT::v4i16, Expand);
923  setOperationAction(ISD::XOR, MVT::v2i32, Expand);
924  setOperationAction(ISD::XOR, MVT::v1i64, Expand);
925  setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
926  setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
927  setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
928  setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
929  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
930  setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
931  setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
932  setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
933  setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
934  setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
935  setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
936  setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
937  setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
938 
939  if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
940  addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
941 
942  setOperationAction(ISD::FADD, MVT::v4f32, Legal);
943  setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
944  setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
945  setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
946  setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
947  setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
948  setOperationAction(ISD::FABS, MVT::v4f32, Custom);
949  setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
950  setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
951  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
952  setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
953  setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
954  }
955 
956  if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
957  addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
958 
959  // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
960  // registers cannot be used even for integer operations.
961  addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
962  addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
963  addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
964  addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
965 
966  setOperationAction(ISD::ADD, MVT::v16i8, Legal);
967  setOperationAction(ISD::ADD, MVT::v8i16, Legal);
968  setOperationAction(ISD::ADD, MVT::v4i32, Legal);
969  setOperationAction(ISD::ADD, MVT::v2i64, Legal);
970  setOperationAction(ISD::MUL, MVT::v4i32, Custom);
971  setOperationAction(ISD::MUL, MVT::v2i64, Custom);
972  setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
973  setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
974  setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
975  setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
976  setOperationAction(ISD::SUB, MVT::v16i8, Legal);
977  setOperationAction(ISD::SUB, MVT::v8i16, Legal);
978  setOperationAction(ISD::SUB, MVT::v4i32, Legal);
979  setOperationAction(ISD::SUB, MVT::v2i64, Legal);
980  setOperationAction(ISD::MUL, MVT::v8i16, Legal);
981  setOperationAction(ISD::FADD, MVT::v2f64, Legal);
982  setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
983  setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
984  setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
985  setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
986  setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
987  setOperationAction(ISD::FABS, MVT::v2f64, Custom);
988 
989  setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
990  setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
991  setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
992  setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
993 
994  setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
995  setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
996  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
997  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
998  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
999 
1000  // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1001  for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1002  MVT VT = (MVT::SimpleValueType)i;
1003  // Do not attempt to custom lower non-power-of-2 vectors
1004  if (!isPowerOf2_32(VT.getVectorNumElements()))
1005  continue;
1006  // Do not attempt to custom lower non-128-bit vectors
1007  if (!VT.is128BitVector())
1008  continue;
1009  setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1010  setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1011  setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1012  }
1013 
1014  setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1015  setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1016  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1017  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1018  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1019  setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1020 
1021  if (Subtarget->is64Bit()) {
1022  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023  setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1024  }
1025 
1026  // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1027  for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1028  MVT VT = (MVT::SimpleValueType)i;
1029 
1030  // Do not attempt to promote non-128-bit vectors
1031  if (!VT.is128BitVector())
1032  continue;
1033 
1034  setOperationAction(ISD::AND, VT, Promote);
1035  AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1036  setOperationAction(ISD::OR, VT, Promote);
1037  AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1038  setOperationAction(ISD::XOR, VT, Promote);
1039  AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1040  setOperationAction(ISD::LOAD, VT, Promote);
1041  AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1042  setOperationAction(ISD::SELECT, VT, Promote);
1043  AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1044  }
1045 
1046  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1047 
1048  // Custom lower v2i64 and v2f64 selects.
1049  setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1050  setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1051  setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1052  setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1053 
1054  setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1055  setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1056 
1057  setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1058  setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1059  // As there is no 64-bit GPR available, we need build a special custom
1060  // sequence to convert from v2i32 to v2f32.
1061  if (!Subtarget->is64Bit())
1062  setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1063 
1064  setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1065  setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1066 
1067  setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1068 
1069  setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1070  setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1071  setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1072  }
1073 
1074  if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1075  setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1076  setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1077  setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1078  setOperationAction(ISD::FRINT, MVT::f32, Legal);
1079  setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1080  setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1081  setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1082  setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1083  setOperationAction(ISD::FRINT, MVT::f64, Legal);
1084  setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1085 
1086  setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1087  setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1088  setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1089  setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1090  setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1091  setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1092  setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1093  setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1094  setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1095  setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1096 
1097  // FIXME: Do we need to handle scalar-to-vector here?
1098  setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1099 
1100  setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1101  setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1102  setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1103  setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1104  setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1105  // There is no BLENDI for byte vectors. We don't need to custom lower
1106  // some vselects for now.
1107  setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1108 
1109  // i8 and i16 vectors are custom , because the source register and source
1110  // source memory operand types are not the same width. f32 vectors are
1111  // custom since the immediate controlling the insert encodes additional
1112  // information.
1113  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1114  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1115  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1116  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1117 
1118  setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1119  setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1120  setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1121  setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1122 
1123  // FIXME: these should be Legal but thats only for the case where
1124  // the index is constant. For now custom expand to deal with that.
1125  if (Subtarget->is64Bit()) {
1126  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1127  setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1128  }
1129  }
1130 
1131  if (Subtarget->hasSSE2()) {
1132  setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1133  setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1134 
1135  setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1136  setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1137 
1138  setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1139  setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1140 
1141  // In the customized shift lowering, the legal cases in AVX2 will be
1142  // recognized.
1143  setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1144  setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1145 
1146  setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1147  setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1148 
1149  setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1150  }
1151 
1152  if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1153  addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1154  addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1155  addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1156  addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1157  addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1158  addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1159 
1160  setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1161  setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1162  setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1163 
1164  setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1165  setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1166  setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1167  setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1168  setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1169  setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1170  setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1171  setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1172  setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1173  setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1174  setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1175  setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1176 
1177  setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1178  setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1179  setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1180  setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1181  setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1182  setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1183  setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1184  setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1185  setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1186  setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1187  setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1188  setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1189 
1190  // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1191  // even though v8i16 is a legal type.
1192  setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1193  setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1194  setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1195 
1196  setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1197  setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1198  setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1199 
1200  setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1201  setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1202 
1203  setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1204 
1205  setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1206  setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1207 
1208  setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1209  setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1210 
1211  setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1212  setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1213 
1214  setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1215  setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1216  setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1217  setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1218 
1219  setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1220  setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1221  setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1222 
1223  setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1224  setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1225  setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1226  setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1227 
1228  setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1229  setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1230  setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1231  setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1232  setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1233  setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1234  setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1235  setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1236  setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1237  setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1238  setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1239  setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1240 
1241  if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1242  setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1243  setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1244  setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1245  setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1246  setOperationAction(ISD::FMA, MVT::f32, Legal);
1247  setOperationAction(ISD::FMA, MVT::f64, Legal);
1248  }
1249 
1250  if (Subtarget->hasInt256()) {
1251  setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1252  setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1253  setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1254  setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1255 
1256  setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1257  setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1258  setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1259  setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1260 
1261  setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1262  setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1263  setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1264  // Don't lower v32i8 because there is no 128-bit byte mul
1265 
1266  setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1267  setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1268  setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1269  setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1270 
1271  setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1272  setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1273  } else {
1274  setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1275  setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1276  setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1277  setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1278 
1279  setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1280  setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1281  setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1282  setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1283 
1284  setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1285  setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1286  setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1287  // Don't lower v32i8 because there is no 128-bit byte mul
1288  }
1289 
1290  // In the customized shift lowering, the legal cases in AVX2 will be
1291  // recognized.
1292  setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1293  setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1294 
1295  setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1296  setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1297 
1298  setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1299 
1300  // Custom lower several nodes for 256-bit types.
1301  for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1302  i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1303  MVT VT = (MVT::SimpleValueType)i;
1304 
1305  // Extract subvector is special because the value type
1306  // (result) is 128-bit but the source is 256-bit wide.
1307  if (VT.is128BitVector())
1308  setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1309 
1310  // Do not attempt to custom lower other non-256-bit vectors
1311  if (!VT.is256BitVector())
1312  continue;
1313 
1314  setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1315  setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1316  setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1317  setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1318  setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1319  setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1320  setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1321  }
1322 
1323  // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1324  for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1325  MVT VT = (MVT::SimpleValueType)i;
1326 
1327  // Do not attempt to promote non-256-bit vectors
1328  if (!VT.is256BitVector())
1329  continue;
1330 
1331  setOperationAction(ISD::AND, VT, Promote);
1332  AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1333  setOperationAction(ISD::OR, VT, Promote);
1334  AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1335  setOperationAction(ISD::XOR, VT, Promote);
1336  AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1337  setOperationAction(ISD::LOAD, VT, Promote);
1338  AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1339  setOperationAction(ISD::SELECT, VT, Promote);
1340  AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1341  }
1342  }
1343 
1344  if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1345  addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1346  addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1347  addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1348  addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1349 
1350  addRegisterClass(MVT::i1, &X86::VK1RegClass);
1351  addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1352  addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1353 
1354  setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1355  setOperationAction(ISD::SETCC, MVT::i1, Custom);
1356  setOperationAction(ISD::XOR, MVT::i1, Legal);
1357  setOperationAction(ISD::OR, MVT::i1, Legal);
1358  setOperationAction(ISD::AND, MVT::i1, Legal);
1359  setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1360  setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1361  setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1362  setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1363  setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1364  setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1365 
1366  setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1367  setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1368  setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1369  setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1370  setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1371  setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1372 
1373  setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1374  setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1375  setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1376  setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1377  setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1378  setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1379  setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1380  setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1381 
1382  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1383  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1384  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1385  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1386  if (Subtarget->is64Bit()) {
1387  setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1388  setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1389  setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1390  setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1391  }
1392  setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1393  setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1394  setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1395  setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1396  setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1397  setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1398  setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1399  setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1400  setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1401  setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1402 
1403  setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1404  setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1405  setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1406  setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1407  setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1408  setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1409  setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1410  setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1411  setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1412  setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1413  setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1414  setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1415  setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1416 
1417  setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1418  setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1419  setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1420  setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1421  setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1422  setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1423 
1424  setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1425  setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1426 
1427  setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1428 
1429  setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1430  setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1431  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1432  setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1433  setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1434  setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1435  setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1436  setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1437  setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1438 
1439  setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1440  setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1441 
1442  setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1443  setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1444 
1445  setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1446 
1447  setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1448  setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1449 
1450  setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1451  setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1452 
1453  setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1454  setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1455 
1456  setOperationAction(ISD::AND, MVT::v8i64, Legal);
1457  setOperationAction(ISD::OR, MVT::v8i64, Legal);
1458  setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1459  setOperationAction(ISD::AND, MVT::v16i32, Legal);
1460  setOperationAction(ISD::OR, MVT::v16i32, Legal);
1461  setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1462 
1463  if (Subtarget->hasCDI()) {
1464  setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1465  setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1466  }
1467 
1468  // Custom lower several nodes.
1469  for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1470  i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1471  MVT VT = (MVT::SimpleValueType)i;
1472 
1473  unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1474  // Extract subvector is special because the value type
1475  // (result) is 256/128-bit but the source is 512-bit wide.
1476  if (VT.is128BitVector() || VT.is256BitVector())
1477  setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1478 
1479  if (VT.getVectorElementType() == MVT::i1)
1480  setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1481 
1482  // Do not attempt to custom lower other non-512-bit vectors
1483  if (!VT.is512BitVector())
1484  continue;
1485 
1486  if ( EltSize >= 32) {
1487  setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1488  setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1489  setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1490  setOperationAction(ISD::VSELECT, VT, Legal);
1491  setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1492  setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1493  setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1494  }
1495  }
1496  for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1497  MVT VT = (MVT::SimpleValueType)i;
1498 
1499  // Do not attempt to promote non-256-bit vectors
1500  if (!VT.is512BitVector())
1501  continue;
1502 
1503  setOperationAction(ISD::SELECT, VT, Promote);
1504  AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1505  }
1506  }// has AVX-512
1507 
1508  // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1509  // of this type with custom code.
1510  for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1511  VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1512  setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1513  Custom);
1514  }
1515 
1516  // We want to custom lower some of our intrinsics.
1517  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1518  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1519  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1520  if (!Subtarget->is64Bit())
1521  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1522 
1523  // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1524  // handle type legalization for these operations here.
1525  //
1526  // FIXME: We really should do custom legalization for addition and
1527  // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1528  // than generic legalization for 64-bit multiplication-with-overflow, though.
1529  for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1530  // Add/Sub/Mul with overflow operations are custom lowered.
1531  MVT VT = IntVTs[i];
1532  setOperationAction(ISD::SADDO, VT, Custom);
1533  setOperationAction(ISD::UADDO, VT, Custom);
1534  setOperationAction(ISD::SSUBO, VT, Custom);
1535  setOperationAction(ISD::USUBO, VT, Custom);
1536  setOperationAction(ISD::SMULO, VT, Custom);
1537  setOperationAction(ISD::UMULO, VT, Custom);
1538  }
1539 
1540  // There are no 8-bit 3-address imul/mul instructions
1541  setOperationAction(ISD::SMULO, MVT::i8, Expand);
1542  setOperationAction(ISD::UMULO, MVT::i8, Expand);
1543 
1544  if (!Subtarget->is64Bit()) {
1545  // These libcalls are not available in 32-bit.
1546  setLibcallName(RTLIB::SHL_I128, nullptr);
1547  setLibcallName(RTLIB::SRL_I128, nullptr);
1548  setLibcallName(RTLIB::SRA_I128, nullptr);
1549  }
1550 
1551  // Combine sin / cos into one node or libcall if possible.
1552  if (Subtarget->hasSinCos()) {
1553  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1554  setLibcallName(RTLIB::SINCOS_F64, "sincos");
1555  if (Subtarget->isTargetDarwin()) {
1556  // For MacOSX, we don't want to the normal expansion of a libcall to
1557  // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1558  // traffic.
1559  setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1560  setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1561  }
1562  }
1563 
1564  if (Subtarget->isTargetWin64()) {
1565  setOperationAction(ISD::SDIV, MVT::i128, Custom);
1566  setOperationAction(ISD::UDIV, MVT::i128, Custom);
1567  setOperationAction(ISD::SREM, MVT::i128, Custom);
1568  setOperationAction(ISD::UREM, MVT::i128, Custom);
1569  setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1570  setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1571  }
1572 
1573  // We have target-specific dag combine patterns for the following nodes:
1574  setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1575  setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1576  setTargetDAGCombine(ISD::VSELECT);
1577  setTargetDAGCombine(ISD::SELECT);
1578  setTargetDAGCombine(ISD::SHL);
1579  setTargetDAGCombine(ISD::SRA);
1580  setTargetDAGCombine(ISD::SRL);
1581  setTargetDAGCombine(ISD::OR);
1582  setTargetDAGCombine(ISD::AND);
1583  setTargetDAGCombine(ISD::ADD);
1584  setTargetDAGCombine(ISD::FADD);
1585  setTargetDAGCombine(ISD::FSUB);
1586  setTargetDAGCombine(ISD::FMA);
1587  setTargetDAGCombine(ISD::SUB);
1588  setTargetDAGCombine(ISD::LOAD);
1589  setTargetDAGCombine(ISD::STORE);
1590  setTargetDAGCombine(ISD::ZERO_EXTEND);
1591  setTargetDAGCombine(ISD::ANY_EXTEND);
1592  setTargetDAGCombine(ISD::SIGN_EXTEND);
1593  setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1594  setTargetDAGCombine(ISD::TRUNCATE);
1595  setTargetDAGCombine(ISD::SINT_TO_FP);
1596  setTargetDAGCombine(ISD::SETCC);
1597  setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1598  setTargetDAGCombine(ISD::BUILD_VECTOR);
1599  if (Subtarget->is64Bit())
1600  setTargetDAGCombine(ISD::MUL);
1601  setTargetDAGCombine(ISD::XOR);
1602 
1603  computeRegisterProperties();
1604 
1605  // On Darwin, -Os means optimize for size without hurting performance,
1606  // do not reduce the limit.
1607  MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1608  MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1609  MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1610  MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1611  MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1612  MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1613  setPrefLoopAlignment(4); // 2^4 bytes.
1614 
1615  // Predictable cmov don't hurt on atom because it's in-order.
1616  PredictableSelectIsExpensive = !Subtarget->isAtom();
1617 
1618  setPrefFunctionAlignment(4); // 2^4 bytes.
1619 }
llvm::X86Subtarget::hasF16C
bool hasF16C() const
Definition: X86Subtarget.h:335
llvm::X86TargetLowering::Subtarget
const X86Subtarget * Subtarget
Definition: X86ISelLowering.h:809
llvm::X86Subtarget::hasSSE3
bool hasSSE3() const
Definition: X86Subtarget.h:313
llvm::X86Subtarget::isTargetCygMing
bool isTargetCygMing() const
Definition: X86Subtarget.h:403
llvm::TargetLoweringBase::getTargetMachine
const TargetMachine & getTargetMachine() const
Definition: TargetLowering.h:149
llvm::TargetLoweringBase::TM
const TargetMachine & TM
True if this is a little endian target.
Definition: TargetLowering.h:1452
llvm::MVT::is512BitVector
bool is512BitVector() const
is512BitVector - Return true if this is a 512-bit vector type.
Definition: MachineValueType.h:224
llvm::X86Subtarget::hasFMA4
bool hasFMA4() const
Definition: X86Subtarget.h:330
llvm::X86Subtarget::hasBMI
bool hasBMI() const
Definition: X86Subtarget.h:338
llvm::MVT::getSizeInBits
unsigned getSizeInBits() const
Definition: MachineValueType.h:360
llvm::X86Subtarget::isTargetKnownWindowsMSVC
bool isTargetKnownWindowsMSVC() const
Definition: X86Subtarget.h:391
llvm::X86Subtarget::hasSSE41
bool hasSSE41() const
Definition: X86Subtarget.h:315
llvm::TargetLoweringBase::setBooleanVectorContents
void setBooleanVectorContents(BooleanContent Ty)
Definition: TargetLowering.h:978
llvm::APFloat::getZero
static APFloat getZero(const fltSemantics &Sem, bool Negative=false)
Definition: APFloat.h:213
llvm::ISD::SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:221
llvm::X86Subtarget::hasCmpxchg16b
bool hasCmpxchg16b() const
Definition: X86Subtarget.h:350
llvm::TargetLoweringBase::setTruncStoreAction
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Definition: TargetLowering.h:1119
llvm::APFloat::x87DoubleExtended
static const fltSemantics x87DoubleExtended
Definition: APFloat.h:136
llvm::X86Subtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: X86Subtarget.h:370
llvm::TargetLoweringBase::setCondCodeAction
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Definition: TargetLowering.h:1156
llvm::TargetLoweringBase::addBypassSlowDiv
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)
Tells the code generator which bitwidths to bypass.
Definition: TargetLowering.h:1063
llvm::TargetLoweringBase::setOperationAction
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Definition: TargetLowering.h:1102
llvm::X86Subtarget::hasMMX
bool hasMMX() const
Definition: X86Subtarget.h:310
llvm::X86Subtarget::hasLZCNT
bool hasLZCNT() const
Definition: X86Subtarget.h:337
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:283
llvm::X86Subtarget::isTargetWindowsGNU
bool isTargetWindowsGNU() const
Definition: X86Subtarget.h:399
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
f
foo f
Definition: dwarfdump-line-dwo.cc:4
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Definition: TargetMachine.cpp:140
llvm::ISD::UNDEF
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
llvm::X86Subtarget::hasSSE2
bool hasSSE2() const
Definition: X86Subtarget.h:312
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
llvm::APFloat
A self-contained host- and target-independent arbitrary-precision floating-point software implementat...
Definition: APFloat.h:122
llvm::MVT::getVectorNumElements
unsigned getVectorNumElements() const
Definition: MachineValueType.h:312
llvm::TargetLoweringBase::addRegisterClass
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Definition: TargetLowering.h:1074
llvm::ISD::FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:227
llvm::TargetLoweringBase::setTargetDAGCombine
void setTargetDAGCombine(ISD::NodeType NT)
Definition: TargetLowering.h:1180
llvm::X86Subtarget::hasSinCos
bool hasSinCos() const
Definition: X86Subtarget.cpp:168
llvm::TargetLoweringBase::setBooleanContents
void setBooleanContents(BooleanContent Ty)
Definition: TargetLowering.h:964
llvm::X86Subtarget::hasMOVBE
bool hasMOVBE() const
Definition: X86Subtarget.h:333
llvm::X86Subtarget::hasFp256
bool hasFp256() const
Definition: X86Subtarget.h:320
llvm::ISD::TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:622
llvm::TargetLoweringBase::setPrefFunctionAlignment
void setPrefFunctionAlignment(unsigned Align)
Definition: TargetLowering.h:1204
llvm::ISD::DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:625
llvm::APFloat::changeSign
void changeSign()
Definition: APFloat.cpp:1609
llvm::TargetLoweringBase::AddPromotedToType
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
Definition: TargetLowering.h:1173
llvm::TargetLoweringBase::MaxStoresPerMemmove
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Definition: TargetLowering.h:1830
llvm::ISD::CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:317
llvm::ISD::FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:447
llvm::TargetLoweringBase::setUseUnderscoreLongJmp
void setUseUnderscoreLongJmp(bool Val)
Definition: TargetLowering.h:995
llvm::TargetLoweringBase::setLibcallCallingConv
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
Definition: TargetLowering.h:1442
llvm::X86RegisterInfo::getStackRegister
unsigned getStackRegister() const
Definition: X86RegisterInfo.h:125
llvm::TargetLoweringBase::setLoadExtAction
void setLoadExtAction(unsigned ExtType, MVT VT, LegalizeAction Action)
Definition: TargetLowering.h:1110
llvm::TargetLoweringBase::initActions
void initActions()
Initialize all of the actions to default values.
Definition: TargetLoweringBase.cpp:733
llvm::TargetLoweringBase::setExceptionPointerRegister
void setExceptionPointerRegister(unsigned R)
Definition: TargetLowering.h:1018
llvm::X86Subtarget::isTargetELF
bool isTargetELF() const
Definition: X86Subtarget.h:378
llvm::X86Subtarget::hasSlowDivide
bool hasSlowDivide() const
Definition: X86Subtarget.h:352
llvm::ISD::BSWAP
Byte Swap and Counting operators.
Definition: ISDOpcodes.h:314
llvm::X86Subtarget::hasCDI
bool hasCDI() const
Definition: X86Subtarget.h:358
llvm::MVT::is128BitVector
bool is128BitVector() const
is128BitVector - Return true if this is a 128-bit vector type.
Definition: MachineValueType.h:210
llvm::TargetLoweringBase::setExceptionSelectorRegister
void setExceptionSelectorRegister(unsigned R)
Definition: TargetLowering.h:1024
llvm::X86Subtarget::hasInt256
bool hasInt256() const
Definition: X86Subtarget.h:321
llvm::TargetLoweringBase::setPrefLoopAlignment
void setPrefLoopAlignment(unsigned Align)
Definition: TargetLowering.h:1211
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
llvm::X86Subtarget::hasPOPCNT
bool hasPOPCNT() const
Definition: X86Subtarget.h:325
llvm::X86Subtarget::hasSSE1
bool hasSSE1() const
Definition: X86Subtarget.h:311
llvm::X86Subtarget::isAtom
bool isAtom() const
Definition: X86Subtarget.h:365
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
llvm::MVT::is256BitVector
bool is256BitVector() const
is256BitVector - Return true if this is a 256-bit vector type.
Definition: MachineValueType.h:217
llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore
void setStackPointerRegisterToSaveRestore(unsigned R)
Definition: TargetLowering.h:1012
llvm::X86Subtarget::hasAVX512
bool hasAVX512() const
Definition: X86Subtarget.h:319
llvm::TargetLoweringBase::setLibcallName
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
Definition: TargetLowering.h:1420
llvm::ISD::SMULO
Same for multiplication.
Definition: ISDOpcodes.h:224
llvm::TargetMachine::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
Definition: Target/TargetMachine.h:143
llvm::ISD::FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
Definition: ISDOpcodes.h:490
llvm::TargetLoweringBase::MaxStoresPerMemcpy
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
Definition: TargetLowering.h:1814
llvm::X86Subtarget::isTargetWin64
bool isTargetWin64() const
Definition: X86Subtarget.h:407
llvm::TargetLoweringBase::setSchedulingPreference
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
Definition: TargetLowering.h:983
llvm::TargetLoweringBase::setUseUnderscoreSetJmp
void setUseUnderscoreSetJmp(bool Val)
Definition: TargetLowering.h:989
llvm::X86TargetLowering::addLegalFPImmediate
void addLegalFPImmediate(const APFloat &Imm)
Definition: X86ISelLowering.h:828
llvm::isPowerOf2_32
bool isPowerOf2_32(uint32_t Value)
Definition: MathExtras.h:363
llvm::TargetLoweringBase::MaxStoresPerMemset
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
Definition: TargetLowering.h:1797
llvm::MVT::getVectorElementType
MVT getVectorElementType() const
Definition: MachineValueType.h:264
llvm::X86Subtarget::hasFMA
bool hasFMA() const
Definition: X86Subtarget.h:328
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  Ty)
inlineprotectedinherited

Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. See getBooleanContents.

Definition at line 964 of file TargetLowering.h.

964  {
965  BooleanContents = Ty;
966  BooleanFloatContents = Ty;
967  }
llvm::TargetLoweringBase::BooleanFloatContents
BooleanContent BooleanFloatContents
Definition: TargetLowering.h:1520
llvm::TargetLoweringBase::BooleanContents
BooleanContent BooleanContents
Definition: TargetLowering.h:1516
void llvm::TargetLoweringBase::setBooleanContents ( BooleanContent  IntTy,
BooleanContent  FloatTy 
)
inlineprotectedinherited

Specify how the target extends the result of integer and floating point boolean values from i1 to a wider type. See getBooleanContents.

Definition at line 971 of file TargetLowering.h.

971  {
972  BooleanContents = IntTy;
973  BooleanFloatContents = FloatTy;
974  }
llvm::TargetLoweringBase::BooleanFloatContents
BooleanContent BooleanFloatContents
Definition: TargetLowering.h:1520
llvm::TargetLoweringBase::BooleanContents
BooleanContent BooleanContents
Definition: TargetLowering.h:1516
void llvm::TargetLoweringBase::setBooleanVectorContents ( BooleanContent  Ty)
inlineprotectedinherited

Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider type. See getBooleanContents.

Definition at line 978 of file TargetLowering.h.

978  {
979  BooleanVectorContents = Ty;
980  }
llvm::TargetLoweringBase::BooleanVectorContents
BooleanContent BooleanVectorContents
Definition: TargetLowering.h:1524
void llvm::TargetLoweringBase::setCmpLibcallCC ( RTLIB::Libcall  Call,
ISD::CondCode  CC 
)
inlineinherited

Override the default CondCode to be used to test the result of the comparison libcall against zero.

Definition at line 1431 of file TargetLowering.h.

1431  {
1432  CmpLibcallCCs[Call] = CC;
1433  }
llvm::TargetLoweringBase::CmpLibcallCCs
ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL]
Definition: TargetLowering.h:1781
void llvm::TargetLoweringBase::setCondCodeAction ( ISD::CondCode  CC,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified condition code is or isn't supported on the target and indicate what to do about it.

The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit value and the upper 27 bits index into the second dimension of the array to select what 32-bit value to use.

Definition at line 1156 of file TargetLowering.h.

1157  {
1158  assert(VT < MVT::LAST_VALUETYPE &&
1159  (unsigned)CC < array_lengthof(CondCodeActions) &&
1160  "Table isn't big enough!");
1161  /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1162  /// value and the upper 27 bits index into the second dimension of the array
1163  /// to select what 32-bit value to use.
1164  uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1165  CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1166  CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1167  }
Action
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::CondCodeActions
uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE+15)/16]
Definition: TargetLowering.h:1623
void llvm::TargetLoweringBase::setExceptionPointerRegister ( unsigned  R)
inlineprotectedinherited

If set to a physical register, this sets the register that receives the exception address on entry to a landing pad.

Definition at line 1018 of file TargetLowering.h.

1018  {
1019  ExceptionPointerRegister = R;
1020  }
void llvm::TargetLoweringBase::setExceptionSelectorRegister ( unsigned  R)
inlineprotectedinherited

If set to a physical register, this sets the register that receives the exception typeid on entry to a landing pad.

Definition at line 1024 of file TargetLowering.h.

1024  {
1025  ExceptionSelectorRegister = R;
1026  }
void llvm::TargetLoweringBase::setHasExtractBitsInsn ( bool  hasExtractInsn = true)
inlineprotectedinherited

Tells the code generator that the target has BitExtract instructions. The code generator will aggressively sink "shift"s into the blocks of their users if the users will generate "and" instructions which can be combined with "shift" to BitExtract instructions.

Definition at line 1047 of file TargetLowering.h.

1047  {
1048  HasExtractBitsInsn = hasExtractInsn;
1049  }
void llvm::TargetLoweringBase::setHasMultipleConditionRegisters ( bool  hasManyRegs = true)
inlineprotectedinherited

Tells the code generator that the target has multiple (allocatable) condition registers that can be used to store the results of comparisons for use by selects and conditional branches. With multiple condition registers, the code generator will not aggressively sink comparisons into the blocks of their users.

Definition at line 1039 of file TargetLowering.h.

1039  {
1040  HasMultipleConditionRegisters = hasManyRegs;
1041  }
void llvm::TargetLoweringBase::setIndexedLoadAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified indexed load does or does not work with the specified type and indicate what to do abort it.

NOTE: All indexed mode loads are initialized to Expand in TargetLowering.cpp

Definition at line 1131 of file TargetLowering.h.

1132  {
1133  assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1134  (unsigned)Action < 0xf && "Table isn't big enough!");
1135  // Load action are kept in the upper half.
1136  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1137  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1138  }
llvm::TargetLoweringBase::IndexedModeActions
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
Definition: TargetLowering.h:1615
Action
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setIndexedStoreAction ( unsigned  IdxMode,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified indexed store does or does not work with the specified type and indicate what to do about it.

NOTE: All indexed mode stores are initialized to Expand in TargetLowering.cpp

Definition at line 1145 of file TargetLowering.h.

1146  {
1147  assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1148  (unsigned)Action < 0xf && "Table isn't big enough!");
1149  // Store action are kept in the lower half.
1150  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1151  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1152  }
llvm::TargetLoweringBase::IndexedModeActions
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE]
Definition: TargetLowering.h:1615
Action
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setInsertFencesForAtomic ( bool  fence)
inlineprotectedinherited

Set if the DAG builder should automatically insert fences and reduce the order of atomic memory operations to Monotonic.

Definition at line 1222 of file TargetLowering.h.

1222  {
1223  InsertFencesForAtomic = fence;
1224  }
void llvm::TargetLoweringBase::setIntDivIsCheap ( bool  isCheap = true)
inlineprotectedinherited

Tells the code generator that integer divide is expensive, and if possible, should be replaced by an alternate sequence of instructions not containing an integer divide.

Definition at line 1060 of file TargetLowering.h.

1060 { IntDivIsCheap = isCheap; }
void llvm::TargetLoweringBase::setJumpBufAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's required jmp_buf buffer alignment (in bytes); default is 0

Definition at line 1192 of file TargetLowering.h.

1192  {
1193  JumpBufAlignment = Align;
1194  }
llvm::TargetLoweringBase::JumpBufAlignment
unsigned JumpBufAlignment
The alignment, in bytes, of the target's jmp_buf buffers.
Definition: TargetLowering.h:1534
Align
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setJumpBufSize ( unsigned  Size)
inlineprotectedinherited

Set the target's required jmp_buf buffer size (in bytes); default is 200.

Definition at line 1186 of file TargetLowering.h.

1186  {
1187  JumpBufSize = Size;
1188  }
llvm::TargetLoweringBase::JumpBufSize
unsigned JumpBufSize
The size, in bytes, of the target's jmp_buf buffers.
Definition: TargetLowering.h:1531
void llvm::TargetLoweringBase::setJumpIsExpensive ( bool  isExpensive = true)
inlineprotectedinherited

Tells the code generator not to expand sequence of operations into a separate sequences that increases the amount of flow control.

Definition at line 1053 of file TargetLowering.h.

1053  {
1054  JumpIsExpensive = isExpensive;
1055  }
void llvm::TargetLoweringBase::setLibcallCallingConv ( RTLIB::Libcall  Call,
CallingConv::ID  CC 
)
inlineinherited

Set the CallingConv that should be used for the specified libcall.

Definition at line 1442 of file TargetLowering.h.

1442  {
1443  LibcallCallingConvs[Call] = CC;
1444  }
llvm::TargetLoweringBase::LibcallCallingConvs
CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL]
Stores the CallingConv that should be used for each libcall.
Definition: TargetLowering.h:1784
void llvm::TargetLoweringBase::setLibcallName ( RTLIB::Libcall  Call,
const char *  Name 
)
inlineinherited

Rename the default libcall routine name for the specified libcall.

Definition at line 1420 of file TargetLowering.h.

1420  {
1421  LibcallRoutineNames[Call] = Name;
1422  }
llvm::TargetLoweringBase::LibcallRoutineNames
const char * LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL]
Stores the name each libcall.
Definition: TargetLowering.h:1777
void llvm::TargetLoweringBase::setLoadExtAction ( unsigned  ExtType,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified load with extension does not work with the specified type and indicate what to do about it.

Definition at line 1110 of file TargetLowering.h.

1111  {
1112  assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1113  "Table isn't big enough!");
1114  LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1115  }
Action
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::LoadExtActions
uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE]
Definition: TargetLowering.h:1603
void llvm::TargetLoweringBase::setMinFunctionAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's minimum function alignment (in log2(bytes))

Definition at line 1197 of file TargetLowering.h.

1197  {
1198  MinFunctionAlignment = Align;
1199  }
Align
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setMinimumJumpTableEntries ( int  Val)
inlineprotectedinherited

Indicate the number of blocks to generate jump tables rather than if sequence.

Definition at line 1006 of file TargetLowering.h.

1006  {
1007  MinimumJumpTableEntries = Val;
1008  }
llvm::TargetLoweringBase::MinimumJumpTableEntries
int MinimumJumpTableEntries
Number of blocks threshold to use jump tables.
Definition: TargetLowering.h:1512
void llvm::TargetLoweringBase::setMinStackArgumentAlignment ( unsigned  Align)
inlineprotectedinherited

Set the minimum stack alignment of an argument (in log2(bytes)).

Definition at line 1216 of file TargetLowering.h.

1216  {
1217  MinStackArgumentAlignment = Align;
1218  }
llvm::TargetLoweringBase::MinStackArgumentAlignment
unsigned MinStackArgumentAlignment
The minimum alignment that any argument on the stack needs to have.
Definition: TargetLowering.h:1537
Align
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setOperationAction ( unsigned  Op,
MVT  VT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified operation does not work with the specified type and indicate what to do about it.

Definition at line 1102 of file TargetLowering.h.

1103  {
1104  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1105  OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1106  }
Action
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::OpActions
uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END]
Definition: TargetLowering.h:1598
void llvm::TargetLoweringBase::setPow2DivIsCheap ( bool  isCheap = true)
inlineprotectedinherited

Tells the code generator that it shouldn't generate srl/add/sra for a signed divide by power of two, and let the target handle it.

Definition at line 1069 of file TargetLowering.h.

1069 { Pow2DivIsCheap = isCheap; }
void llvm::TargetLoweringBase::setPrefFunctionAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's preferred function alignment. This should be set if there is a performance benefit to higher-than-minimum alignment (in log2(bytes))

Definition at line 1204 of file TargetLowering.h.

1204  {
1205  PrefFunctionAlignment = Align;
1206  }
Align
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setPrefLoopAlignment ( unsigned  Align)
inlineprotectedinherited

Set the target's preferred loop alignment. Default alignment is zero, it means the target does not care about loop alignment. The alignment is specified in log2(bytes).

Definition at line 1211 of file TargetLowering.h.

1211  {
1212  PrefLoopAlignment = Align;
1213  }
llvm::TargetLoweringBase::PrefLoopAlignment
unsigned PrefLoopAlignment
The preferred loop alignment.
Definition: TargetLowering.h:1548
Align
static cl::opt< AlignMode > Align(cl::desc("Load/store alignment support"), cl::Hidden, cl::init(NoStrictAlign), cl::values(clEnumValN(StrictAlign,"aarch64-strict-align","Disallow all unaligned memory accesses"), clEnumValN(NoStrictAlign,"aarch64-no-strict-align","Allow unaligned memory accesses"), clEnumValEnd))
void llvm::TargetLoweringBase::setSchedulingPreference ( Sched::Preference  Pref)
inlineprotectedinherited

Specify the target scheduling preference.

Definition at line 983 of file TargetLowering.h.

983  {
984  SchedPreferenceInfo = Pref;
985  }
llvm::TargetLoweringBase::SchedPreferenceInfo
Sched::Preference SchedPreferenceInfo
Definition: TargetLowering.h:1528
void llvm::TargetLoweringBase::setSelectIsExpensive ( bool  isExpensive = true)
inlineprotectedinherited

Tells the code generator not to expand operations into sequences that use the select operations if possible.

Definition at line 1030 of file TargetLowering.h.

1030  {
1031  SelectIsExpensive = isExpensive;
1032  }
void llvm::TargetLoweringBase::setStackPointerRegisterToSaveRestore ( unsigned  R)
inlineprotectedinherited

If set to a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save and restore.

Definition at line 1012 of file TargetLowering.h.

1012  {
1013  StackPointerRegisterToSaveRestore = R;
1014  }
llvm::TargetLoweringBase::StackPointerRegisterToSaveRestore
unsigned StackPointerRegisterToSaveRestore
Definition: TargetLowering.h:1557
void llvm::TargetLoweringBase::setSupportJumpTables ( bool  Val)
inlineprotectedinherited

Indicate whether the target can generate code for jump tables.

Definition at line 1000 of file TargetLowering.h.

1000  {
1001  SupportJumpTables = Val;
1002  }
void llvm::TargetLoweringBase::setTargetDAGCombine ( ISD::NodeType  NT)
inlineprotectedinherited

Targets should invoke this method for each target independent node that they want to provide a custom DAG combiner for by implementing the PerformDAGCombine virtual method.

Definition at line 1180 of file TargetLowering.h.

1180  {
1181  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1182  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1183  }
llvm::TargetLoweringBase::TargetDAGCombineArray
unsigned char TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT]
Definition: TargetLowering.h:1765
llvm::array_lengthof
LLVM_CONSTEXPR size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:295
assert
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setTruncStoreAction ( MVT  ValVT,
MVT  MemVT,
LegalizeAction  Action 
)
inlineprotectedinherited

Indicate that the specified truncating store does not work with the specified type and indicate what to do about it.

Definition at line 1119 of file TargetLowering.h.

1120  {
1121  assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1122  "Table isn't big enough!");
1123  TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1124  }
llvm::TargetLoweringBase::TruncStoreActions
uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
Definition: TargetLowering.h:1607
Action
static cl::opt< ActionType > Action(cl::desc("Action to perform:"), cl::init(AC_Assemble), cl::values(clEnumValN(AC_AsLex,"as-lex","Lex tokens from a .s file"), clEnumValN(AC_Assemble,"assemble","Assemble a .s file (default)"), clEnumValN(AC_Disassemble,"disassemble","Disassemble strings of hex bytes"), clEnumValN(AC_MDisassemble,"mdis","Marked up disassembly of strings of hex bytes"), clEnumValEnd))
assert
assert(Globals.size() > 1)
void llvm::TargetLoweringBase::setUseUnderscoreLongJmp ( bool  Val)
inlineprotectedinherited

Indicate whether this target prefers to use _longjmp to implement llvm.longjmp or the version without _. Defaults to false.

Definition at line 995 of file TargetLowering.h.

995  {
996  UseUnderscoreLongJmp = Val;
997  }
void llvm::TargetLoweringBase::setUseUnderscoreSetJmp ( bool  Val)
inlineprotectedinherited

Indicate whether this target prefers to use _setjmp to implement llvm.setjmp or the version without _. Defaults to false.

Definition at line 989 of file TargetLowering.h.

989  {
990  UseUnderscoreSetJmp = Val;
991  }
bool X86TargetLowering::shouldConvertConstantLoadToIntImm ( const APInt &  Imm,
Type *  Ty 
) const
overridevirtual

Returns true if it is beneficial to convert a load of a constant to just the constant itself.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 3672 of file X86ISelLowering.cpp.

3673  {
3674  assert(Ty->isIntegerTy());
3675 
3676  unsigned BitSize = Ty->getPrimitiveSizeInBits();
3677  if (BitSize == 0 || BitSize > 64)
3678  return false;
3679  return true;
3680 }
assert
assert(Globals.size() > 1)
llvm::Type::isIntegerTy
bool isIntegerTy() const
Definition: Type.h:193
llvm::Type::getPrimitiveSizeInBits
unsigned getPrimitiveSizeInBits() const LLVM_READONLY
Definition: Type.cpp:117
virtual bool llvm::TargetLoweringBase::shouldExpandAtomicInIR ( Instruction *  Inst) const
inlinevirtualinherited

Return true if the given (atomic) instruction should be expanded by the IR-level AtomicExpandLoadLinked pass into a loop involving load-linked/store-conditional pairs. Atomic stores will be expanded in the same way as "atomic xchg" operations which ignore their output if needed.

Reimplemented in llvm::ARMTargetLowering, and llvm::AArch64TargetLowering.

Definition at line 948 of file TargetLowering.h.

948  {
949  return false;
950  }
virtual bool llvm::TargetLoweringBase::shouldExpandBuildVectorWithShuffles ( EVT  ,
unsigned  DefinedValues 
) const
inlinevirtualinherited

Reimplemented in llvm::PPCTargetLowering.

Definition at line 208 of file TargetLowering.h.

209  {
210  return DefinedValues < 3;
211  }
bool llvm::X86TargetLowering::ShouldShrinkFPConstant ( EVT  VT) const
inlineoverridevirtual

ShouldShrinkFPConstant - If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.

Reimplemented from llvm::TargetLoweringBase.

Definition at line 739 of file X86ISelLowering.h.

739  {
740  // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
741  // expensive than a straight movsd. On the other hand, it's important to
742  // shrink long double fp constant since fldt is very slow.
743  return !X86ScalarSSEf64 || VT == MVT::f80;
744  }
bool TargetLowering::SimplifyDemandedBits ( SDValue  Op,
const APInt &  DemandedMask,
APInt &  KnownZero,
APInt &  KnownOne,
TargetLoweringOpt &  TLO,
unsigned  Depth = 0 
) const
inherited

Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.

SimplifyDemandedBits - Look at Op. At this point, we know that only the DemandedMask bits of the result of Op are ever used downstream. If we can use this information to simplify Op, create a new simplified DAG node and return true, returning the original and new nodes in Old and New. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the DemandedMask.

Definition at line 372 of file TargetLowering.cpp.

377  {
378  unsigned BitWidth = DemandedMask.getBitWidth();
379  assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
380  "Mask size mismatches value type size!");
381  APInt NewMask = DemandedMask;
382  SDLoc dl(Op);
383 
384  // Don't know anything.
385  KnownZero = KnownOne = APInt(BitWidth, 0);
386 
387  // Other users may use these bits.
388  if (!Op.getNode()->hasOneUse()) {
389  if (Depth != 0) {
390  // If not at the root, Just compute the KnownZero/KnownOne bits to
391  // simplify things downstream.
392  TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
393  return false;
394  }
395  // If this is the root being simplified, allow it to have multiple uses,
396  // just set the NewMask to all bits.
397  NewMask = APInt::getAllOnesValue(BitWidth);
398  } else if (DemandedMask == 0) {
399  // Not demanding any bits from Op.
400  if (Op.getOpcode() != ISD::UNDEF)
401  return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
402  return false;
403  } else if (Depth == 6) { // Limit search depth.
404  return false;
405  }
406 
407  APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
408  switch (Op.getOpcode()) {
409  case ISD::Constant:
410  // We know all of the bits for a constant!
411  KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
412  KnownZero = ~KnownOne;
413  return false; // Don't fall through, will infinitely loop.
414  case ISD::AND:
415  // If the RHS is a constant, check to see if the LHS would be zero without
416  // using the bits from the RHS. Below, we use knowledge about the RHS to
417  // simplify the LHS, here we're using information from the LHS to simplify
418  // the RHS.
419  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
420  APInt LHSZero, LHSOne;
421  // Do not increment Depth here; that can cause an infinite loop.
422  TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
423  // If the LHS already has zeros where RHSC does, this and is dead.
424  if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
425  return TLO.CombineTo(Op, Op.getOperand(0));
426  // If any of the set bits in the RHS are known zero on the LHS, shrink
427  // the constant.
428  if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
429  return true;
430  }
431 
432  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
433  KnownOne, TLO, Depth+1))
434  return true;
435  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
436  if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
437  KnownZero2, KnownOne2, TLO, Depth+1))
438  return true;
439  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
440 
441  // If all of the demanded bits are known one on one side, return the other.
442  // These bits cannot contribute to the result of the 'and'.
443  if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
444  return TLO.CombineTo(Op, Op.getOperand(0));
445  if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
446  return TLO.CombineTo(Op, Op.getOperand(1));
447  // If all of the demanded bits in the inputs are known zeros, return zero.
448  if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
449  return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
450  // If the RHS is a constant, see if we can simplify it.
451  if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
452  return true;
453  // If the operation can be done in a smaller type, do so.
454  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
455  return true;
456 
457  // Output known-1 bits are only known if set in both the LHS & RHS.
458  KnownOne &= KnownOne2;
459  // Output known-0 are known to be clear if zero in either the LHS | RHS.
460  KnownZero |= KnownZero2;
461  break;
462  case ISD::OR:
463  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
464  KnownOne, TLO, Depth+1))
465  return true;
466  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
467  if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
468  KnownZero2, KnownOne2, TLO, Depth+1))
469  return true;
470  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
471 
472  // If all of the demanded bits are known zero on one side, return the other.
473  // These bits cannot contribute to the result of the 'or'.
474  if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
475  return TLO.CombineTo(Op, Op.getOperand(0));
476  if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
477  return TLO.CombineTo(Op, Op.getOperand(1));
478  // If all of the potentially set bits on one side are known to be set on
479  // the other side, just use the 'other' side.
480  if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
481  return TLO.CombineTo(Op, Op.getOperand(0));
482  if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
483  return TLO.CombineTo(Op, Op.getOperand(1));
484  // If the RHS is a constant, see if we can simplify it.
485  if (TLO.ShrinkDemandedConstant(Op, NewMask))
486  return true;
487  // If the operation can be done in a smaller type, do so.
488  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
489  return true;
490 
491  // Output known-0 bits are only known if clear in both the LHS & RHS.
492  KnownZero &= KnownZero2;
493  // Output known-1 are known to be set if set in either the LHS | RHS.
494  KnownOne |= KnownOne2;
495  break;
496  case ISD::XOR:
497  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
498  KnownOne, TLO, Depth+1))
499  return true;
500  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
501  if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
502  KnownOne2, TLO, Depth+1))
503  return true;
504  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
505 
506  // If all of the demanded bits are known zero on one side, return the other.
507  // These bits cannot contribute to the result of the 'xor'.
508  if ((KnownZero & NewMask) == NewMask)
509  return TLO.CombineTo(Op, Op.getOperand(0));
510  if ((KnownZero2 & NewMask) == NewMask)
511  return TLO.CombineTo(Op, Op.getOperand(1));
512  // If the operation can be done in a smaller type, do so.
513  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
514  return true;
515 
516  // If all of the unknown bits are known to be zero on one side or the other
517  // (but not both) turn this into an *inclusive* or.
518  // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
519  if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
520  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
521  Op.getOperand(0),
522  Op.getOperand(1)));
523 
524  // Output known-0 bits are known if clear or set in both the LHS & RHS.
525  KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
526  // Output known-1 are known to be set if set in only one of the LHS, RHS.
527  KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
528 
529  // If all of the demanded bits on one side are known, and all of the set
530  // bits on that side are also known to be set on the other side, turn this
531  // into an AND, as we know the bits will be cleared.
532  // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
533  // NB: it is okay if more bits are known than are requested
534  if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
535  if (KnownOne == KnownOne2) { // set bits are the same on both sides
536  EVT VT = Op.getValueType();
537  SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
538  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
539  Op.getOperand(0), ANDC));
540  }
541  }
542 
543  // If the RHS is a constant, see if we can simplify it.
544  // for XOR, we prefer to force bits to 1 if they will make a -1.
545  // if we can't force bits, try to shrink constant
546  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
547  APInt Expanded = C->getAPIntValue() | (~NewMask);
548  // if we can expand it to have all bits set, do it
549  if (Expanded.isAllOnesValue()) {
550  if (Expanded != C->getAPIntValue()) {
551  EVT VT = Op.getValueType();
552  SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
553  TLO.DAG.getConstant(Expanded, VT));
554  return TLO.CombineTo(Op, New);
555  }
556  // if it already has all the bits set, nothing to change
557  // but don't shrink either!
558  } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
559  return true;
560  }
561  }
562 
563  KnownZero = KnownZeroOut;
564  KnownOne = KnownOneOut;
565  break;
566  case ISD::SELECT:
567  if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
568  KnownOne, TLO, Depth+1))
569  return true;
570  if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
571  KnownOne2, TLO, Depth+1))
572  return true;
573  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
574  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
575 
576  // If the operands are constants, see if we can simplify them.
577  if (TLO.ShrinkDemandedConstant(Op, NewMask))
578  return true;
579 
580  // Only known if known in both the LHS and RHS.
581  KnownOne &= KnownOne2;
582  KnownZero &= KnownZero2;
583  break;
584  case ISD::SELECT_CC:
585  if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
586  KnownOne, TLO, Depth+1))
587  return true;
588  if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
589  KnownOne2, TLO, Depth+1))
590  return true;
591  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
592  assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
593 
594  // If the operands are constants, see if we can simplify them.
595  if (TLO.ShrinkDemandedConstant(Op, NewMask))
596  return true;
597 
598  // Only known if known in both the LHS and RHS.
599  KnownOne &= KnownOne2;
600  KnownZero &= KnownZero2;
601  break;
602  case ISD::SHL:
603  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
604  unsigned ShAmt = SA->getZExtValue();
605  SDValue InOp = Op.getOperand(0);
606 
607  // If the shift count is an invalid immediate, don't do anything.
608  if (ShAmt >= BitWidth)
609  break;
610 
611  // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
612  // single shift. We can do this if the bottom bits (which are shifted
613  // out) are never demanded.
614  if (InOp.getOpcode() == ISD::SRL &&
615  isa<ConstantSDNode>(InOp.getOperand(1))) {
616  if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
617  unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
618  unsigned Opc = ISD::SHL;
619  int Diff = ShAmt-C1;
620  if (Diff < 0) {
621  Diff = -Diff;
622  Opc = ISD::SRL;
623  }
624 
625  SDValue NewSA =
626  TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
627  EVT VT = Op.getValueType();
628  return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
629  InOp.getOperand(0), NewSA));
630  }
631  }
632 
633  if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
634  KnownZero, KnownOne, TLO, Depth+1))
635  return true;
636 
637  // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
638  // are not demanded. This will likely allow the anyext to be folded away.
639  if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
640  SDValue InnerOp = InOp.getNode()->getOperand(0);
641  EVT InnerVT = InnerOp.getValueType();
642  unsigned InnerBits = InnerVT.getSizeInBits();
643  if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
644  isTypeDesirableForOp(ISD::SHL, InnerVT)) {
645  EVT ShTy = getShiftAmountTy(InnerVT);
646  if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
647  ShTy = InnerVT;
648  SDValue NarrowShl =
649  TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
650  TLO.DAG.getConstant(ShAmt, ShTy));
651  return
652  TLO.CombineTo(Op,
653  TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
654  NarrowShl));
655  }
656  // Repeat the SHL optimization above in cases where an extension
657  // intervenes: (shl (anyext (shr x, c1)), c2) to
658  // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
659  // aren't demanded (as above) and that the shifted upper c1 bits of
660  // x aren't demanded.
661  if (InOp.hasOneUse() &&
662  InnerOp.getOpcode() == ISD::SRL &&
663  InnerOp.hasOneUse() &&
664  isa<ConstantSDNode>(InnerOp.getOperand(1))) {
665  uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
666  ->getZExtValue();
667  if (InnerShAmt < ShAmt &&
668  InnerShAmt < InnerBits &&
669  NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
670  NewMask.trunc(ShAmt) == 0) {
671  SDValue NewSA =
672  TLO.DAG.getConstant(ShAmt - InnerShAmt,
673  Op.getOperand(1).getValueType());
674  EVT VT = Op.getValueType();
675  SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
676  InnerOp.getOperand(0));
677  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
678  NewExt, NewSA));
679  }
680  }
681  }
682 
683  KnownZero <<= SA->getZExtValue();
684  KnownOne <<= SA->getZExtValue();
685  // low bits known zero.
686  KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
687  }
688  break;
689  case ISD::SRL:
690  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
691  EVT VT = Op.getValueType();
692  unsigned ShAmt = SA->getZExtValue();
693  unsigned VTSize = VT.getSizeInBits();
694  SDValue InOp = Op.getOperand(0);
695 
696  // If the shift count is an invalid immediate, don't do anything.
697  if (ShAmt >= BitWidth)
698  break;
699 
700  // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
701  // single shift. We can do this if the top bits (which are shifted out)
702  // are never demanded.
703  if (InOp.getOpcode() == ISD::SHL &&
704  isa<ConstantSDNode>(InOp.getOperand(1))) {
705  if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
706  unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
707  unsigned Opc = ISD::SRL;
708  int Diff = ShAmt-C1;
709  if (Diff < 0) {
710  Diff = -Diff;
711  Opc = ISD::SHL;
712  }
713 
714  SDValue NewSA =
715  TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
716  return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
717  InOp.getOperand(0), NewSA));
718  }
719  }
720 
721  // Compute the new bits that are at the top now.
722  if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
723  KnownZero, KnownOne, TLO, Depth+1))
724  return true;
725  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
726  KnownZero = KnownZero.lshr(ShAmt);
727  KnownOne = KnownOne.lshr(ShAmt);
728 
729  APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
730  KnownZero |= HighBits; // High bits known zero.
731  }
732  break;
733  case ISD::SRA:
734  // If this is an arithmetic shift right and only the low-bit is set, we can
735  // always convert this into a logical shr, even if the shift amount is
736  // variable. The low bit of the shift cannot be an input sign bit unless
737  // the shift amount is >= the size of the datatype, which is undefined.
738  if (NewMask == 1)
739  return TLO.CombineTo(Op,
740  TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
741  Op.getOperand(0), Op.getOperand(1)));
742 
743  if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
744  EVT VT = Op.getValueType();
745  unsigned ShAmt = SA->getZExtValue();
746 
747  // If the shift count is an invalid immediate, don't do anything.
748  if (ShAmt >= BitWidth)
749  break;
750 
751  APInt InDemandedMask = (NewMask << ShAmt);
752 
753  // If any of the demanded bits are produced by the sign extension, we also
754  // demand the input sign bit.
755  APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
756  if (HighBits.intersects(NewMask))
757  InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
758 
759  if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
760  KnownZero, KnownOne, TLO, Depth+1))
761  return true;
762  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
763  KnownZero = KnownZero.lshr(ShAmt);
764  KnownOne = KnownOne.lshr(ShAmt);
765 
766  // Handle the sign bit, adjusted to where it is now in the mask.
767  APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
768 
769  // If the input sign bit is known to be zero, or if none of the top bits
770  // are demanded, turn this into an unsigned shift right.
771  if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
772  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
773  Op.getOperand(0),
774  Op.getOperand(1)));
775 
776  int Log2 = NewMask.exactLogBase2();
777  if (Log2 >= 0) {
778  // The bit must come from the sign.
779  SDValue NewSA =
780  TLO.DAG.getConstant(BitWidth - 1 - Log2,
781  Op.getOperand(1).getValueType());
782  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
783  Op.getOperand(0), NewSA));
784  }
785 
786  if (KnownOne.intersects(SignBit))
787  // New bits are known one.
788  KnownOne |= HighBits;
789  }
790  break;
791  case ISD::SIGN_EXTEND_INREG: {
792  EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
793 
794  APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
795  // If we only care about the highest bit, don't bother shifting right.
796  if (MsbMask == DemandedMask) {
797  unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
798  SDValue InOp = Op.getOperand(0);
799 
800  // Compute the correct shift amount type, which must be getShiftAmountTy
801  // for scalar types after legalization.
802  EVT ShiftAmtTy = Op.getValueType();
803  if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
804  ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
805 
806  SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
807  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
808  Op.getValueType(), InOp, ShiftAmt));
809  }
810 
811  // Sign extension. Compute the demanded bits in the result that are not
812  // present in the input.
813  APInt NewBits =
814  APInt::getHighBitsSet(BitWidth,
815  BitWidth - ExVT.getScalarType().getSizeInBits());
816 
817  // If none of the extended bits are demanded, eliminate the sextinreg.
818  if ((NewBits & NewMask) == 0)
819  return TLO.CombineTo(Op, Op.getOperand(0));
820 
821  APInt InSignBit =
822  APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
823  APInt InputDemandedBits =
824  APInt::getLowBitsSet(BitWidth,
825  ExVT.getScalarType().getSizeInBits()) &
826  NewMask;
827 
828  // Since the sign extended bits are demanded, we know that the sign
829  // bit is demanded.
830  InputDemandedBits |= InSignBit;
831 
832  if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
833  KnownZero, KnownOne, TLO, Depth+1))
834  return true;
835  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
836 
837  // If the sign bit of the input is known set or clear, then we know the
838  // top bits of the result.
839 
840  // If the input sign bit is known zero, convert this into a zero extension.
841  if (KnownZero.intersects(InSignBit))
842  return TLO.CombineTo(Op,
843  TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
844 
845  if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
846  KnownOne |= NewBits;
847  KnownZero &= ~NewBits;
848  } else { // Input sign bit unknown
849  KnownZero &= ~NewBits;
850  KnownOne &= ~NewBits;
851  }
852  break;
853  }
854  case ISD::BUILD_PAIR: {
855  EVT HalfVT = Op.getOperand(0).getValueType();
856  unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
857 
858  APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
859  APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
860 
861  APInt KnownZeroLo, KnownOneLo;
862  APInt KnownZeroHi, KnownOneHi;
863 
864  if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
865  KnownOneLo, TLO, Depth + 1))
866  return true;
867 
868  if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
869  KnownOneHi, TLO, Depth + 1))
870  return true;
871 
872  KnownZero = KnownZeroLo.zext(BitWidth) |
873  KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
874 
875  KnownOne = KnownOneLo.zext(BitWidth) |
876  KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
877  break;
878  }
879  case ISD::ZERO_EXTEND: {
880  unsigned OperandBitWidth =
881  Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
882  APInt InMask = NewMask.trunc(OperandBitWidth);
883 
884  // If none of the top bits are demanded, convert this into an any_extend.
885  APInt NewBits =
886  APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
887  if (!NewBits.intersects(NewMask))
888  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
889  Op.getValueType(),
890  Op.getOperand(0)));
891 
892  if (SimplifyDemandedBits(Op.getOperand(0), InMask,
893  KnownZero, KnownOne, TLO, Depth+1))
894  return true;
895  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
896  KnownZero = KnownZero.zext(BitWidth);
897  KnownOne = KnownOne.zext(BitWidth);
898  KnownZero |= NewBits;
899  break;
900  }
901  case ISD::SIGN_EXTEND: {
902  EVT InVT = Op.getOperand(0).getValueType();
903  unsigned InBits = InVT.getScalarType().getSizeInBits();
904  APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
905  APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
906  APInt NewBits = ~InMask & NewMask;
907 
908  // If none of the top bits are demanded, convert this into an any_extend.
909  if (NewBits == 0)
910  return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
911  Op.getValueType(),
912  Op.getOperand(0)));
913 
914  // Since some of the sign extended bits are demanded, we know that the sign
915  // bit is demanded.
916  APInt InDemandedBits = InMask & NewMask;
917  InDemandedBits |= InSignBit;
918  InDemandedBits = InDemandedBits.trunc(InBits);
919 
920  if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
921  KnownOne, TLO, Depth+1))
922  return true;
923  KnownZero = KnownZero.zext(BitWidth);
924  KnownOne = KnownOne.zext(BitWidth);
925 
926  // If the sign bit is known zero, convert this to a zero extend.
927  if (KnownZero.intersects(InSignBit))
928  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
929  Op.getValueType(),
930  Op.getOperand(0)));
931 
932  // If the sign bit is known one, the top bits match.
933  if (KnownOne.intersects(InSignBit)) {
934  KnownOne |= NewBits;
935  assert((KnownZero & NewBits) == 0);
936  } else { // Otherwise, top bits aren't known.
937  assert((KnownOne & NewBits) == 0);
938  assert((KnownZero & NewBits) == 0);
939  }
940  break;
941  }
942  case ISD::ANY_EXTEND: {
943  unsigned OperandBitWidth =
944  Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
945  APInt InMask = NewMask.trunc(OperandBitWidth);
946  if (SimplifyDemandedBits(Op.getOperand(0), InMask,
947  KnownZero, KnownOne, TLO, Depth+1))
948  return true;
949  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
950  KnownZero = KnownZero.zext(BitWidth);
951  KnownOne = KnownOne.zext(BitWidth);
952  break;
953  }
954  case ISD::TRUNCATE: {
955  // Simplify the input, using demanded bit information, and compute the known
956  // zero/one bits live out.
957  unsigned OperandBitWidth =
958  Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
959  APInt TruncMask = NewMask.zext(OperandBitWidth);
960  if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
961  KnownZero, KnownOne, TLO, Depth+1))
962  return true;
963  KnownZero = KnownZero.trunc(BitWidth);
964  KnownOne = KnownOne.trunc(BitWidth);
965 
966  // If the input is only used by this truncate, see if we can shrink it based
967  // on the known demanded bits.
968  if (Op.getOperand(0).getNode()->hasOneUse()) {
969  SDValue In = Op.getOperand(0);
970  switch (In.getOpcode()) {
971  default: break;
972  case ISD::SRL:
973  // Shrink SRL by a constant if none of the high bits shifted in are
974  // demanded.
975  if (TLO.LegalTypes() &&
976  !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
977  // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
978  // undesirable.
979  break;
980  ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
981  if (!ShAmt)
982  break;
983  SDValue Shift = In.getOperand(1);
984  if (TLO.LegalTypes()) {
985  uint64_t ShVal = ShAmt->getZExtValue();
986  Shift =
987  TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
988  }
989 
990  APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
991  OperandBitWidth - BitWidth);
992  HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
993 
994  if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
995  // None of the shifted in bits are needed. Add a truncate of the
996  // shift input, then shift it.
997  SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
998  Op.getValueType(),
999  In.getOperand(0));
1000  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1001  Op.getValueType(),
1002  NewTrunc,
1003  Shift));
1004  }
1005  break;
1006  }
1007  }
1008 
1009  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1010  break;
1011  }
1012  case ISD::AssertZext: {
1013  // AssertZext demands all of the high bits, plus any of the low bits
1014  // demanded by its users.
1015  EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1016  APInt InMask = APInt::getLowBitsSet(BitWidth,
1017  VT.getSizeInBits());
1018  if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1019  KnownZero, KnownOne, TLO, Depth+1))
1020  return true;
1021  assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1022 
1023  KnownZero |= ~InMask & NewMask;
1024  break;
1025  }
1026  case ISD::BITCAST:
1027  // If this is an FP->Int bitcast and if the sign bit is the only
1028  // thing demanded, turn this into a FGETSIGN.
1029  if (!TLO.LegalOperations() &&
1030  !Op.getValueType().isVector() &&
1031  !Op.getOperand(0).getValueType().isVector() &&
1032  NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1033  Op.getOperand(0).getValueType().isFloatingPoint()) {
1034  bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1035  bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1036  if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1037  EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1038  // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1039  // place. We expect the SHL to be eliminated by other optimizations.
1040  SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1041  unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1042  if (!OpVTLegal && OpVTSizeInBits > 32)
1043  Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1044  unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1045  SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1046  return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1047  Op.getValueType(),
1048  Sign, ShAmt));
1049  }
1050  }
1051  break;
1052  case ISD::ADD:
1053  case ISD::MUL:
1054  case ISD::SUB: {
1055  // Add, Sub, and Mul don't demand any bits in positions beyond that
1056  // of the highest bit demanded of them.
1057  APInt LoMask = APInt::getLowBitsSet(BitWidth,
1058  BitWidth - NewMask.countLeadingZeros());
1059  if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1060  KnownOne2, TLO, Depth+1))
1061  return true;
1062  if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1063  KnownOne2, TLO, Depth+1))
1064  return true;
1065  // See if the operation should be performed at a smaller bit width.
1066  if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1067  return true;
1068  }
1069  // FALL THROUGH
1070  default:
1071  // Just use computeKnownBits to compute output bits.
1072  TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1073  break;
1074  }
1075 
1076  // If we know the value of all of the demanded bits, return this as a
1077  // constant.
1078  if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1079  return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1080 
1081  return false;
1082 }
llvm::APInt::getSignBit
static APInt getSignBit(unsigned BitWidth)
Get the SignBit for a specific bit width.
Definition: APInt.h:441
llvm::APInt::getAllOnesValue
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:448
llvm::SDNode::hasOneUse
bool hasOneUse() const
Definition: SelectionDAGNodes.h:438
llvm::SDValue::hasOneUse
bool hasOneUse() const
Definition: SelectionDAGNodes.h:910
llvm::APInt::getLowBitsSet
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:526
llvm::SDNode::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:401
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:592
llvm::TargetLowering::isTypeDesirableForOp
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Definition: TargetLowering.h:2068
llvm::TargetLowering::SimplifyDemandedBits
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const
Definition: TargetLowering.cpp:372
llvm::LibFunc::trunc
double trunc(double x);
Definition: TargetLibraryInfo.h:632
llvm::EVT::isVector
bool isVector() const
isVector - Return true if this is a vector value type.
Definition: ValueTypes.h:116
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy) const
Definition: TargetLoweringBase.cpp:860
llvm::APInt::lshr
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1128
llvm::EVT::getScalarType
EVT getScalarType() const
Definition: ValueTypes.h:211
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::APInt::shl
APInt LLVM_ATTRIBUTE_UNUSED_RESULT shl(unsigned shiftAmt) const
Left-shift function.
Definition: APInt.h:852
llvm::ISD::UNDEF
UNDEF - An undefined node.
Definition: ISDOpcodes.h:159
llvm::APInt::getHighBitsSet
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::EVT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:240
assert
assert(Globals.size() > 1)
llvm::APInt::intersects
bool intersects(const APInt &RHS) const
Definition: APInt.h:1140
llvm::APInt::trunc
APInt LLVM_ATTRIBUTE_UNUSED_RESULT trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:920
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
llvm::TargetLoweringBase::isOperationLegalOrCustom
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Definition: TargetLowering.h:489
llvm::APInt::getLoBits
APInt getLoBits(unsigned numBits) const
Compute an APInt containing numBits lowbits from this APInt.
Definition: APInt.cpp:677
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::isIntN
bool isIntN(unsigned N, int64_t x)
Definition: MathExtras.h:330
llvm::APInt::getHiBits
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
Definition: APInt.cpp:672
llvm::APInt::exactLogBase2
int32_t exactLogBase2() const
Definition: APInt.h:1534
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::dyn_cast
LLVM_ATTRIBUTE_UNUSED_RESULT std::enable_if< !is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:265
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
llvm::APInt::getBitsSet
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
Definition: APInt.h:493
llvm::APInt::isAllOnesValue
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:338
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::EVT::isFloatingPoint
bool isFloatingPoint() const
isFloatingPoint - Return true if this is a FP, or a vector FP type.
Definition: ValueTypes.h:106
llvm::EVT::isSimple
bool isSimple() const
Definition: ValueTypes.h:95
llvm::APInt::zext
APInt LLVM_ATTRIBUTE_UNUSED_RESULT zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:984
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
llvm::ConstantSDNode::getZExtValue
uint64_t getZExtValue() const
Definition: SelectionDAGNodes.h:1350
SDValue TargetLowering::SimplifySetCC ( EVT  VT,
SDValue  N0,
SDValue  N1,
ISD::CondCode  Cond,
bool  foldBooleans,
DAGCombinerInfo &  DCI,
SDLoc  dl 
) const
inherited

Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.

SimplifySetCC - Try to simplify a setcc built with the specified operands and cc. If it is unable to simplify it, return a null SDValue.

Definition at line 1206 of file TargetLowering.cpp.

1208  {
1209  SelectionDAG &DAG = DCI.DAG;
1210 
1211  // These setcc operations always fold.
1212  switch (Cond) {
1213  default: break;
1214  case ISD::SETFALSE:
1215  case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1216  case ISD::SETTRUE:
1217  case ISD::SETTRUE2: {
1218  TargetLowering::BooleanContent Cnt =
1219  getBooleanContents(N0->getValueType(0));
1220  return DAG.getConstant(
1221  Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, VT);
1222  }
1223  }
1224 
1225  // Ensure that the constant occurs on the RHS, and fold constant
1226  // comparisons.
1227  ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1228  if (isa<ConstantSDNode>(N0.getNode()) &&
1229  (DCI.isBeforeLegalizeOps() ||
1230  isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1231  return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1232 
1233  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1234  const APInt &C1 = N1C->getAPIntValue();
1235 
1236  // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1237  // equality comparison, then we're just comparing whether X itself is
1238  // zero.
1239  if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1240  N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1241  N0.getOperand(1).getOpcode() == ISD::Constant) {
1242  const APInt &ShAmt
1243  = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1244  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1245  ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1246  if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1247  // (srl (ctlz x), 5) == 0 -> X != 0
1248  // (srl (ctlz x), 5) != 1 -> X != 0
1249  Cond = ISD::SETNE;
1250  } else {
1251  // (srl (ctlz x), 5) != 0 -> X == 0
1252  // (srl (ctlz x), 5) == 1 -> X == 0
1253  Cond = ISD::SETEQ;
1254  }
1255  SDValue Zero = DAG.getConstant(0, N0.getValueType());
1256  return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1257  Zero, Cond);
1258  }
1259  }
1260 
1261  SDValue CTPOP = N0;
1262  // Look through truncs that don't change the value of a ctpop.
1263  if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1264  CTPOP = N0.getOperand(0);
1265 
1266  if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1267  (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1268  Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1269  EVT CTVT = CTPOP.getValueType();
1270  SDValue CTOp = CTPOP.getOperand(0);
1271 
1272  // (ctpop x) u< 2 -> (x & x-1) == 0
1273  // (ctpop x) u> 1 -> (x & x-1) != 0
1274  if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1275  SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1276  DAG.getConstant(1, CTVT));
1277  SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1278  ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1279  return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1280  }
1281 
1282  // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1283  }
1284 
1285  // (zext x) == C --> x == (trunc C)
1286  if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1287  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1288  unsigned MinBits = N0.getValueSizeInBits();
1289  SDValue PreZExt;
1290  if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1291  // ZExt
1292  MinBits = N0->getOperand(0).getValueSizeInBits();
1293  PreZExt = N0->getOperand(0);
1294  } else if (N0->getOpcode() == ISD::AND) {
1295  // DAGCombine turns costly ZExts into ANDs
1296  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1297  if ((C->getAPIntValue()+1).isPowerOf2()) {
1298  MinBits = C->getAPIntValue().countTrailingOnes();
1299  PreZExt = N0->getOperand(0);
1300  }
1301  } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1302  // ZEXTLOAD
1303  if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1304  MinBits = LN0->getMemoryVT().getSizeInBits();
1305  PreZExt = N0;
1306  }
1307  }
1308 
1309  // Make sure we're not losing bits from the constant.
1310  if (MinBits > 0 &&
1311  MinBits < C1.getBitWidth() && MinBits >= C1.getActiveBits()) {
1312  EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1313  if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1314  // Will get folded away.
1315  SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
1316  SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
1317  return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1318  }
1319  }
1320  }
1321 
1322  // If the LHS is '(and load, const)', the RHS is 0,
1323  // the test is for equality or unsigned, and all 1 bits of the const are
1324  // in the same partial word, see if we can shorten the load.
1325  if (DCI.isBeforeLegalize() &&
1326  !ISD::isSignedIntSetCC(Cond) &&
1327  N0.getOpcode() == ISD::AND && C1 == 0 &&
1328  N0.getNode()->hasOneUse() &&
1329  isa<LoadSDNode>(N0.getOperand(0)) &&
1330  N0.getOperand(0).getNode()->hasOneUse() &&
1331  isa<ConstantSDNode>(N0.getOperand(1))) {
1332  LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1333  APInt bestMask;
1334  unsigned bestWidth = 0, bestOffset = 0;
1335  if (!Lod->isVolatile() && Lod->isUnindexed()) {
1336  unsigned origWidth = N0.getValueType().getSizeInBits();
1337  unsigned maskWidth = origWidth;
1338  // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1339  // 8 bits, but have to be careful...
1340  if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1341  origWidth = Lod->getMemoryVT().getSizeInBits();
1342  const APInt &Mask =
1343  cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1344  for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1345  APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1346  for (unsigned offset=0; offset<origWidth/width; offset++) {
1347  if ((newMask & Mask) == Mask) {
1348  if (!getDataLayout()->isLittleEndian())
1349  bestOffset = (origWidth/width - offset - 1) * (width/8);
1350  else
1351  bestOffset = (uint64_t)offset * (width/8);
1352  bestMask = Mask.lshr(offset * (width/8) * 8);
1353  bestWidth = width;
1354  break;
1355  }
1356  newMask = newMask << width;
1357  }
1358  }
1359  }
1360  if (bestWidth) {
1361  EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1362  if (newVT.isRound()) {
1363  EVT PtrType = Lod->getOperand(1).getValueType();
1364  SDValue Ptr = Lod->getBasePtr();
1365  if (bestOffset != 0)
1366  Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1367  DAG.getConstant(bestOffset, PtrType));
1368  unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1369  SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1370  Lod->getPointerInfo().getWithOffset(bestOffset),
1371  false, false, false, NewAlign);
1372  return DAG.getSetCC(dl, VT,
1373  DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1374  DAG.getConstant(bestMask.trunc(bestWidth),
1375  newVT)),
1376  DAG.getConstant(0LL, newVT), Cond);
1377  }
1378  }
1379  }
1380 
1381  // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1382  if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1383  unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1384 
1385  // If the comparison constant has bits in the upper part, the
1386  // zero-extended value could never match.
1387  if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1388  C1.getBitWidth() - InSize))) {
1389  switch (Cond) {
1390  case ISD::SETUGT:
1391  case ISD::SETUGE:
1392  case ISD::SETEQ: return DAG.getConstant(0, VT);
1393  case ISD::SETULT:
1394  case ISD::SETULE:
1395  case ISD::SETNE: return DAG.getConstant(1, VT);
1396  case ISD::SETGT:
1397  case ISD::SETGE:
1398  // True if the sign bit of C1 is set.
1399  return DAG.getConstant(C1.isNegative(), VT);
1400  case ISD::SETLT:
1401  case ISD::SETLE:
1402  // True if the sign bit of C1 isn't set.
1403  return DAG.getConstant(C1.isNonNegative(), VT);
1404  default:
1405  break;
1406  }
1407  }
1408 
1409  // Otherwise, we can perform the comparison with the low bits.
1410  switch (Cond) {
1411  case ISD::SETEQ:
1412  case ISD::SETNE:
1413  case ISD::SETUGT:
1414  case ISD::SETUGE:
1415  case ISD::SETULT:
1416  case ISD::SETULE: {
1417  EVT newVT = N0.getOperand(0).getValueType();
1418  if (DCI.isBeforeLegalizeOps() ||
1419  (isOperationLegal(ISD::SETCC, newVT) &&
1420  getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1421  EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
1422  SDValue NewConst = DAG.getConstant(C1.trunc(InSize), newVT);
1423 
1424  SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1425  NewConst, Cond);
1426  return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1427  }
1428  break;
1429  }
1430  default:
1431  break; // todo, be more careful with signed comparisons
1432  }
1433  } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1434  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1435  EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1436  unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1437  EVT ExtDstTy = N0.getValueType();
1438  unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1439 
1440  // If the constant doesn't fit into the number of bits for the source of
1441  // the sign extension, it is impossible for both sides to be equal.
1442  if (C1.getMinSignedBits() > ExtSrcTyBits)
1443  return DAG.getConstant(Cond == ISD::SETNE, VT);
1444 
1445  SDValue ZextOp;
1446  EVT Op0Ty = N0.getOperand(0).getValueType();
1447  if (Op0Ty == ExtSrcTy) {
1448  ZextOp = N0.getOperand(0);
1449  } else {
1450  APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1451  ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1452  DAG.getConstant(Imm, Op0Ty));
1453  }
1454  if (!DCI.isCalledByLegalizer())
1455  DCI.AddToWorklist(ZextOp.getNode());
1456  // Otherwise, make this a use of a zext.
1457  return DAG.getSetCC(dl, VT, ZextOp,
1458  DAG.getConstant(C1 & APInt::getLowBitsSet(
1459  ExtDstTyBits,
1460  ExtSrcTyBits),
1461  ExtDstTy),
1462  Cond);
1463  } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1464  (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1465  // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1466  if (N0.getOpcode() == ISD::SETCC &&
1467  isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1468  bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1469  if (TrueWhenTrue)
1470  return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1471  // Invert the condition.
1472  ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1473  CC = ISD::getSetCCInverse(CC,
1474  N0.getOperand(0).getValueType().isInteger());
1475  if (DCI.isBeforeLegalizeOps() ||
1476  isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1477  return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1478  }
1479 
1480  if ((N0.getOpcode() == ISD::XOR ||
1481  (N0.getOpcode() == ISD::AND &&
1482  N0.getOperand(0).getOpcode() == ISD::XOR &&
1483  N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1484  isa<ConstantSDNode>(N0.getOperand(1)) &&
1485  cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1486  // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1487  // can only do this if the top bits are known zero.
1488  unsigned BitWidth = N0.getValueSizeInBits();
1489  if (DAG.MaskedValueIsZero(N0,
1490  APInt::getHighBitsSet(BitWidth,
1491  BitWidth-1))) {
1492  // Okay, get the un-inverted input value.
1493  SDValue Val;
1494  if (N0.getOpcode() == ISD::XOR)
1495  Val = N0.getOperand(0);
1496  else {
1497  assert(N0.getOpcode() == ISD::AND &&
1498  N0.getOperand(0).getOpcode() == ISD::XOR);
1499  // ((X^1)&1)^1 -> X & 1
1500  Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1501  N0.getOperand(0).getOperand(0),
1502  N0.getOperand(1));
1503  }
1504 
1505  return DAG.getSetCC(dl, VT, Val, N1,
1506  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1507  }
1508  } else if (N1C->getAPIntValue() == 1 &&
1509  (VT == MVT::i1 ||
1510  getBooleanContents(N0->getValueType(0)) ==
1511  ZeroOrOneBooleanContent)) {
1512  SDValue Op0 = N0;
1513  if (Op0.getOpcode() == ISD::TRUNCATE)
1514  Op0 = Op0.getOperand(0);
1515 
1516  if ((Op0.getOpcode() == ISD::XOR) &&
1517  Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1518  Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1519  // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1520  Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1521  return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1522  Cond);
1523  }
1524  if (Op0.getOpcode() == ISD::AND &&
1525  isa<ConstantSDNode>(Op0.getOperand(1)) &&
1526  cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1527  // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1528  if (Op0.getValueType().bitsGT(VT))
1529  Op0 = DAG.getNode(ISD::AND, dl, VT,
1530  DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1531  DAG.getConstant(1, VT));
1532  else if (Op0.getValueType().bitsLT(VT))
1533  Op0 = DAG.getNode(ISD::AND, dl, VT,
1534  DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1535  DAG.getConstant(1, VT));
1536 
1537  return DAG.getSetCC(dl, VT, Op0,
1538  DAG.getConstant(0, Op0.getValueType()),
1539  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1540  }
1541  if (Op0.getOpcode() == ISD::AssertZext &&
1542  cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1543  return DAG.getSetCC(dl, VT, Op0,
1544  DAG.getConstant(0, Op0.getValueType()),
1545  Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1546  }
1547  }
1548 
1549  APInt MinVal, MaxVal;
1550  unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1551  if (ISD::isSignedIntSetCC(Cond)) {
1552  MinVal = APInt::getSignedMinValue(OperandBitSize);
1553  MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1554  } else {
1555  MinVal = APInt::getMinValue(OperandBitSize);
1556  MaxVal = APInt::getMaxValue(OperandBitSize);
1557  }
1558 
1559  // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1560  if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1561  if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1562  // X >= C0 --> X > (C0 - 1)
1563  APInt C = C1 - 1;
1564  ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1565  if ((DCI.isBeforeLegalizeOps() ||
1566  isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1567  (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1568  isLegalICmpImmediate(C.getSExtValue())))) {
1569  return DAG.getSetCC(dl, VT, N0,
1570  DAG.getConstant(C, N1.getValueType()),
1571  NewCC);
1572  }
1573  }
1574 
1575  if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1576  if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1577  // X <= C0 --> X < (C0 + 1)
1578  APInt C = C1 + 1;
1579  ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1580  if ((DCI.isBeforeLegalizeOps() ||
1581  isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1582  (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1583  isLegalICmpImmediate(C.getSExtValue())))) {
1584  return DAG.getSetCC(dl, VT, N0,
1585  DAG.getConstant(C, N1.getValueType()),
1586  NewCC);
1587  }
1588  }
1589 
1590  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1591  return DAG.getConstant(0, VT); // X < MIN --> false
1592  if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1593  return DAG.getConstant(1, VT); // X >= MIN --> true
1594  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1595  return DAG.getConstant(0, VT); // X > MAX --> false
1596  if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1597  return DAG.getConstant(1, VT); // X <= MAX --> true
1598 
1599  // Canonicalize setgt X, Min --> setne X, Min
1600  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1601  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1602  // Canonicalize setlt X, Max --> setne X, Max
1603  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1604  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1605 
1606  // If we have setult X, 1, turn it into seteq X, 0
1607  if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1608  return DAG.getSetCC(dl, VT, N0,
1609  DAG.getConstant(MinVal, N0.getValueType()),
1610  ISD::SETEQ);
1611  // If we have setugt X, Max-1, turn it into seteq X, Max
1612  if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1613  return DAG.getSetCC(dl, VT, N0,
1614  DAG.getConstant(MaxVal, N0.getValueType()),
1615  ISD::SETEQ);
1616 
1617  // If we have "setcc X, C0", check to see if we can shrink the immediate
1618  // by changing cc.
1619 
1620  // SETUGT X, SINTMAX -> SETLT X, 0
1621  if (Cond == ISD::SETUGT &&
1622  C1 == APInt::getSignedMaxValue(OperandBitSize))
1623  return DAG.getSetCC(dl, VT, N0,
1624  DAG.getConstant(0, N1.getValueType()),
1625  ISD::SETLT);
1626 
1627  // SETULT X, SINTMIN -> SETGT X, -1
1628  if (Cond == ISD::SETULT &&
1629  C1 == APInt::getSignedMinValue(OperandBitSize)) {
1630  SDValue ConstMinusOne =
1631  DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1632  N1.getValueType());
1633  return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1634  }
1635 
1636  // Fold bit comparisons when we can.
1637  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1638  (VT == N0.getValueType() ||
1639  (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1640  N0.getOpcode() == ISD::AND)
1641  if (ConstantSDNode *AndRHS =
1642  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1643  EVT ShiftTy = DCI.isBeforeLegalize() ?
1644  getPointerTy() : getShiftAmountTy(N0.getValueType());
1645  if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1646  // Perform the xform if the AND RHS is a single bit.
1647  if (AndRHS->getAPIntValue().isPowerOf2()) {
1648  return DAG.getNode(ISD::TRUNCATE, dl, VT,
1649  DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1650  DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
1651  }
1652  } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1653  // (X & 8) == 8 --> (X & 8) >> 3
1654  // Perform the xform if C1 is a single bit.
1655  if (C1.isPowerOf2()) {
1656  return DAG.getNode(ISD::TRUNCATE, dl, VT,
1657  DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1658  DAG.getConstant(C1.logBase2(), ShiftTy)));
1659  }
1660  }
1661  }
1662 
1663  if (C1.getMinSignedBits() <= 64 &&
1664  !isLegalICmpImmediate(C1.getSExtValue())) {
1665  // (X & -256) == 256 -> (X >> 8) == 1
1666  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1667  N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1668  if (ConstantSDNode *AndRHS =
1669  dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1670  const APInt &AndRHSC = AndRHS->getAPIntValue();
1671  if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1672  unsigned ShiftBits = AndRHSC.countTrailingZeros();
1673  EVT ShiftTy = DCI.isBeforeLegalize() ?
1674  getPointerTy() : getShiftAmountTy(N0.getValueType());
1675  EVT CmpTy = N0.getValueType();
1676  SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1677  DAG.getConstant(ShiftBits, ShiftTy));
1678  SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
1679  return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1680  }
1681  }
1682  } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1683  Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1684  bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1685  // X < 0x100000000 -> (X >> 32) < 1
1686  // X >= 0x100000000 -> (X >> 32) >= 1
1687  // X <= 0x0ffffffff -> (X >> 32) < 1
1688  // X > 0x0ffffffff -> (X >> 32) >= 1
1689  unsigned ShiftBits;
1690  APInt NewC = C1;
1691  ISD::CondCode NewCond = Cond;
1692  if (AdjOne) {
1693  ShiftBits = C1.countTrailingOnes();
1694  NewC = NewC + 1;
1695  NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1696  } else {
1697  ShiftBits = C1.countTrailingZeros();
1698  }
1699  NewC = NewC.lshr(ShiftBits);
1700  if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
1701  EVT ShiftTy = DCI.isBeforeLegalize() ?
1702  getPointerTy() : getShiftAmountTy(N0.getValueType());
1703  EVT CmpTy = N0.getValueType();
1704  SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1705  DAG.getConstant(ShiftBits, ShiftTy));
1706  SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
1707  return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1708  }
1709  }
1710  }
1711  }
1712 
1713  if (isa<ConstantFPSDNode>(N0.getNode())) {
1714  // Constant fold or commute setcc.
1715  SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1716  if (O.getNode()) return O;
1717  } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1718  // If the RHS of an FP comparison is a constant, simplify it away in
1719  // some cases.
1720  if (CFP->getValueAPF().isNaN()) {
1721  // If an operand is known to be a nan, we can fold it.
1722  switch (ISD::getUnorderedFlavor(Cond)) {
1723  default: llvm_unreachable("Unknown flavor!");
1724  case 0: // Known false.
1725  return DAG.getConstant(0, VT);
1726  case 1: // Known true.
1727  return DAG.getConstant(1, VT);
1728  case 2: // Undefined.
1729  return DAG.getUNDEF(VT);
1730  }
1731  }
1732 
1733  // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1734  // constant if knowing that the operand is non-nan is enough. We prefer to
1735  // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1736  // materialize 0.0.
1737  if (Cond == ISD::SETO || Cond == ISD::SETUO)
1738  return DAG.getSetCC(dl, VT, N0, N0, Cond);
1739 
1740  // If the condition is not legal, see if we can find an equivalent one
1741  // which is legal.
1742  if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1743  // If the comparison was an awkward floating-point == or != and one of
1744  // the comparison operands is infinity or negative infinity, convert the
1745  // condition to a less-awkward <= or >=.
1746  if (CFP->getValueAPF().isInfinity()) {
1747  if (CFP->getValueAPF().isNegative()) {
1748  if (Cond == ISD::SETOEQ &&
1749  isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1750  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1751  if (Cond == ISD::SETUEQ &&
1752  isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1753  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1754  if (Cond == ISD::SETUNE &&
1755  isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1756  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1757  if (Cond == ISD::SETONE &&
1758  isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1759  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1760  } else {
1761  if (Cond == ISD::SETOEQ &&
1762  isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1763  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1764  if (Cond == ISD::SETUEQ &&
1765  isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1766  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1767  if (Cond == ISD::SETUNE &&
1768  isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1769  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1770  if (Cond == ISD::SETONE &&
1771  isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1772  return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1773  }
1774  }
1775  }
1776  }
1777 
1778  if (N0 == N1) {
1779  // The sext(setcc()) => setcc() optimization relies on the appropriate
1780  // constant being emitted.
1781  uint64_t EqVal = 0;
1782  switch (getBooleanContents(N0.getValueType())) {
1783  case UndefinedBooleanContent:
1784  case ZeroOrOneBooleanContent:
1785  EqVal = ISD::isTrueWhenEqual(Cond);
1786  break;
1787  case ZeroOrNegativeOneBooleanContent:
1788  EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1789  break;
1790  }
1791 
1792  // We can always fold X == X for integer setcc's.
1793  if (N0.getValueType().isInteger()) {
1794  return DAG.getConstant(EqVal, VT);
1795  }
1796  unsigned UOF = ISD::getUnorderedFlavor(Cond);
1797  if (UOF == 2) // FP operators that are undefined on NaNs.
1798  return DAG.getConstant(EqVal, VT);
1799  if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1800  return DAG.getConstant(EqVal, VT);
1801  // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1802  // if it is not already.
1803  ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1804  if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1805  getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1806  return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1807  }
1808 
1809  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1810  N0.getValueType().isInteger()) {
1811  if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1812  N0.getOpcode() == ISD::XOR) {
1813  // Simplify (X+Y) == (X+Z) --> Y == Z
1814  if (N0.getOpcode() == N1.getOpcode()) {
1815  if (N0.getOperand(0) == N1.getOperand(0))
1816  return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1817  if (N0.getOperand(1) == N1.getOperand(1))
1818  return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1819  if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1820  // If X op Y == Y op X, try other combinations.
1821  if (N0.getOperand(0) == N1.getOperand(1))
1822  return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1823  Cond);
1824  if (N0.getOperand(1) == N1.getOperand(0))
1825  return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1826  Cond);
1827  }
1828  }
1829 
1830  // If RHS is a legal immediate value for a compare instruction, we need
1831  // to be careful about increasing register pressure needlessly.
1832  bool LegalRHSImm = false;
1833 
1834  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1835  if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1836  // Turn (X+C1) == C2 --> X == C2-C1
1837  if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1838  return DAG.getSetCC(dl, VT, N0.getOperand(0),
1839  DAG.getConstant(RHSC->getAPIntValue()-
1840  LHSR->getAPIntValue(),
1841  N0.getValueType()), Cond);
1842  }
1843 
1844  // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1845  if (N0.getOpcode() == ISD::XOR)
1846  // If we know that all of the inverted bits are zero, don't bother
1847  // performing the inversion.
1848  if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1849  return
1850  DAG.getSetCC(dl, VT, N0.getOperand(0),
1851  DAG.getConstant(LHSR->getAPIntValue() ^
1852  RHSC->getAPIntValue(),
1853  N0.getValueType()),
1854  Cond);
1855  }
1856 
1857  // Turn (C1-X) == C2 --> X == C1-C2
1858  if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1859  if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1860  return
1861  DAG.getSetCC(dl, VT, N0.getOperand(1),
1862  DAG.getConstant(SUBC->getAPIntValue() -
1863  RHSC->getAPIntValue(),
1864  N0.getValueType()),
1865  Cond);
1866  }
1867  }
1868 
1869  // Could RHSC fold directly into a compare?
1870  if (RHSC->getValueType(0).getSizeInBits() <= 64)
1871  LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1872  }
1873 
1874  // Simplify (X+Z) == X --> Z == 0
1875  // Don't do this if X is an immediate that can fold into a cmp
1876  // instruction and X+Z has other uses. It could be an induction variable
1877  // chain, and the transform would increase register pressure.
1878  if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1879  if (N0.getOperand(0) == N1)
1880  return DAG.getSetCC(dl, VT, N0.getOperand(1),
1881  DAG.getConstant(0, N0.getValueType()), Cond);
1882  if (N0.getOperand(1) == N1) {
1883  if (DAG.isCommutativeBinOp(N0.getOpcode()))
1884  return DAG.getSetCC(dl, VT, N0.getOperand(0),
1885  DAG.getConstant(0, N0.getValueType()), Cond);
1886  if (N0.getNode()->hasOneUse()) {
1887  assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1888  // (Z-X) == X --> Z == X<<1
1889  SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1890  DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
1891  if (!DCI.isCalledByLegalizer())
1892  DCI.AddToWorklist(SH.getNode());
1893  return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1894  }
1895  }
1896  }
1897  }
1898 
1899  if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1900  N1.getOpcode() == ISD::XOR) {
1901  // Simplify X == (X+Z) --> Z == 0
1902  if (N1.getOperand(0) == N0)
1903  return DAG.getSetCC(dl, VT, N1.getOperand(1),
1904  DAG.getConstant(0, N1.getValueType()), Cond);
1905  if (N1.getOperand(1) == N0) {
1906  if (DAG.isCommutativeBinOp(N1.getOpcode()))
1907  return DAG.getSetCC(dl, VT, N1.getOperand(0),
1908  DAG.getConstant(0, N1.getValueType()), Cond);
1909  if (N1.getNode()->hasOneUse()) {
1910  assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1911  // X == (Z-X) --> X<<1 == Z
1912  SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1913  DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
1914  if (!DCI.isCalledByLegalizer())
1915  DCI.AddToWorklist(SH.getNode());
1916  return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1917  }
1918  }
1919  }
1920 
1921  // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1922  // Note that where y is variable and is known to have at most
1923  // one bit set (for example, if it is z&1) we cannot do this;
1924  // the expressions are not equivalent when y==0.
1925  if (N0.getOpcode() == ISD::AND)
1926  if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1927  if (ValueHasExactlyOneBitSet(N1, DAG)) {
1928  Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1929  if (DCI.isBeforeLegalizeOps() ||
1930  isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1931  SDValue Zero = DAG.getConstant(0, N1.getValueType());
1932  return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1933  }
1934  }
1935  }
1936  if (N1.getOpcode() == ISD::AND)
1937  if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1938  if (ValueHasExactlyOneBitSet(N0, DAG)) {
1939  Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1940  if (DCI.isBeforeLegalizeOps() ||
1941  isCondCodeLegal(Cond, N1.getSimpleValueType())) {
1942  SDValue Zero = DAG.getConstant(0, N0.getValueType());
1943  return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1944  }
1945  }
1946  }
1947  }
1948 
1949  // Fold away ALL boolean setcc's.
1950  SDValue Temp;
1951  if (N0.getValueType() == MVT::i1 && foldBooleans) {
1952  switch (Cond) {
1953  default: llvm_unreachable("Unknown integer setcc!");
1954  case ISD::SETEQ: // X == Y -> ~(X^Y)
1955  Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1956  N0 = DAG.getNOT(dl, Temp, MVT::i1);
1957  if (!DCI.isCalledByLegalizer())
1958  DCI.AddToWorklist(Temp.getNode());
1959  break;
1960  case ISD::SETNE: // X != Y --> (X^Y)
1961  N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1962  break;
1963  case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1964  case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1965  Temp = DAG.getNOT(dl, N0, MVT::i1);
1966  N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1967  if (!DCI.isCalledByLegalizer())
1968  DCI.AddToWorklist(Temp.getNode());
1969  break;
1970  case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1971  case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1972  Temp = DAG.getNOT(dl, N1, MVT::i1);
1973  N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1974  if (!DCI.isCalledByLegalizer())
1975  DCI.AddToWorklist(Temp.getNode());
1976  break;
1977  case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
1978  case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1979  Temp = DAG.getNOT(dl, N0, MVT::i1);
1980  N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1981  if (!DCI.isCalledByLegalizer())
1982  DCI.AddToWorklist(Temp.getNode());
1983  break;
1984  case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
1985  case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
1986  Temp = DAG.getNOT(dl, N1, MVT::i1);
1987  N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1988  break;
1989  }
1990  if (VT != MVT::i1) {
1991  if (!DCI.isCalledByLegalizer())
1992  DCI.AddToWorklist(N0.getNode());
1993  // FIXME: If running after legalize, we probably can't do this.
1994  N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
1995  }
1996  return N0;
1997  }
1998 
1999  // Could not fold it.
2000  return SDValue();
2001 }
llvm::SDValue::getSimpleValueType
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
Definition: SelectionDAGNodes.h:162
llvm::Log2_32_Ceil
unsigned Log2_32_Ceil(uint32_t Value)
Definition: MathExtras.h:465
llvm::APInt::getAllOnesValue
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:448
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::SelectionDAG::getBoolExtOrTrunc
SDValue getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, EVT OpVT)
Definition: SelectionDAG.cpp:1015
llvm::SDNode::hasOneUse
bool hasOneUse() const
Definition: SelectionDAGNodes.h:438
llvm::SDValue::hasOneUse
bool hasOneUse() const
Definition: SelectionDAGNodes.h:910
llvm::APInt::getLowBitsSet
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:526
llvm::LSBaseSDNode::isUnindexed
bool isUnindexed() const
isUnindexed - Return true if this is NOT a pre/post inc/dec load/store.
Definition: SelectionDAGNodes.h:1829
llvm::TargetLoweringBase::isLegalICmpImmediate
virtual bool isLegalICmpImmediate(int64_t) const
Definition: TargetLowering.h:1280
llvm::SDValue::getValueSizeInBits
unsigned getValueSizeInBits() const
Definition: SelectionDAGNodes.h:168
llvm::SDNode::getOperand
const SDValue & getOperand(unsigned Num) const
Definition: SelectionDAGNodes.h:592
llvm::SelectionDAG::isCommutativeBinOp
static bool isCommutativeBinOp(unsigned Opcode)
Definition: SelectionDAG.h:1024
llvm::ISD::isTrueWhenEqual
bool isTrueWhenEqual(CondCode Cond)
Definition: ISDOpcodes.h:809
llvm::LoadSDNode::getBasePtr
const SDValue & getBasePtr() const
Definition: SelectionDAGNodes.h:1858
llvm::TargetLowering::isTypeDesirableForOp
virtual bool isTypeDesirableForOp(unsigned, EVT VT) const
Definition: TargetLowering.h:2068
llvm::APInt::getSignedMaxValue
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
Definition: APInt.h:421
llvm::EVT::bitsLT
bool bitsLT(EVT VT) const
bitsLT - Return true if this has less bits than VT.
Definition: ValueTypes.h:190
llvm::TargetLoweringBase::getValueType
EVT getValueType(Type *Ty, bool AllowUnknown=false) const
Definition: TargetLowering.h:638
llvm::TargetLoweringBase::getShiftAmountTy
EVT getShiftAmountTy(EVT LHSTy) const
Definition: TargetLoweringBase.cpp:860
llvm::TargetLoweringBase::isLittleEndian
bool isLittleEndian() const
Definition: TargetLowering.h:154
llvm::EVT::isRound
bool isRound() const
isRound - Return true if the size is a power-of-two number of bytes.
Definition: ValueTypes.h:166
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::SDNode::getValueType
EVT getValueType(unsigned ResNo) const
Definition: SelectionDAGNodes.h:648
llvm::APInt::lshr
APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.cpp:1128
llvm::TargetLoweringBase::getSetCCResultType
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const
Definition: TargetLoweringBase.cpp:1209
llvm::MachinePointerInfo::getWithOffset
MachinePointerInfo getWithOffset(int64_t O) const
Definition: MachineMemOperand.h:50
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(uint32_t=0) const
Definition: TargetLoweringBase.cpp:843
llvm::ISD::ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:181
llvm::SelectionDAG::getUNDEF
SDValue getUNDEF(EVT VT)
getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:625
llvm::MemSDNode::getMemoryVT
EVT getMemoryVT() const
getMemoryVT - Return the type of the in-memory value.
Definition: SelectionDAGNodes.h:1098
llvm::ISD::isSignedIntSetCC
bool isSignedIntSetCC(CondCode Code)
Definition: ISDOpcodes.h:796
llvm::EVT::bitsLE
bool bitsLE(EVT VT) const
bitsLE - Return true if this has no more bits than VT.
Definition: ValueTypes.h:196
llvm::APInt::getHighBitsSet
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:508
llvm::SDValue::getNode
SDNode * getNode() const
get the SDNode which holds the desired result
Definition: SelectionDAGNodes.h:130
llvm::TargetLoweringBase::isTypeLegal
bool isTypeLegal(EVT VT) const
Definition: TargetLowering.h:341
assert
assert(Globals.size() > 1)
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889
ValueHasExactlyOneBitSet
static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG)
Definition: TargetLowering.cpp:1120
llvm::APInt::getSExtValue
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1314
llvm::TargetLoweringBase::isOperationLegal
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
Definition: TargetLowering.h:512
llvm::TargetLoweringBase::getDataLayout
const DataLayout * getDataLayout() const
Definition: TargetLowering.h:150
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1248
llvm::SDValue::getOpcode
unsigned getOpcode() const
Definition: SelectionDAGNodes.h:880
llvm::ISD::getUnorderedFlavor
unsigned getUnorderedFlavor(CondCode Cond)
Definition: ISDOpcodes.h:817
llvm::ISD::getSetCCSwappedOperands
CondCode getSetCCSwappedOperands(CondCode Operation)
Definition: SelectionDAG.cpp:253
llvm::MemSDNode::isVolatile
bool isVolatile() const
Definition: SelectionDAGNodes.h:1077
llvm::SelectionDAG::MaskedValueIsZero
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Definition: SelectionDAG.cpp:1934
llvm::TargetLoweringBase::getBooleanContents
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
Definition: TargetLowering.h:290
llvm::MemSDNode::getPointerInfo
const MachinePointerInfo & getPointerInfo() const
Definition: SelectionDAGNodes.h:1104
llvm::EVT::bitsGT
bool bitsGT(EVT VT) const
bitsGT - Return true if this has more bits than VT.
Definition: ValueTypes.h:178
llvm::APInt::countTrailingZeros
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.cpp:737
llvm::SelectionDAG::getNOT
SDValue getNOT(SDLoc DL, SDValue Val, EVT VT)
getNOT - Create a bitwise NOT operation as (XOR Val, -1).
Definition: SelectionDAG.cpp:1068
llvm::MemSDNode::getChain
const SDValue & getChain() const
Definition: SelectionDAGNodes.h:1121
llvm::APInt::getMinValue
static APInt getMinValue(unsigned numBits)
Gets minimum unsigned value of APInt for a specific bit width.
Definition: APInt.h:428
llvm::ISD::getSetCCInverse
CondCode getSetCCInverse(CondCode Operation, bool isInteger)
Definition: SelectionDAG.cpp:265
llvm::Log2_32
unsigned Log2_32(uint32_t Value)
Definition: MathExtras.h:452
llvm::LoadSDNode::getExtensionType
ISD::LoadExtType getExtensionType() const
Definition: SelectionDAGNodes.h:1854
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::ISD::ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:362
llvm::SelectionDAG::getLoad
SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const MDNode *TBAAInfo=nullptr, const MDNode *Ranges=nullptr)
Definition: SelectionDAG.cpp:4762
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::ISD::ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:365
llvm::APInt::getMaxValue
static APInt getMaxValue(unsigned numBits)
Gets maximum unsigned value of APInt for specific bit width.
Definition: APInt.h:416
llvm::APIntOps::And
APInt And(const APInt &LHS, const APInt &RHS)
Bitwise AND function for APInt.
Definition: APInt.h:1865
llvm::MinAlign
uint64_t MinAlign(uint64_t A, uint64_t B)
Definition: MathExtras.h:544
llvm::ISD::AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:300
llvm::EVT::getSizeInBits
unsigned getSizeInBits() const
getSizeInBits - Return the size of the specified value type in bits.
Definition: ValueTypes.h:234
llvm::APInt::countTrailingOnes
unsigned countTrailingOnes() const
Count the number of trailing one bits.
Definition: APInt.h:1378
llvm::SelectionDAG::FoldSetCC
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, SDLoc dl)
FoldSetCC - Constant fold a setcc to true or false.
Definition: SelectionDAG.cpp:1811
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
llvm::APInt::getSignedMinValue
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
Definition: APInt.h:431
llvm::SelectionDAG::getSetCC
SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond)
Definition: SelectionDAG.h:690
llvm::TargetLoweringBase::BooleanContent
BooleanContent
Enum that describes how the target represents true/false values.
Definition: TargetLowering.h:109
llvm::ISD::TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:368
llvm::MemSDNode::getAlignment
unsigned getAlignment() const
Definition: SelectionDAGNodes.h:1064
llvm::TargetLoweringBase::isCondCodeLegal
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
Definition: TargetLowering.h:602
llvm::EVT::getIntegerVT
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Definition: ValueTypes.h:62
llvm::TargetLoweringBase::getCondCodeAction
LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const
Definition: TargetLowering.h:589
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Definition: ValueTypes.h:204
void TargetLowering::softenSetCCOperands ( SelectionDAG &  DAG,
EVT  VT,
SDValue &  NewLHS,
SDValue &  NewRHS,
ISD::CondCode &  CCCode,
SDLoc  dl 
) const
inherited

SoftenSetCCOperands - Soften the operands of a comparison. This code is shared among BR_CC, SELECT_CC, and SETCC handlers.

Definition at line 117 of file TargetLowering.cpp.

120  {
121  assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
122  && "Unsupported setcc type!");
123 
124  // Expand into one or more soft-fp libcall(s).
125  RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
126  switch (CCCode) {
127  case ISD::SETEQ:
128  case ISD::SETOEQ:
129  LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
130  (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
131  break;
132  case ISD::SETNE:
133  case ISD::SETUNE:
134  LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
135  (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
136  break;
137  case ISD::SETGE:
138  case ISD::SETOGE:
139  LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
140  (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
141  break;
142  case ISD::SETLT:
143  case ISD::SETOLT:
144  LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
145  (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
146  break;
147  case ISD::SETLE:
148  case ISD::SETOLE:
149  LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
150  (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
151  break;
152  case ISD::SETGT:
153  case ISD::SETOGT:
154  LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
155  (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
156  break;
157  case ISD::SETUO:
158  LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
159  (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
160  break;
161  case ISD::SETO:
162  LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
163  (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
164  break;
165  default:
166  LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
167  (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
168  switch (CCCode) {
169  case ISD::SETONE:
170  // SETONE = SETOLT | SETOGT
171  LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
172  (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
173  // Fallthrough
174  case ISD::SETUGT:
175  LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
176  (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
177  break;
178  case ISD::SETUGE:
179  LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
180  (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
181  break;
182  case ISD::SETULT:
183  LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
184  (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
185  break;
186  case ISD::SETULE:
187  LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
188  (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
189  break;
190  case ISD::SETUEQ:
191  LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
192  (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
193  break;
194  default: llvm_unreachable("Do not know how to soften this setcc!");
195  }
196  }
197 
198  // Use the target specific return value for comparions lib calls.
199  EVT RetVT = getCmpLibcallReturnType();
200  SDValue Ops[2] = { NewLHS, NewRHS };
201  NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
202  dl).first;
203  NewRHS = DAG.getConstant(0, RetVT);
204  CCCode = getCmpLibcallCC(LC1);
205  if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
206  SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
207  getSetCCResultType(*DAG.getContext(), RetVT),
208  NewLHS, NewRHS, DAG.getCondCode(CCCode));
209  NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
210  dl).first;
211  NewLHS = DAG.getNode(ISD::SETCC, dl,
212  getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
213  NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
214  NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
215  NewRHS = SDValue();
216  }
217 }
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm_unreachable
#define llvm_unreachable(msg)
Definition: ErrorHandling.h:98
llvm::TargetLowering::makeLibCall
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const
Returns a pair of (return value, chain).
Definition: TargetLowering.cpp:86
llvm::TargetLoweringBase::getSetCCResultType
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const
Definition: TargetLoweringBase.cpp:1209
assert
assert(Globals.size() > 1)
llvm::TargetLoweringBase::getCmpLibcallCC
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const
Definition: TargetLowering.h:1437
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT)
Definition: SelectionDAG.cpp:2668
llvm::TargetLoweringBase::getCmpLibcallReturnType
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Definition: TargetLoweringBase.cpp:1214
llvm::SDValue::getValueType
EVT getValueType() const
Definition: SelectionDAGNodes.h:883
llvm::SelectionDAG::getCondCode
SDValue getCondCode(ISD::CondCode Cond)
Definition: SelectionDAG.cpp:1452
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, EVT VT, bool isTarget=false, bool isOpaque=false)
Definition: SelectionDAG.cpp:1091
bool llvm::TargetLoweringBase::supportJumpTables ( ) const
inlineinherited

Return whether the target can generate code for jump tables.

Definition at line 827 of file TargetLowering.h.

827  {
828  return SupportJumpTables;
829  }
bool llvm::TargetLoweringBase::usesUnderscoreLongJmp ( ) const
inlineinherited

Determine if we should use _longjmp or longjmp to implement llvm.longjmp.

Definition at line 822 of file TargetLowering.h.

822  {
823  return UseUnderscoreLongJmp;
824  }
bool llvm::TargetLoweringBase::usesUnderscoreSetJmp ( ) const
inlineinherited

Determine if we should use _setjmp or setjmp to implement llvm.setjmp.

Definition at line 817 of file TargetLowering.h.

817  {
818  return UseUnderscoreSetJmp;
819  }
bool TargetLowering::verifyReturnAddressArgumentIsConstant ( SDValue  Op,
SelectionDAG &  DAG 
) const
inherited

Definition at line 2772 of file TargetLowering.cpp.

2772  {
2773  if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2774  DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2775  "be a constant integer");
2776  return true;
2777  }
2778 
2779  return false;
2780 }
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:280
llvm::LLVMContext::emitError
void emitError(unsigned LocCookie, const Twine &ErrorStr)
Definition: LLVMContext.cpp:188
llvm::SDValue::getOperand
const SDValue & getOperand(unsigned i) const
Definition: SelectionDAGNodes.h:889

Field Documentation

std::vector<APFloat> llvm::X86TargetLowering::LegalFPImmediates
private

LegalFPImmediates - A list of legal fp immediates.

Definition at line 824 of file X86ISelLowering.h.

bool llvm::TargetLoweringBase::MaskAndBranchFoldingIsLegal
protectedinherited

MaskAndBranchFoldingIsLegal - Indicates if the target supports folding a mask of a single bit, a compare, and a branch into a single instruction.

Definition at line 1842 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpy
protectedinherited

Specify maximum bytes of store instructions per memcpy call.

When lowering @llvm.memcpy this field specifies the maximum number of store operations that may be substituted for a call to memcpy. Targets must set this value based on the cost threshold for that target. Targets should assume that the memcpy will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 7 bytes on a 32-bit machine with 32-bit alignment would result in one 4-byte store, a one 2-byte store and one 1-byte store. This only applies to copying a constant array of constant size.

Definition at line 1814 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemcpyOptSize
protectedinherited

Maximum number of store operations that may be substituted for a call to memcpy, used for functions with OptSize attribute.

Definition at line 1818 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemmove
protectedinherited

Specify maximum bytes of store instructions per memmove call.

When lowering @llvm.memmove this field specifies the maximum number of store instructions that may be substituted for a call to memmove. Targets must set this value based on the cost threshold for that target. Targets should assume that the memmove will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, moving 9 bytes on a 32-bit machine with 8-bit alignment would result in nine 1-byte stores. This only applies to copying a constant array of constant size.

Definition at line 1830 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemmoveOptSize
protectedinherited

Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OpSize attribute.

Definition at line 1834 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemset
protectedinherited

Specify maximum number of store instructions per memset call.

When lowering @llvm.memset this field specifies the maximum number of store operations that may be substituted for the call to memset. Targets must set this value based on the cost threshold for that target. Targets should assume that the memset will be done using as many of the largest store operations first, followed by smaller ones, if necessary, per alignment restrictions. For example, storing 9 bytes on a 32-bit machine with 16-bit alignment would result in four 2-byte stores and one 1-byte store. This only applies to setting a constant array of a constant size.

Definition at line 1797 of file TargetLowering.h.

unsigned llvm::TargetLoweringBase::MaxStoresPerMemsetOptSize
protectedinherited

Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.

Definition at line 1801 of file TargetLowering.h.

bool llvm::TargetLoweringBase::PredictableSelectIsExpensive
protectedinherited

Tells the code generator that select is more expensive than a branch if the branch is usually predicted right.

Definition at line 1838 of file TargetLowering.h.

const X86Subtarget* llvm::X86TargetLowering::Subtarget
private

Subtarget - Keep a pointer to the X86Subtarget around so that we can make the right decision when generating code for different targets.

Definition at line 809 of file X86ISelLowering.h.

const DataLayout* llvm::X86TargetLowering::TD
private

Definition at line 810 of file X86ISelLowering.h.

TargetOptions llvm::X86TargetLowering::TO
private

Used to store the TargetOptions so that we don't waste time resetting the operation actions unless we have to.

Definition at line 814 of file X86ISelLowering.h.

bool llvm::X86TargetLowering::X86ScalarSSEf32
private

X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 floating point ops. When SSE is available, use it for f32 operations. When SSE2 is available, use it for f64 operations.

Definition at line 820 of file X86ISelLowering.h.

bool llvm::X86TargetLowering::X86ScalarSSEf64
private

Definition at line 821 of file X86ISelLowering.h.

The documentation for this class was generated from the following files: